forked from ~ljy/RK356X_SDK_RELEASE

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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/clk/rockchip/clk-rk3368.c
....@@ -1,29 +1,19 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
3
- *
4
- * This program is free software; you can redistribute it and/or modify
5
- * it under the terms of the GNU General Public License as published by
6
- * the Free Software Foundation; either version 2 of the License, or
7
- * (at your option) any later version.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
134  */
145 
156 #include <linux/clk-provider.h>
7
+#include <linux/io.h>
8
+#include <linux/module.h>
169 #include <linux/of.h>
1710 #include <linux/of_address.h>
11
+#include <linux/of_device.h>
1812 #include <linux/platform_device.h>
1913 #include <dt-bindings/clock/rk3368-cru.h>
2014 #include "clk.h"
2115 
2216 #define RK3368_GRF_SOC_STATUS0	0x480
23
-#define RK3368_I2S_FRAC_MAX_PRATE       600000000
24
-#define RK3368_UART_FRAC_MAX_PRATE	600000000
25
-#define RK3368_SPDIF_FRAC_MAX_PRATE	600000000
26
-#define RK3368_DCLK_PARENT_MAX_PRATE	600000000
2717 
2818 enum rk3368_plls {
2919 	apllb, aplll, dpll, cpll, gpll, npll,
....@@ -71,7 +61,6 @@
7161 	RK3066_PLL_RATE(1248000000, 1, 52, 1),
7262 	RK3066_PLL_RATE(1224000000, 1, 51, 1),
7363 	RK3066_PLL_RATE(1200000000, 1, 50, 1),
74
-	RK3066_PLL_RATE(1188000000, 2, 99, 1),
7564 	RK3066_PLL_RATE(1176000000, 1, 49, 1),
7665 	RK3066_PLL_RATE(1128000000, 1, 47, 1),
7766 	RK3066_PLL_RATE(1104000000, 1, 46, 1),
....@@ -119,8 +108,6 @@
119108 };
120109 
121110 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
122
-PNAME(mux_armclkb_p)		= { "apllb_core", "gpllb_core" };
123
-PNAME(mux_armclkl_p)		= { "aplll_core", "gplll_core" };
124111 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
125112 PNAME(mux_cs_src_p)		= { "apllb_cs", "aplll_cs", "gpll_cs"};
126113 PNAME(mux_aclk_bus_src_p)	= { "cpll_aclk_bus", "gpll_aclk_bus" };
....@@ -143,7 +130,7 @@
143130 PNAME(mux_i2s_8ch_clkout_p)	= { "i2s_8ch_pre", "xin12m" };
144131 PNAME(mux_i2s_2ch_p)		= { "i2s_2ch_src", "i2s_2ch_frac",
145132 				    "dummy", "xin12m" };
146
-PNAME(mux_spdif_8ch_p)		= { "spdif_8ch_src", "spdif_8ch_frac",
133
+PNAME(mux_spdif_8ch_p)		= { "spdif_8ch_pre", "spdif_8ch_frac",
147134 				    "ext_i2s", "xin12m" };
148135 PNAME(mux_edp_24m_p)		= { "xin24m", "dummy" };
149136 PNAME(mux_vip_out_p)		= { "vip_src", "xin24m" };
....@@ -166,7 +153,7 @@
166153 	[dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3368_PLL_CON(8),
167154 		     RK3368_PLL_CON(11), 8, 2, 0, NULL),
168155 	[cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK3368_PLL_CON(12),
169
-		     RK3368_PLL_CON(15), 8, 3, 0, rk3368_pll_rates),
156
+		     RK3368_PLL_CON(15), 8, 3, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
170157 	[gpll] = PLL(pll_rk3066, PLL_GPLL, "gpll", mux_pll_p, 0, RK3368_PLL_CON(16),
171158 		     RK3368_PLL_CON(19), 8, 4, ROCKCHIP_PLL_SYNC_RATE, rk3368_pll_rates),
172159 	[npll] = PLL(pll_rk3066, PLL_NPLL, "npll",  mux_pll_p, 0, RK3368_PLL_CON(20),
....@@ -253,7 +240,6 @@
253240 	RK3368_CPUCLKB_RATE(1512000000, 1, 5, 5),
254241 	RK3368_CPUCLKB_RATE(1488000000, 1, 4, 4),
255242 	RK3368_CPUCLKB_RATE(1416000000, 1, 4, 4),
256
-	RK3368_CPUCLKL_RATE(1296000000, 1, 4, 4),
257243 	RK3368_CPUCLKB_RATE(1200000000, 1, 3, 3),
258244 	RK3368_CPUCLKB_RATE(1008000000, 1, 3, 3),
259245 	RK3368_CPUCLKB_RATE( 816000000, 1, 2, 2),
....@@ -261,15 +247,12 @@
261247 	RK3368_CPUCLKB_RATE( 600000000, 1, 1, 1),
262248 	RK3368_CPUCLKB_RATE( 408000000, 1, 1, 1),
263249 	RK3368_CPUCLKB_RATE( 312000000, 1, 1, 1),
264
-	RK3368_CPUCLKB_RATE( 216000000, 1, 1, 1),
265
-	RK3368_CPUCLKB_RATE( 126000000, 1, 1, 1),
266250 };
267251 
268252 static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
269253 	RK3368_CPUCLKL_RATE(1512000000, 1, 6, 6),
270254 	RK3368_CPUCLKL_RATE(1488000000, 1, 5, 5),
271255 	RK3368_CPUCLKL_RATE(1416000000, 1, 5, 5),
272
-	RK3368_CPUCLKL_RATE(1296000000, 1, 5, 5),
273256 	RK3368_CPUCLKL_RATE(1200000000, 1, 4, 4),
274257 	RK3368_CPUCLKL_RATE(1008000000, 1, 4, 4),
275258 	RK3368_CPUCLKL_RATE( 816000000, 1, 3, 3),
....@@ -277,8 +260,6 @@
277260 	RK3368_CPUCLKL_RATE( 600000000, 1, 2, 2),
278261 	RK3368_CPUCLKL_RATE( 408000000, 1, 1, 1),
279262 	RK3368_CPUCLKL_RATE( 312000000, 1, 1, 1),
280
-	RK3368_CPUCLKL_RATE( 216000000, 1, 1, 1),
281
-	RK3368_CPUCLKL_RATE( 126000000, 1, 1, 1),
282263 };
283264 
284265 static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
....@@ -364,9 +345,6 @@
364345 			RK3368_CLKGATE_CON(1), 8, GFLAGS),
365346 	GATE(0, "gpll_ddr", "gpll", 0,
366347 			RK3368_CLKGATE_CON(1), 9, GFLAGS),
367
-	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddrphy_p, 0,
368
-			RK3368_CLKSEL_CON(13), 4, 1, 0, 0, ROCKCHIP_DDRCLK_SCPI),
369
-
370348 	COMPOSITE_NOGATE_DIVTBL(0, "ddrphy_src", mux_ddrphy_p, CLK_IGNORE_UNUSED,
371349 			RK3368_CLKSEL_CON(13), 4, 1, MFLAGS, 0, 2, DFLAGS, div_ddrphy_t),
372350 
....@@ -375,22 +353,22 @@
375353 	GATE(0, "sclk_ddr4x", "ddrphy_src", CLK_IGNORE_UNUSED,
376354 			RK3368_CLKGATE_CON(6), 15, GFLAGS),
377355 
378
-	GATE(0, "gpll_aclk_bus", "gpll", CLK_IGNORE_UNUSED,
356
+	GATE(0, "gpll_aclk_bus", "gpll", CLK_IS_CRITICAL,
379357 			RK3368_CLKGATE_CON(1), 10, GFLAGS),
380
-	GATE(0, "cpll_aclk_bus", "cpll", CLK_IGNORE_UNUSED,
358
+	GATE(0, "cpll_aclk_bus", "cpll", CLK_IS_CRITICAL,
381359 			RK3368_CLKGATE_CON(1), 11, GFLAGS),
382
-	COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IGNORE_UNUSED,
360
+	COMPOSITE_NOGATE(0, "aclk_bus_src", mux_aclk_bus_src_p, CLK_IS_CRITICAL,
383361 			RK3368_CLKSEL_CON(8), 7, 1, MFLAGS, 0, 5, DFLAGS),
384362 
385
-	GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
363
+	GATE(ACLK_BUS, "aclk_bus", "aclk_bus_src", CLK_IS_CRITICAL,
386364 			RK3368_CLKGATE_CON(1), 0, GFLAGS),
387
-	COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
365
+	COMPOSITE_NOMUX(PCLK_BUS, "pclk_bus", "aclk_bus_src", CLK_IS_CRITICAL,
388366 			RK3368_CLKSEL_CON(8), 12, 3, DFLAGS,
389367 			RK3368_CLKGATE_CON(1), 2, GFLAGS),
390
-	COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IGNORE_UNUSED,
368
+	COMPOSITE_NOMUX(HCLK_BUS, "hclk_bus", "aclk_bus_src", CLK_IS_CRITICAL,
391369 			RK3368_CLKSEL_CON(8), 8, 2, DFLAGS,
392370 			RK3368_CLKGATE_CON(1), 1, GFLAGS),
393
-	COMPOSITE_NOMUX(SCLK_CRYPTO, "sclk_crypto", "aclk_bus_src", 0,
371
+	COMPOSITE_NOMUX(0, "sclk_crypto", "aclk_bus_src", 0,
394372 			RK3368_CLKSEL_CON(10), 14, 2, DFLAGS,
395373 			RK3368_CLKGATE_CON(7), 2, GFLAGS),
396374 
....@@ -411,7 +389,7 @@
411389 	COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
412390 			  RK3368_CLKSEL_CON(28), 0,
413391 			  RK3368_CLKGATE_CON(6), 2, GFLAGS,
414
-			  &rk3368_i2s_8ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE),
392
+			  &rk3368_i2s_8ch_fracmux),
415393 	COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
416394 			RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
417395 			RK3368_CLKGATE_CON(6), 0, GFLAGS),
....@@ -423,7 +401,7 @@
423401 	COMPOSITE_FRACMUX(0, "spdif_8ch_frac", "spdif_8ch_src", CLK_SET_RATE_PARENT,
424402 			  RK3368_CLKSEL_CON(32), 0,
425403 			  RK3368_CLKGATE_CON(6), 5, GFLAGS,
426
-			  &rk3368_spdif_8ch_fracmux, RK3368_SPDIF_FRAC_MAX_PRATE),
404
+			  &rk3368_spdif_8ch_fracmux),
427405 	GATE(SCLK_SPDIF_8CH, "sclk_spdif_8ch", "spdif_8ch_pre", CLK_SET_RATE_PARENT,
428406 	     RK3368_CLKGATE_CON(6), 6, GFLAGS),
429407 	COMPOSITE(0, "i2s_2ch_src", mux_pll_src_cpll_gpll_p, 0,
....@@ -432,14 +410,14 @@
432410 	COMPOSITE_FRACMUX(0, "i2s_2ch_frac", "i2s_2ch_src", CLK_SET_RATE_PARENT,
433411 			  RK3368_CLKSEL_CON(54), 0,
434412 			  RK3368_CLKGATE_CON(5), 14, GFLAGS,
435
-			  &rk3368_i2s_2ch_fracmux, RK3368_I2S_FRAC_MAX_PRATE),
413
+			  &rk3368_i2s_2ch_fracmux),
436414 	GATE(SCLK_I2S_2CH, "sclk_i2s_2ch", "i2s_2ch_pre", CLK_SET_RATE_PARENT,
437415 	     RK3368_CLKGATE_CON(5), 15, GFLAGS),
438416 
439
-	COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
417
+	COMPOSITE(0, "sclk_tsp", mux_pll_src_cpll_gpll_npll_p, 0,
440418 			RK3368_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
441419 			RK3368_CLKGATE_CON(6), 12, GFLAGS),
442
-	GATE(SCLK_HSADC_TSP, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
420
+	GATE(0, "sclk_hsadc_tsp", "ext_hsadc_tsp", 0,
443421 			RK3368_CLKGATE_CON(13), 7, GFLAGS),
444422 
445423 	MUX(0, "uart_src", mux_pll_src_cpll_gpll_p, 0,
....@@ -481,16 +459,16 @@
481459 	DIV(0, "hclk_vio", "aclk_vio0", 0,
482460 			RK3368_CLKSEL_CON(21), 0, 5, DFLAGS),
483461 
484
-	COMPOSITE(ACLK_RGA, "aclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
462
+	COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_usb_p, 0,
485463 			RK3368_CLKSEL_CON(18), 14, 2, MFLAGS, 8, 5, DFLAGS,
486464 			RK3368_CLKGATE_CON(4), 3, GFLAGS),
487465 	COMPOSITE(SCLK_RGA, "sclk_rga", mux_pll_src_cpll_gpll_usb_p, 0,
488466 			RK3368_CLKSEL_CON(18), 6, 2, MFLAGS, 0, 5, DFLAGS,
489467 			RK3368_CLKGATE_CON(4), 4, GFLAGS),
490468 
491
-	COMPOSITE_DCLK(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT,
469
+	COMPOSITE(DCLK_VOP, "dclk_vop", mux_pll_src_dmycpll_dmygpll_npll_p, CLK_SET_RATE_PARENT,
492470 			RK3368_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
493
-			RK3368_CLKGATE_CON(4), 1, GFLAGS, RK3368_DCLK_PARENT_MAX_PRATE),
471
+			RK3368_CLKGATE_CON(4), 1, GFLAGS),
494472 
495473 	GATE(SCLK_VOP0_PWM, "sclk_vop0_pwm", "xin24m", 0,
496474 			RK3368_CLKGATE_CON(4), 2, GFLAGS),
....@@ -514,10 +492,10 @@
514492 	GATE(SCLK_HDMI_CEC, "sclk_hdmi_cec", "xin32k", 0,
515493 			RK3368_CLKGATE_CON(4), 12, GFLAGS),
516494 
517
-	COMPOSITE_NODIV(SCLK_VIP_SRC, "vip_src", mux_pll_src_cpll_gpll_p, 0,
495
+	COMPOSITE_NODIV(0, "vip_src", mux_pll_src_cpll_gpll_p, 0,
518496 			RK3368_CLKSEL_CON(21), 15, 1, MFLAGS,
519497 			RK3368_CLKGATE_CON(4), 5, GFLAGS),
520
-	COMPOSITE_NOGATE(SCLK_VIP_OUT, "sclk_vip_out", mux_vip_out_p, 0,
498
+	COMPOSITE_NOGATE(0, "sclk_vip_out", mux_vip_out_p, 0,
521499 			RK3368_CLKSEL_CON(21), 14, 1, MFLAGS, 8, 5, DFLAGS),
522500 
523501 	COMPOSITE_NODIV(SCLK_EDP_24M, "sclk_edp_24m", mux_edp_24m_p, 0,
....@@ -531,12 +509,12 @@
531509 			RK3368_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 6, DFLAGS,
532510 			RK3368_CLKGATE_CON(5), 5, GFLAGS),
533511 
534
-	DIV(0, "pclk_pd_alive", "gpll", 0,
512
+	DIV(0, "pclk_pd_alive", "gpll", CLK_IS_CRITICAL,
535513 			RK3368_CLKSEL_CON(10), 8, 5, DFLAGS),
536514 
537515 	/* sclk_timer has a gate in the sgrf */
538516 
539
-	COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IGNORE_UNUSED,
517
+	COMPOSITE_NOMUX(0, "pclk_pd_pmu", "gpll", CLK_IS_CRITICAL,
540518 			RK3368_CLKSEL_CON(10), 0, 5, DFLAGS,
541519 			RK3368_CLKGATE_CON(7), 9, GFLAGS),
542520 	GATE(SCLK_PVTM_PMU, "sclk_pvtm_pmu", "xin24m", 0,
....@@ -555,19 +533,19 @@
555533 	GATE(SCLK_PVTM_GPU, "sclk_pvtm_gpu", "xin24m", 0,
556534 			RK3368_CLKGATE_CON(7), 11, GFLAGS),
557535 
558
-	COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
536
+	COMPOSITE(0, "aclk_peri_src", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
559537 			RK3368_CLKSEL_CON(9), 7, 1, MFLAGS, 0, 5, DFLAGS,
560538 			RK3368_CLKGATE_CON(3), 0, GFLAGS),
561
-	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", 0,
539
+	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
562540 			RK3368_CLKSEL_CON(9), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
563541 			RK3368_CLKGATE_CON(3), 3, GFLAGS),
564
-	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
542
+	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
565543 			RK3368_CLKSEL_CON(9), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
566544 			RK3368_CLKGATE_CON(3), 2, GFLAGS),
567
-	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IGNORE_UNUSED,
545
+	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
568546 			RK3368_CLKGATE_CON(3), 1, GFLAGS),
569547 
570
-	GATE(SCLK_MIPIDSI_24M, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
548
+	GATE(0, "sclk_mipidsi_24m", "xin24m", 0, RK3368_CLKGATE_CON(4), 14, GFLAGS),
571549 
572550 	/*
573551 	 * Clock-Architecture Diagram 4
....@@ -603,7 +581,7 @@
603581 	MMC(SCLK_EMMC_DRV,     "emmc_drv",     "sclk_emmc",  RK3368_EMMC_CON0,  1),
604582 	MMC(SCLK_EMMC_SAMPLE,  "emmc_sample",  "sclk_emmc",  RK3368_EMMC_CON1,  0),
605583 
606
-	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
584
+	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", CLK_IGNORE_UNUSED,
607585 			RK3368_CLKGATE_CON(8), 1, GFLAGS),
608586 
609587 	/* pmu_grf_soc_con0[6] allows to select between xin32k and pvtm_pmu */
....@@ -633,7 +611,7 @@
633611 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
634612 			  RK3368_CLKSEL_CON(34), 0,
635613 			  RK3368_CLKGATE_CON(2), 1, GFLAGS,
636
-			  &rk3368_uart0_fracmux, RK3368_UART_FRAC_MAX_PRATE),
614
+			  &rk3368_uart0_fracmux),
637615 
638616 	COMPOSITE_NOMUX(0, "uart1_src", "uart_src", 0,
639617 			RK3368_CLKSEL_CON(35), 0, 7, DFLAGS,
....@@ -641,7 +619,7 @@
641619 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
642620 			  RK3368_CLKSEL_CON(36), 0,
643621 			  RK3368_CLKGATE_CON(2), 3, GFLAGS,
644
-			  &rk3368_uart1_fracmux, RK3368_UART_FRAC_MAX_PRATE),
622
+			  &rk3368_uart1_fracmux),
645623 
646624 	COMPOSITE_NOMUX(0, "uart3_src", "uart_src", 0,
647625 			RK3368_CLKSEL_CON(39), 0, 7, DFLAGS,
....@@ -649,7 +627,7 @@
649627 	COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_src", CLK_SET_RATE_PARENT,
650628 			  RK3368_CLKSEL_CON(40), 0,
651629 			  RK3368_CLKGATE_CON(2), 7, GFLAGS,
652
-			  &rk3368_uart3_fracmux, RK3368_UART_FRAC_MAX_PRATE),
630
+			  &rk3368_uart3_fracmux),
653631 
654632 	COMPOSITE_NOMUX(0, "uart4_src", "uart_src", 0,
655633 			RK3368_CLKSEL_CON(41), 0, 7, DFLAGS,
....@@ -657,7 +635,7 @@
657635 	COMPOSITE_FRACMUX(0, "uart4_frac", "uart4_src", CLK_SET_RATE_PARENT,
658636 			  RK3368_CLKSEL_CON(42), 0,
659637 			  RK3368_CLKGATE_CON(2), 9, GFLAGS,
660
-			  &rk3368_uart4_fracmux, RK3368_UART_FRAC_MAX_PRATE),
638
+			  &rk3368_uart4_fracmux),
661639 
662640 	COMPOSITE(0, "mac_pll_src", mux_pll_src_npll_cpll_gpll_p, 0,
663641 			RK3368_CLKSEL_CON(43), 6, 2, MFLAGS, 0, 5, DFLAGS,
....@@ -711,7 +689,7 @@
711689 
712690 	/* aclk_bus gates */
713691 	GATE(0, "aclk_strc_sys", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 12, GFLAGS),
714
-	GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", 0, RK3368_CLKGATE_CON(12), 11, GFLAGS),
692
+	GATE(ACLK_DMAC_BUS, "aclk_dmac_bus", "aclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(12), 11, GFLAGS),
715693 	GATE(0, "sclk_intmem1", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 6, GFLAGS),
716694 	GATE(0, "sclk_intmem0", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 5, GFLAGS),
717695 	GATE(0, "aclk_intmem", "aclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 4, GFLAGS),
....@@ -737,17 +715,17 @@
737715 	GATE(MCLK_CRYPTO, "mclk_crypto", "hclk_bus", 0, RK3368_CLKGATE_CON(13), 3, GFLAGS),
738716 
739717 	/* pclk_cpu gates */
740
-	GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 14, GFLAGS),
741
-	GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 13, GFLAGS),
718
+	GATE(PCLK_DDRPHY, "pclk_ddrphy", "pclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(12), 14, GFLAGS),
719
+	GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(12), 13, GFLAGS),
742720 	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 3, GFLAGS),
743721 	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 2, GFLAGS),
744722 	GATE(PCLK_MAILBOX, "pclk_mailbox", "pclk_bus", 0, RK3368_CLKGATE_CON(12), 1, GFLAGS),
745723 	GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
746724 	GATE(PCLK_SIM, "pclk_sim", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 8, GFLAGS),
747
-	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 6, GFLAGS),
725
+	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(13), 6, GFLAGS),
748726 	GATE(PCLK_UART2, "pclk_uart2", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 5, GFLAGS),
749727 	GATE(PCLK_EFUSE256, "pclk_efuse_256", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 1, GFLAGS),
750
-	GATE(PCLK_EFUSE1024, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
728
+	GATE(0, "pclk_efuse_1024", "pclk_bus", 0, RK3368_CLKGATE_CON(13), 0, GFLAGS),
751729 
752730 	/*
753731 	 * video clk gates
....@@ -759,9 +737,10 @@
759737 	GATE(SCLK_HEVC_CORE, "sclk_hevc_core", "sclk_hevc_core_src", 0, RK3368_CLKGATE_CON(15), 2, GFLAGS),
760738 	GATE(HCLK_VIDEO, "hclk_video", "hclk_video_pre", 0, RK3368_CLKGATE_CON(15), 1, GFLAGS),
761739 
762
-	/* aclk_rga gates */
763
-	GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
764
-	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
740
+	/* aclk_rga_pre gates */
741
+	GATE(ACLK_VIO1_NOC, "aclk_vio1_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(16), 10, GFLAGS),
742
+	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(16), 0, GFLAGS),
743
+	GATE(ACLK_HDCP, "aclk_hdcp", "aclk_rga_pre", 0, RK3368_CLKGATE_CON(17), 10, GFLAGS),
765744 
766745 	/* aclk_vio0 gates */
767746 	GATE(ACLK_VIP, "aclk_vip", "aclk_vio0", 0, RK3368_CLKGATE_CON(16), 11, GFLAGS),
....@@ -772,7 +751,7 @@
772751 
773752 	/* sclk_isp gates */
774753 	GATE(HCLK_ISP, "hclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(16), 14, GFLAGS),
775
-	FACTOR(ACLK_ISP, "aclk_isp", "sclk_isp", CLK_SET_RATE_PARENT, 1, 1),
754
+	GATE(ACLK_ISP, "aclk_isp", "sclk_isp", 0, RK3368_CLKGATE_CON(17), 0, GFLAGS),
776755 
777756 	/* hclk_vio gates */
778757 	GATE(HCLK_VIP, "hclk_vip", "hclk_vio", 0, RK3368_CLKGATE_CON(16), 12, GFLAGS),
....@@ -816,12 +795,12 @@
816795 	GATE(0, "hclk_mmc_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 10, GFLAGS),
817796 	GATE(0, "hclk_emem_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 9, GFLAGS),
818797 	GATE(0, "hclk_peri_ahb_arbi", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 7, GFLAGS),
819
-	GATE(HCLK_USB_PERI, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
798
+	GATE(0, "hclk_usb_peri", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 6, GFLAGS),
820799 	GATE(HCLK_HSIC, "hclk_hsic", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 5, GFLAGS),
821800 	GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 4, GFLAGS),
822801 	GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 3, GFLAGS),
823
-	GATE(0, "pmu_hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 2, GFLAGS),
824
-	GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", 0, RK3368_CLKGATE_CON(20), 1, GFLAGS),
802
+	GATE(0, "pmu_hclk_otg0", "hclk_peri", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(20), 2, GFLAGS),
803
+	GATE(HCLK_OTG0, "hclk_otg0", "hclk_peri", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(20), 1, GFLAGS),
825804 	GATE(HCLK_HSADC, "hclk_hsadc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 3, GFLAGS),
826805 	GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 2, GFLAGS),
827806 	GATE(HCLK_SDIO0, "hclk_sdio0", "hclk_peri", 0, RK3368_CLKGATE_CON(21), 1, GFLAGS),
....@@ -847,18 +826,21 @@
847826 	/* pclk_pd_alive gates */
848827 	GATE(PCLK_TIMER1, "pclk_timer1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 13, GFLAGS),
849828 	GATE(PCLK_TIMER0, "pclk_timer0", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 12, GFLAGS),
850
-	GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 9, GFLAGS),
851
-	GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(22), 8, GFLAGS),
829
+	GATE(0, "pclk_alive_niu", "pclk_pd_alive", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(22), 9, GFLAGS),
830
+	GATE(PCLK_GRF, "pclk_grf", "pclk_pd_alive", CLK_IS_CRITICAL, RK3368_CLKGATE_CON(22), 8, GFLAGS),
852831 	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 3, GFLAGS),
853832 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 2, GFLAGS),
854833 	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_pd_alive", 0, RK3368_CLKGATE_CON(22), 1, GFLAGS),
834
+
835
+	/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
836
+	SGRF_GATE(PCLK_WDT, "pclk_wdt", "pclk_pd_alive"),
855837 
856838 	/*
857839 	 * pclk_vio gates
858840 	 * pclk_vio comes from the exactly same source as hclk_vio
859841 	 */
860
-	GATE(PCLK_DPHYRX, "pclk_dphyrx", "hclk_vio", 0, RK3368_CLKGATE_CON(22), 11, GFLAGS),
861
-	GATE(PCLK_DPHYTX0, "pclk_dphytx", "hclk_vio", 0, RK3368_CLKGATE_CON(22), 10, GFLAGS),
842
+	GATE(0, "pclk_dphyrx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
843
+	GATE(0, "pclk_dphytx", "hclk_vio", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(14), 8, GFLAGS),
862844 
863845 	/* pclk_pd_pmu gates */
864846 	GATE(PCLK_PMUGRF, "pclk_pmugrf", "pclk_pd_pmu", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(23), 5, GFLAGS),
....@@ -883,24 +865,6 @@
883865 	GATE(SCLK_TIMER00, "sclk_timer00", "xin24m", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(24), 0, GFLAGS),
884866 };
885867 
886
-static const char *const rk3368_critical_clocks[] __initconst = {
887
-	"aclk_bus",
888
-	"aclk_peri",
889
-	/*
890
-	 * pwm1 supplies vdd_logic on a lot of boards, is currently unhandled
891
-	 * but needs to stay enabled there (including its parents) at all times.
892
-	 */
893
-	"pclk_pwm1",
894
-	"pclk_pd_pmu",
895
-	"pclk_pd_alive",
896
-	"pclk_peri",
897
-	"hclk_peri",
898
-	"pclk_ddrphy",
899
-	"pclk_ddrupctl",
900
-	"pmu_hclk_otg0",
901
-	"aclk_dmac_bus",
902
-};
903
-
904868 static void __iomem *rk3368_cru_base;
905869 
906870 static void rk3368_dump_cru(void)
....@@ -917,7 +881,7 @@
917881 {
918882 	struct rockchip_clk_provider *ctx;
919883 	void __iomem *reg_base;
920
-	struct clk *clk;
884
+	struct clk **clks;
921885 
922886 	reg_base = of_iomap(np, 0);
923887 	if (!reg_base) {
....@@ -931,30 +895,21 @@
931895 		iounmap(reg_base);
932896 		return;
933897 	}
934
-
935
-	/* Watchdog pclk is controlled by sgrf_soc_con3[7]. */
936
-	clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_pd_alive", 0, 1, 1);
937
-	if (IS_ERR(clk))
938
-		pr_warn("%s: could not register clock pclk_wdt: %ld\n",
939
-			__func__, PTR_ERR(clk));
940
-	else
941
-		rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
898
+	clks = ctx->clk_data.clks;
942899 
943900 	rockchip_clk_register_plls(ctx, rk3368_pll_clks,
944901 				   ARRAY_SIZE(rk3368_pll_clks),
945902 				   RK3368_GRF_SOC_STATUS0);
946903 	rockchip_clk_register_branches(ctx, rk3368_clk_branches,
947904 				  ARRAY_SIZE(rk3368_clk_branches));
948
-	rockchip_clk_protect_critical(rk3368_critical_clocks,
949
-				      ARRAY_SIZE(rk3368_critical_clocks));
950905 
951906 	rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
952
-			mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
907
+			2, clks[PLL_APLLB], clks[PLL_GPLL],
953908 			&rk3368_cpuclkb_data, rk3368_cpuclkb_rates,
954909 			ARRAY_SIZE(rk3368_cpuclkb_rates));
955910 
956911 	rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
957
-			mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
912
+			2, clks[PLL_APLLL], clks[PLL_GPLL],
958913 			&rk3368_cpuclkl_data, rk3368_cpuclkl_rates,
959914 			ARRAY_SIZE(rk3368_cpuclkl_rates));
960915 
....@@ -971,3 +926,31 @@
971926 	}
972927 }
973928 CLK_OF_DECLARE(rk3368_cru, "rockchip,rk3368-cru", rk3368_clk_init);
929
+
930
+static int __init clk_rk3368_probe(struct platform_device *pdev)
931
+{
932
+	struct device_node *np = pdev->dev.of_node;
933
+
934
+	rk3368_clk_init(np);
935
+
936
+	return 0;
937
+}
938
+
939
+static const struct of_device_id clk_rk3368_match_table[] = {
940
+	{
941
+		.compatible = "rockchip,rk3368-cru",
942
+	},
943
+	{ }
944
+};
945
+MODULE_DEVICE_TABLE(of, clk_rk3368_match_table);
946
+
947
+static struct platform_driver clk_rk3368_driver = {
948
+	.driver		= {
949
+		.name	= "clk-rk3368",
950
+		.of_match_table = clk_rk3368_match_table,
951
+	},
952
+};
953
+builtin_platform_driver_probe(clk_rk3368_driver, clk_rk3368_probe);
954
+
955
+MODULE_DESCRIPTION("Rockchip RK3368 Clock Driver");
956
+MODULE_LICENSE("GPL");