forked from ~ljy/RK356X_SDK_RELEASE

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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/clk/rockchip/clk-rk3188.c
....@@ -1,31 +1,21 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2014 MundoReader S.L.
34  * Author: Heiko Stuebner <heiko@sntech.de>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
145  */
156 
167 #include <linux/clk.h>
8
+#include <linux/module.h>
179 #include <linux/clk-provider.h>
10
+#include <linux/io.h>
1811 #include <linux/of.h>
1912 #include <linux/of_address.h>
13
+#include <linux/of_device.h>
2014 #include <dt-bindings/clock/rk3188-cru-common.h>
2115 #include "clk.h"
2216 
2317 #define RK3066_GRF_SOC_STATUS	0x15c
2418 #define RK3188_GRF_SOC_STATUS	0xac
25
-#define RK3188_UART_FRAC_MAX_PRATE	600000000
26
-#define RK3188_I2S_FRAC_MAX_PRATE	600000000
27
-#define RK3188_SPDIF_FRAC_MAX_PRATE	600000000
28
-#define RK3188_HSADC_FRAC_MAX_PRATE	300000000
2919 
3020 enum rk3188_plls {
3121 	apll, cpll, dpll, gpll,
....@@ -208,7 +198,6 @@
208198 };
209199 
210200 PNAME(mux_pll_p)		= { "xin24m", "xin32k" };
211
-PNAME(mux_armclk_p)		= { "apll", "gpll_armclk" };
212201 PNAME(mux_ddrphy_p)		= { "dpll", "gpll_ddr" };
213202 PNAME(mux_pll_src_gpll_cpll_p)	= { "gpll", "cpll" };
214203 PNAME(mux_pll_src_cpll_gpll_p)	= { "cpll", "gpll" };
....@@ -313,14 +302,14 @@
313302 			RK2928_CLKSEL_CON(26), 8, 1, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
314303 			RK2928_CLKGATE_CON(0), 2, GFLAGS),
315304 
316
-	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", 0,
305
+	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_pre", CLK_IS_CRITICAL,
317306 			RK2928_CLKGATE_CON(0), 3, GFLAGS),
318307 
319308 	GATE(0, "atclk_cpu", "pclk_cpu_pre", 0,
320309 			RK2928_CLKGATE_CON(0), 6, GFLAGS),
321
-	GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", 0,
310
+	GATE(PCLK_CPU, "pclk_cpu", "pclk_cpu_pre", CLK_IS_CRITICAL,
322311 			RK2928_CLKGATE_CON(0), 5, GFLAGS),
323
-	GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IGNORE_UNUSED,
312
+	GATE(HCLK_CPU, "hclk_cpu", "hclk_cpu_pre", CLK_IS_CRITICAL,
324313 			RK2928_CLKGATE_CON(0), 4, GFLAGS),
325314 
326315 	COMPOSITE(0, "aclk_lcdc0_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
....@@ -330,12 +319,12 @@
330319 			RK2928_CLKSEL_CON(31), 15, 1, MFLAGS, 8, 5, DFLAGS,
331320 			RK2928_CLKGATE_CON(1), 4, GFLAGS),
332321 
333
-	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", 0,
322
+	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
334323 			RK2928_CLKGATE_CON(2), 1, GFLAGS),
335
-	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", 0,
324
+	COMPOSITE_NOMUX(HCLK_PERI, "hclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
336325 			RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
337326 			RK2928_CLKGATE_CON(2), 2, GFLAGS),
338
-	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", 0,
327
+	COMPOSITE_NOMUX(PCLK_PERI, "pclk_peri", "aclk_peri_pre", CLK_IS_CRITICAL,
339328 			RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO,
340329 			RK2928_CLKGATE_CON(2), 3, GFLAGS),
341330 
....@@ -349,7 +338,7 @@
349338 
350339 	GATE(0, "pclkin_cif0", "ext_cif0", 0,
351340 			RK2928_CLKGATE_CON(3), 3, GFLAGS),
352
-	INVERTER(PCLK_CIF0, "pclk_cif0", "pclkin_cif0",
341
+	INVERTER(0, "pclk_cif0", "pclkin_cif0",
353342 			RK2928_CLKSEL_CON(30), 8, IFLAGS),
354343 
355344 	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
....@@ -368,7 +357,7 @@
368357 			RK2928_CLKGATE_CON(2), 5, GFLAGS),
369358 	MUX(SCLK_MAC, "sclk_macref", mux_sclk_macref_p, CLK_SET_RATE_PARENT,
370359 			RK2928_CLKSEL_CON(21), 4, 1, MFLAGS),
371
-	GATE(0, "sclk_mac_lbtest", "sclk_macref", 0,
360
+	GATE(0, "sclk_mac_lbtest", "sclk_macref", CLK_IS_CRITICAL,
372361 			RK2928_CLKGATE_CON(2), 12, GFLAGS),
373362 
374363 	COMPOSITE(0, "hsadc_src", mux_pll_src_gpll_cpll_p, 0,
....@@ -377,7 +366,7 @@
377366 	COMPOSITE_FRACMUX(0, "hsadc_frac", "hsadc_src", 0,
378367 			RK2928_CLKSEL_CON(23), 0,
379368 			RK2928_CLKGATE_CON(2), 7, GFLAGS,
380
-			&common_hsadc_out_fracmux, RK3188_HSADC_FRAC_MAX_PRATE),
369
+			&common_hsadc_out_fracmux),
381370 	INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
382371 			RK2928_CLKSEL_CON(22), 7, IFLAGS),
383372 
....@@ -391,7 +380,7 @@
391380 	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_pre", CLK_SET_RATE_PARENT,
392381 			RK2928_CLKSEL_CON(9), 0,
393382 			RK2928_CLKGATE_CON(0), 14, GFLAGS,
394
-			&common_spdif_fracmux, RK3188_SPDIF_FRAC_MAX_PRATE),
383
+			&common_spdif_fracmux),
395384 
396385 	/*
397386 	 * Clock-Architecture Diagram 4
....@@ -425,28 +414,28 @@
425414 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_pre", 0,
426415 			RK2928_CLKSEL_CON(17), 0,
427416 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
428
-			&common_uart0_fracmux, RK3188_UART_FRAC_MAX_PRATE),
417
+			&common_uart0_fracmux),
429418 	COMPOSITE_NOMUX(0, "uart1_pre", "uart_src", 0,
430419 			RK2928_CLKSEL_CON(14), 0, 7, DFLAGS,
431420 			RK2928_CLKGATE_CON(1), 10, GFLAGS),
432421 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_pre", 0,
433422 			RK2928_CLKSEL_CON(18), 0,
434423 			RK2928_CLKGATE_CON(1), 11, GFLAGS,
435
-			&common_uart1_fracmux, RK3188_UART_FRAC_MAX_PRATE),
424
+			&common_uart1_fracmux),
436425 	COMPOSITE_NOMUX(0, "uart2_pre", "uart_src", 0,
437426 			RK2928_CLKSEL_CON(15), 0, 7, DFLAGS,
438427 			RK2928_CLKGATE_CON(1), 12, GFLAGS),
439428 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_pre", 0,
440429 			RK2928_CLKSEL_CON(19), 0,
441430 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
442
-			&common_uart2_fracmux, RK3188_UART_FRAC_MAX_PRATE),
431
+			&common_uart2_fracmux),
443432 	COMPOSITE_NOMUX(0, "uart3_pre", "uart_src", 0,
444433 			RK2928_CLKSEL_CON(16), 0, 7, DFLAGS,
445434 			RK2928_CLKGATE_CON(1), 14, GFLAGS),
446435 	COMPOSITE_FRACMUX(0, "uart3_frac", "uart3_pre", 0,
447436 			RK2928_CLKSEL_CON(20), 0,
448437 			RK2928_CLKGATE_CON(1), 15, GFLAGS,
449
-			&common_uart3_fracmux, RK3188_UART_FRAC_MAX_PRATE),
438
+			&common_uart3_fracmux),
450439 
451440 	GATE(SCLK_JTAG, "jtag", "ext_jtag", 0, RK2928_CLKGATE_CON(1), 3, GFLAGS),
452441 
....@@ -465,9 +454,9 @@
465454 	GATE(HCLK_ROM, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(5), 6, GFLAGS),
466455 	GATE(HCLK_I2S0_2CH, "hclk_i2s0_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 2, GFLAGS),
467456 	GATE(HCLK_SPDIF, "hclk_spdif", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 1, GFLAGS),
468
-	GATE(0, "hclk_cpubus", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 8, GFLAGS),
457
+	GATE(0, "hclk_cpubus", "hclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(4), 8, GFLAGS),
469458 	/* hclk_ahb2apb is part of a clk branch */
470
-	GATE(0, "hclk_vio_bus", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 12, GFLAGS),
459
+	GATE(0, "hclk_vio_bus", "hclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(6), 12, GFLAGS),
471460 	GATE(HCLK_LCDC0, "hclk_lcdc0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 1, GFLAGS),
472461 	GATE(HCLK_LCDC1, "hclk_lcdc1", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 2, GFLAGS),
473462 	GATE(HCLK_CIF0, "hclk_cif0", "hclk_cpu", 0, RK2928_CLKGATE_CON(6), 4, GFLAGS),
....@@ -585,7 +574,7 @@
585574 	GATE(CORE_L2C, "core_l2c", "aclk_cpu", CLK_IGNORE_UNUSED,
586575 			RK2928_CLKGATE_CON(9), 4, GFLAGS),
587576 
588
-	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, 0,
577
+	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_gpll_cpll_p, CLK_IS_CRITICAL,
589578 			RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
590579 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
591580 
....@@ -608,7 +597,7 @@
608597 
609598 	GATE(0, "pclkin_cif1", "ext_cif1", 0,
610599 			RK2928_CLKGATE_CON(3), 4, GFLAGS),
611
-	INVERTER(PCLK_CIF1, "pclk_cif1", "pclkin_cif1",
600
+	INVERTER(0, "pclk_cif1", "pclkin_cif1",
612601 			RK2928_CLKSEL_CON(30), 12, IFLAGS),
613602 
614603 	COMPOSITE(0, "aclk_gpu_src", mux_pll_src_cpll_gpll_p, 0,
....@@ -632,21 +621,21 @@
632621 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", 0,
633622 			RK2928_CLKSEL_CON(6), 0,
634623 			RK2928_CLKGATE_CON(0), 8, GFLAGS,
635
-			&rk3066a_i2s0_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
624
+			&rk3066a_i2s0_fracmux),
636625 	COMPOSITE_NOMUX(0, "i2s1_pre", "i2s_src", 0,
637626 			RK2928_CLKSEL_CON(3), 0, 7, DFLAGS,
638627 			RK2928_CLKGATE_CON(0), 9, GFLAGS),
639628 	COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_pre", 0,
640629 			RK2928_CLKSEL_CON(7), 0,
641630 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
642
-			&rk3066a_i2s1_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
631
+			&rk3066a_i2s1_fracmux),
643632 	COMPOSITE_NOMUX(0, "i2s2_pre", "i2s_src", 0,
644633 			RK2928_CLKSEL_CON(4), 0, 7, DFLAGS,
645634 			RK2928_CLKGATE_CON(0), 11, GFLAGS),
646635 	COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_pre", 0,
647636 			RK2928_CLKSEL_CON(8), 0,
648637 			RK2928_CLKGATE_CON(0), 12, GFLAGS,
649
-			&rk3066a_i2s2_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
638
+			&rk3066a_i2s2_fracmux),
650639 
651640 	GATE(HCLK_I2S1_2CH, "hclk_i2s1_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 3, GFLAGS),
652641 	GATE(HCLK_I2S_8CH, "hclk_i2s_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(7), 4, GFLAGS),
....@@ -690,7 +679,7 @@
690679 			div_rk3188_aclk_core_t, RK2928_CLKGATE_CON(0), 7, GFLAGS),
691680 
692681 	/* do not source aclk_cpu_pre from the apll, to keep complexity down */
693
-	COMPOSITE_NOGATE(0, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
682
+	COMPOSITE_NOGATE(ACLK_CPU_PRE, "aclk_cpu_pre", mux_aclk_cpu_p, CLK_SET_RATE_NO_REPARENT,
694683 			RK2928_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS),
695684 	DIV(0, "pclk_cpu_pre", "aclk_cpu_pre", 0,
696685 			RK2928_CLKSEL_CON(1), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
....@@ -703,7 +692,7 @@
703692 	GATE(CORE_L2C, "core_l2c", "armclk", CLK_IGNORE_UNUSED,
704693 			RK2928_CLKGATE_CON(9), 4, GFLAGS),
705694 
706
-	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, 0,
695
+	COMPOSITE(0, "aclk_peri_pre", mux_pll_src_cpll_gpll_p, CLK_IS_CRITICAL,
707696 			RK2928_CLKSEL_CON(10), 15, 1, MFLAGS, 0, 5, DFLAGS,
708697 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
709698 
....@@ -740,7 +729,7 @@
740729 	COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_pre", CLK_SET_RATE_PARENT,
741730 			RK2928_CLKSEL_CON(7), 0,
742731 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
743
-			&rk3188_i2s0_fracmux, RK3188_I2S_FRAC_MAX_PRATE),
732
+			&rk3188_i2s0_fracmux),
744733 
745734 	GATE(0, "hclk_imem0", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 14, GFLAGS),
746735 	GATE(0, "hclk_imem1", "hclk_cpu", 0, RK2928_CLKGATE_CON(4), 15, GFLAGS),
....@@ -755,17 +744,6 @@
755744 	GATE(PCLK_UART1, "pclk_uart1", "hclk_ahb2apb", 0, RK2928_CLKGATE_CON(8), 1, GFLAGS),
756745 
757746 	GATE(ACLK_GPS, "aclk_gps", "aclk_peri", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
758
-};
759
-
760
-static const char *const rk3188_critical_clocks[] __initconst = {
761
-	"aclk_cpu",
762
-	"aclk_peri",
763
-	"hclk_peri",
764
-	"pclk_cpu",
765
-	"pclk_peri",
766
-	"hclk_cpubus",
767
-	"hclk_vio_bus",
768
-	"hclk_ahb2apb",
769747 };
770748 
771749 static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)
....@@ -800,10 +778,12 @@
800778 static void __init rk3066a_clk_init(struct device_node *np)
801779 {
802780 	struct rockchip_clk_provider *ctx;
781
+	struct clk **clks;
803782 
804783 	ctx = rk3188_common_clk_init(np);
805784 	if (IS_ERR(ctx))
806785 		return;
786
+	clks = ctx->clk_data.clks;
807787 
808788 	rockchip_clk_register_plls(ctx, rk3066_pll_clks,
809789 				   ARRAY_SIZE(rk3066_pll_clks),
....@@ -811,11 +791,9 @@
811791 	rockchip_clk_register_branches(ctx, rk3066a_clk_branches,
812792 				  ARRAY_SIZE(rk3066a_clk_branches));
813793 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
814
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
794
+			2, clks[PLL_APLL], clks[PLL_GPLL],
815795 			&rk3066_cpuclk_data, rk3066_cpuclk_rates,
816796 			ARRAY_SIZE(rk3066_cpuclk_rates));
817
-	rockchip_clk_protect_critical(rk3188_critical_clocks,
818
-				      ARRAY_SIZE(rk3188_critical_clocks));
819797 	rockchip_clk_of_add_provider(np, ctx);
820798 }
821799 CLK_OF_DECLARE(rk3066a_cru, "rockchip,rk3066a-cru", rk3066a_clk_init);
....@@ -823,13 +801,14 @@
823801 static void __init rk3188a_clk_init(struct device_node *np)
824802 {
825803 	struct rockchip_clk_provider *ctx;
826
-	struct clk *clk1, *clk2;
804
+	struct clk **clks;
827805 	unsigned long rate;
828806 	int ret;
829807 
830808 	ctx = rk3188_common_clk_init(np);
831809 	if (IS_ERR(ctx))
832810 		return;
811
+	clks = ctx->clk_data.clks;
833812 
834813 	rockchip_clk_register_plls(ctx, rk3188_pll_clks,
835814 				   ARRAY_SIZE(rk3188_pll_clks),
....@@ -837,29 +816,25 @@
837816 	rockchip_clk_register_branches(ctx, rk3188_clk_branches,
838817 				  ARRAY_SIZE(rk3188_clk_branches));
839818 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
840
-				  mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
819
+				  2, clks[PLL_APLL], clks[PLL_GPLL],
841820 				  &rk3188_cpuclk_data, rk3188_cpuclk_rates,
842821 				  ARRAY_SIZE(rk3188_cpuclk_rates));
843822 
844823 	/* reparent aclk_cpu_pre from apll */
845
-	clk1 = __clk_lookup("aclk_cpu_pre");
846
-	clk2 = __clk_lookup("gpll");
847
-	if (clk1 && clk2) {
848
-		rate = clk_get_rate(clk1);
824
+	if (clks[ACLK_CPU_PRE] && clks[PLL_GPLL]) {
825
+		rate = clk_get_rate(clks[ACLK_CPU_PRE]);
849826 
850
-		ret = clk_set_parent(clk1, clk2);
827
+		ret = clk_set_parent(clks[ACLK_CPU_PRE], clks[PLL_GPLL]);
851828 		if (ret < 0)
852829 			pr_warn("%s: could not reparent aclk_cpu_pre to gpll\n",
853830 				__func__);
854831 
855
-		clk_set_rate(clk1, rate);
832
+		clk_set_rate(clks[ACLK_CPU_PRE], rate);
856833 	} else {
857834 		pr_warn("%s: missing clocks to reparent aclk_cpu_pre to gpll\n",
858835 			__func__);
859836 	}
860837 
861
-	rockchip_clk_protect_critical(rk3188_critical_clocks,
862
-				      ARRAY_SIZE(rk3188_critical_clocks));
863838 	rockchip_clk_of_add_provider(np, ctx);
864839 }
865840 CLK_OF_DECLARE(rk3188a_cru, "rockchip,rk3188a-cru", rk3188a_clk_init);
....@@ -885,3 +860,62 @@
885860 	rk3188a_clk_init(np);
886861 }
887862 CLK_OF_DECLARE(rk3188_cru, "rockchip,rk3188-cru", rk3188_clk_init);
863
+
864
+struct clk_rk3188_inits {
865
+	void (*inits)(struct device_node *np);
866
+};
867
+
868
+static const struct clk_rk3188_inits clk_rk3066a_init = {
869
+	.inits = rk3066a_clk_init,
870
+};
871
+
872
+static const struct clk_rk3188_inits clk_rk3188a_init = {
873
+	.inits = rk3188a_clk_init,
874
+};
875
+
876
+static const struct clk_rk3188_inits clk_rk3188_init = {
877
+	.inits = rk3188_clk_init,
878
+};
879
+
880
+static const struct of_device_id clk_rk3188_match_table[] = {
881
+	{
882
+		.compatible = "rockchip,rk3066a-cru",
883
+		.data = &clk_rk3066a_init,
884
+	}, {
885
+		.compatible = "rockchip,rk3188a-cru",
886
+		.data = &clk_rk3188a_init,
887
+	}, {
888
+		.compatible = "rockchip,rk3188-cru",
889
+		.data = &rk3188_clk_init,
890
+	},
891
+	{ }
892
+};
893
+MODULE_DEVICE_TABLE(of, clk_rk3188_match_table);
894
+
895
+static int __init clk_rk3188_probe(struct platform_device *pdev)
896
+{
897
+	struct device_node *np = pdev->dev.of_node;
898
+	const struct of_device_id *match;
899
+	const struct clk_rk3188_inits *init_data;
900
+
901
+	match = of_match_device(clk_rk3188_match_table, &pdev->dev);
902
+	if (!match || !match->data)
903
+		return -EINVAL;
904
+
905
+	init_data = match->data;
906
+	if (init_data->inits)
907
+		init_data->inits(np);
908
+
909
+	return 0;
910
+}
911
+
912
+static struct platform_driver clk_rk3188_driver = {
913
+	.driver		= {
914
+		.name	= "clk-rk3188",
915
+		.of_match_table = clk_rk3188_match_table,
916
+	},
917
+};
918
+builtin_platform_driver_probe(clk_rk3188_driver, clk_rk3188_probe);
919
+
920
+MODULE_DESCRIPTION("Rockchip RK3188 Clock Driver");
921
+MODULE_LICENSE("GPL");