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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/clk/rockchip/clk-rk3036.c
....@@ -1,32 +1,23 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2014 MundoReader S.L.
34  * Author: Heiko Stuebner <heiko@sntech.de>
45  *
56  * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
67  * Author: Xing Zheng <zhengxing@rock-chips.com>
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License as published by
10
- * the Free Software Foundation; either version 2 of the License, or
11
- * (at your option) any later version.
12
- *
13
- * This program is distributed in the hope that it will be useful,
14
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
15
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
- * GNU General Public License for more details.
178  */
189 
1910 #include <linux/clk-provider.h>
11
+#include <linux/io.h>
12
+#include <linux/module.h>
2013 #include <linux/of.h>
2114 #include <linux/of_address.h>
15
+#include <linux/of_device.h>
2216 #include <linux/syscore_ops.h>
2317 #include <dt-bindings/clock/rk3036-cru.h>
2418 #include "clk.h"
2519 
2620 #define RK3036_GRF_SOC_STATUS0	0x14c
27
-#define RK3036_UART_FRAC_MAX_PRATE	600000000
28
-#define RK3036_I2S_FRAC_MAX_PRATE	600000000
29
-#define RK3036_SPDIF_FRAC_MAX_PRATE	600000000
3021 
3122 enum rk3036_plls {
3223 	apll, dpll, gpll,
....@@ -128,7 +119,6 @@
128119 
129120 PNAME(mux_pll_p)		= { "xin24m", "xin24m" };
130121 
131
-PNAME(mux_armclk_p)		= { "apll", "gpll_armclk" };
132122 PNAME(mux_busclk_p)		= { "dummy_apll", "dpll_cpu", "gpll_cpu" };
133123 PNAME(mux_ddrphy_p)		= { "dpll_ddr", "gpll_ddr" };
134124 PNAME(mux_pll_src_apll_dpll_gpll_p)	= { "apll", "dpll", "gpll" };
....@@ -211,16 +201,16 @@
211201 			RK2928_CLKSEL_CON(1), 4, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
212202 			RK2928_CLKGATE_CON(0), 7, GFLAGS),
213203 
214
-	GATE(0, "dpll_cpu", "dpll", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
215
-	GATE(0, "gpll_cpu", "gpll", 0, RK2928_CLKGATE_CON(0), 1, GFLAGS),
216
-	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, 0,
204
+	GATE(0, "dpll_cpu", "dpll", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(10), 8, GFLAGS),
205
+	GATE(0, "gpll_cpu", "gpll", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(0), 1, GFLAGS),
206
+	COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_busclk_p, CLK_IS_CRITICAL,
217207 			RK2928_CLKSEL_CON(0), 14, 2, MFLAGS, 8, 5, DFLAGS),
218
-	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
208
+	GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src",  CLK_IS_CRITICAL,
219209 			RK2928_CLKGATE_CON(0), 3, GFLAGS),
220
-	COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
210
+	COMPOSITE_NOMUX(PCLK_CPU, "pclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
221211 			RK2928_CLKSEL_CON(1), 12, 3, DFLAGS | CLK_DIVIDER_READ_ONLY,
222212 			RK2928_CLKGATE_CON(0), 5, GFLAGS),
223
-	COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IGNORE_UNUSED,
213
+	COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", CLK_IS_CRITICAL,
224214 			RK2928_CLKSEL_CON(1), 8, 2, DFLAGS | CLK_DIVIDER_READ_ONLY,
225215 			RK2928_CLKGATE_CON(0), 4, GFLAGS),
226216 
....@@ -228,15 +218,15 @@
228218 			RK2928_CLKSEL_CON(10), 14, 2, MFLAGS, 0, 5, DFLAGS,
229219 			RK2928_CLKGATE_CON(2), 0, GFLAGS),
230220 
231
-	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", 0,
221
+	GATE(ACLK_PERI, "aclk_peri", "aclk_peri_src", CLK_IS_CRITICAL,
232222 			RK2928_CLKGATE_CON(2), 1, GFLAGS),
233
-	DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
223
+	DIV(0, "pclk_peri_src", "aclk_peri_src", CLK_IS_CRITICAL,
234224 			RK2928_CLKSEL_CON(10), 12, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
235
-	GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", 0,
225
+	GATE(PCLK_PERI, "pclk_peri", "pclk_peri_src", CLK_IS_CRITICAL,
236226 			RK2928_CLKGATE_CON(2), 3, GFLAGS),
237
-	DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IGNORE_UNUSED,
227
+	DIV(0, "hclk_peri_src", "aclk_peri_src", CLK_IS_CRITICAL,
238228 			RK2928_CLKSEL_CON(10), 8, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
239
-	GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", 0,
229
+	GATE(HCLK_PERI, "hclk_peri", "hclk_peri_src", CLK_IS_CRITICAL,
240230 			RK2928_CLKGATE_CON(2), 2, GFLAGS),
241231 
242232 	COMPOSITE_NODIV(SCLK_TIMER0, "sclk_timer0", mux_timer_p, CLK_IGNORE_UNUSED,
....@@ -266,15 +256,15 @@
266256 	COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
267257 			RK2928_CLKSEL_CON(17), 0,
268258 			RK2928_CLKGATE_CON(1), 9, GFLAGS,
269
-			&rk3036_uart0_fracmux, RK3036_UART_FRAC_MAX_PRATE),
259
+			&rk3036_uart0_fracmux),
270260 	COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
271261 			RK2928_CLKSEL_CON(18), 0,
272262 			RK2928_CLKGATE_CON(1), 11, GFLAGS,
273
-			&rk3036_uart1_fracmux, RK3036_UART_FRAC_MAX_PRATE),
263
+			&rk3036_uart1_fracmux),
274264 	COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
275265 			RK2928_CLKSEL_CON(19), 0,
276266 			RK2928_CLKGATE_CON(1), 13, GFLAGS,
277
-			&rk3036_uart2_fracmux, RK3036_UART_FRAC_MAX_PRATE),
267
+			&rk3036_uart2_fracmux),
278268 
279269 	COMPOSITE(ACLK_VCODEC, "aclk_vcodec", mux_pll_src_dmyapll_dpll_gpll_p, 0,
280270 			RK2928_CLKSEL_CON(32), 14, 2, MFLAGS, 8, 5, DFLAGS,
....@@ -327,7 +317,7 @@
327317 	COMPOSITE_FRACMUX(SCLK_I2S_FRAC, "i2s_frac", "i2s_src", CLK_SET_RATE_PARENT,
328318 			RK2928_CLKSEL_CON(7), 0,
329319 			RK2928_CLKGATE_CON(0), 10, GFLAGS,
330
-			&rk3036_i2s_fracmux, RK3036_I2S_FRAC_MAX_PRATE),
320
+			&rk3036_i2s_fracmux),
331321 	COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_clkout", mux_i2s_clkout_p, 0,
332322 			RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
333323 			RK2928_CLKGATE_CON(0), 13, GFLAGS),
....@@ -340,7 +330,7 @@
340330 	COMPOSITE_FRACMUX(0, "spdif_frac", "spdif_src", 0,
341331 			RK2928_CLKSEL_CON(9), 0,
342332 			RK2928_CLKGATE_CON(2), 12, GFLAGS,
343
-			&rk3036_spdif_fracmux, RK3036_SPDIF_FRAC_MAX_PRATE),
333
+			&rk3036_spdif_fracmux),
344334 
345335 	GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin12m", CLK_IGNORE_UNUSED,
346336 			RK2928_CLKGATE_CON(1), 5, GFLAGS),
....@@ -387,7 +377,7 @@
387377 
388378 	/* pclk_cpu gates */
389379 	GATE(PCLK_GRF, "pclk_grf", "pclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(5), 4, GFLAGS),
390
-	GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 7, GFLAGS),
380
+	GATE(PCLK_DDRUPCTL, "pclk_ddrupctl", "pclk_cpu", CLK_IS_CRITICAL, RK2928_CLKGATE_CON(5), 7, GFLAGS),
391381 	GATE(PCLK_ACODEC, "pclk_acodec", "pclk_cpu", 0, RK2928_CLKGATE_CON(5), 14, GFLAGS),
392382 	GATE(PCLK_HDMI, "pclk_hdmi", "pclk_cpu", 0, RK2928_CLKGATE_CON(3), 8, GFLAGS),
393383 
....@@ -441,15 +431,6 @@
441431 	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
442432 };
443433 
444
-static const char *const rk3036_critical_clocks[] __initconst = {
445
-	"armclk",
446
-	"aclk_cpu",
447
-	"aclk_peri",
448
-	"hclk_peri",
449
-	"pclk_peri",
450
-	"pclk_ddrupctl",
451
-};
452
-
453434 static void __iomem *rk3036_cru_base;
454435 
455436 static void rk3036_dump_cru(void)
....@@ -467,6 +448,7 @@
467448 	struct rockchip_clk_provider *ctx;
468449 	void __iomem *reg_base;
469450 	struct clk *clk;
451
+	struct clk **clks;
470452 
471453 	reg_base = of_iomap(np, 0);
472454 	if (!reg_base) {
....@@ -487,6 +469,7 @@
487469 		iounmap(reg_base);
488470 		return;
489471 	}
472
+	clks = ctx->clk_data.clks;
490473 
491474 	clk = clk_register_fixed_factor(NULL, "usb480m", "xin24m", 0, 20, 1);
492475 	if (IS_ERR(clk))
....@@ -498,13 +481,11 @@
498481 				   RK3036_GRF_SOC_STATUS0);
499482 	rockchip_clk_register_branches(ctx, rk3036_clk_branches,
500483 				  ARRAY_SIZE(rk3036_clk_branches));
484
+
501485 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
502
-			mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
486
+			2, clks[PLL_APLL], clks[PLL_GPLL],
503487 			&rk3036_cpuclk_data, rk3036_cpuclk_rates,
504488 			ARRAY_SIZE(rk3036_cpuclk_rates));
505
-
506
-	rockchip_clk_protect_critical(rk3036_critical_clocks,
507
-				      ARRAY_SIZE(rk3036_critical_clocks));
508489 
509490 	rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
510491 				  ROCKCHIP_SOFTRST_HIWORD_MASK);
....@@ -519,3 +500,31 @@
519500 	}
520501 }
521502 CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);
503
+
504
+static int __init clk_rk3036_probe(struct platform_device *pdev)
505
+{
506
+	struct device_node *np = pdev->dev.of_node;
507
+
508
+	rk3036_clk_init(np);
509
+
510
+	return 0;
511
+}
512
+
513
+static const struct of_device_id clk_rk3036_match_table[] = {
514
+	{
515
+		.compatible = "rockchip,rk3036-cru",
516
+	},
517
+	{ }
518
+};
519
+MODULE_DEVICE_TABLE(of, clk_rk3036_match_table);
520
+
521
+static struct platform_driver clk_rk3036_driver = {
522
+	.driver		= {
523
+		.name	= "clk-rk3036",
524
+		.of_match_table = clk_rk3036_match_table,
525
+	},
526
+};
527
+builtin_platform_driver_probe(clk_rk3036_driver, clk_rk3036_probe);
528
+
529
+MODULE_DESCRIPTION("Rockchip RK3036 Clock Driver");
530
+MODULE_LICENSE("GPL");