forked from ~ljy/RK356X_SDK_RELEASE

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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/clk/rockchip/clk-rk1808.c
....@@ -4,8 +4,10 @@
44  * Author: Elaine Zhang <zhangqing@rock-chips.com>
55  */
66 #include <linux/clk-provider.h>
7
+#include <linux/module.h>
78 #include <linux/of.h>
89 #include <linux/of_address.h>
10
+#include <linux/of_device.h>
911 #include <linux/syscore_ops.h>
1012 #include <dt-bindings/clock/rk1808-cru.h>
1113 #include "clk.h"
....@@ -128,7 +130,6 @@
128130 
129131 PNAME(mux_pll_p)		= { "xin24m", "xin32k"};
130132 PNAME(mux_usb480m_p)		= { "xin24m", "usb480m_phy", "xin32k" };
131
-PNAME(mux_armclk_p)		= { "apll_core", "cpll_core", "gpll_core" };
132133 PNAME(mux_gpll_cpll_p)		= { "gpll", "cpll" };
133134 PNAME(mux_gpll_cpll_apll_p)		= { "gpll", "cpll", "apll" };
134135 PNAME(mux_npu_p)		= { "clk_npu_div", "clk_npu_np5" };
....@@ -297,7 +298,7 @@
297298 	GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
298299 			RK1808_CLKGATE_CON(0), 5, GFLAGS),
299300 
300
-	COMPOSITE_NOMUX(MSCLK_CORE_NIU, "msclk_core_niu", "gpll", 0,
301
+	COMPOSITE_NOMUX(MSCLK_CORE_NIU, "msclk_core_niu", "gpll", CLK_IS_CRITICAL,
301302 			RK1808_CLKSEL_CON(18), 0, 5, DFLAGS,
302303 			RK1808_CLKGATE_CON(0), 1, GFLAGS),
303304 
....@@ -305,12 +306,12 @@
305306 	 * Clock-Architecture Diagram 3
306307 	 */
307308 
308
-	COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_gpll_cpll_p, 0,
309
+	COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
309310 			RK1808_CLKSEL_CON(15), 11, 1, MFLAGS, 12, 4, DFLAGS,
310311 			RK1808_CLKGATE_CON(1), 0, GFLAGS),
311
-	GATE(0, "aclk_gic_niu", "aclk_gic_pre", CLK_IGNORE_UNUSED,
312
+	GATE(0, "aclk_gic_niu", "aclk_gic_pre", CLK_IS_CRITICAL,
312313 			RK1808_CLKGATE_CON(1), 1, GFLAGS),
313
-	GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", 0,
314
+	GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL,
314315 			RK1808_CLKGATE_CON(1), 2, GFLAGS),
315316 	GATE(0, "aclk_core2gic", "aclk_gic_pre", CLK_IGNORE_UNUSED,
316317 			RK1808_CLKGATE_CON(1), 3, GFLAGS),
....@@ -337,9 +338,9 @@
337338 	/*
338339 	 * Clock-Architecture Diagram 4
339340 	 */
340
-	COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE | CLK_OPS_PARENT_ENABLE,
341
+	COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
341342 			RK1808_CLKSEL_CON(1), 8, 2, MFLAGS, 0, 4, DFLAGS),
342
-	COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE | CLK_OPS_PARENT_ENABLE,
343
+	COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
343344 			RK1808_CLKSEL_CON(1), 10, 2, MFLAGS, 4, 4, DFLAGS),
344345 	MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT,
345346 			RK1808_CLKSEL_CON(1), 15, 1, MFLAGS),
....@@ -355,40 +356,40 @@
355356 			RK1808_CLKGATE_CON(1), 9, GFLAGS),
356357 	GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
357358 			RK1808_CLKGATE_CON(1), 11, GFLAGS),
358
-	GATE(0, "aclk_npu_niu", "aclk_npu_pre", CLK_IGNORE_UNUSED,
359
+	GATE(0, "aclk_npu_niu", "aclk_npu_pre", CLK_IS_CRITICAL,
359360 			RK1808_CLKGATE_CON(1), 13, GFLAGS),
360361 	COMPOSITE_NOMUX(0, "aclk_npu2mem", "aclk_npu_pre", CLK_IGNORE_UNUSED,
361362 			RK1808_CLKSEL_CON(2), 4, 4, DFLAGS,
362363 			RK1808_CLKGATE_CON(1), 15, GFLAGS),
363364 	GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
364365 			RK1808_CLKGATE_CON(1), 12, GFLAGS),
365
-	GATE(0, "hclk_npu_niu", "hclk_npu_pre", CLK_IGNORE_UNUSED,
366
+	GATE(0, "hclk_npu_niu", "hclk_npu_pre", CLK_IS_CRITICAL,
366367 			RK1808_CLKGATE_CON(1), 14, GFLAGS),
367368 
368369 	GATE(SCLK_PVTM_NPU, "clk_pvtm_npu", "xin24m", 0,
369370 			RK1808_CLKGATE_CON(0), 15, GFLAGS),
370371 
371
-	COMPOSITE(ACLK_IMEM_PRE, "aclk_imem_pre", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
372
+	COMPOSITE(ACLK_IMEM_PRE, "aclk_imem_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
372373 			RK1808_CLKSEL_CON(17), 7, 1, MFLAGS, 0, 5, DFLAGS,
373374 			RK1808_CLKGATE_CON(7), 0, GFLAGS),
374375 	GATE(ACLK_IMEM0, "aclk_imem0", "aclk_imem_pre", CLK_IGNORE_UNUSED,
375376 			RK1808_CLKGATE_CON(7), 6, GFLAGS),
376
-	GATE(0, "aclk_imem0_niu", "aclk_imem_pre", CLK_IGNORE_UNUSED,
377
+	GATE(0, "aclk_imem0_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
377378 			RK1808_CLKGATE_CON(7), 10, GFLAGS),
378379 	GATE(ACLK_IMEM1, "aclk_imem1", "aclk_imem_pre", CLK_IGNORE_UNUSED,
379380 			RK1808_CLKGATE_CON(7), 7, GFLAGS),
380
-	GATE(0, "aclk_imem1_niu", "aclk_imem_pre", CLK_IGNORE_UNUSED,
381
+	GATE(0, "aclk_imem1_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
381382 			RK1808_CLKGATE_CON(7), 11, GFLAGS),
382383 	GATE(ACLK_IMEM2, "aclk_imem2", "aclk_imem_pre", CLK_IGNORE_UNUSED,
383384 			RK1808_CLKGATE_CON(7), 8, GFLAGS),
384
-	GATE(0, "aclk_imem2_niu", "aclk_imem_pre", CLK_IGNORE_UNUSED,
385
+	GATE(0, "aclk_imem2_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
385386 			RK1808_CLKGATE_CON(7), 12, GFLAGS),
386387 	GATE(ACLK_IMEM3, "aclk_imem3", "aclk_imem_pre", CLK_IGNORE_UNUSED,
387388 			RK1808_CLKGATE_CON(7), 9, GFLAGS),
388
-	GATE(0, "aclk_imem3_niu", "aclk_imem_pre", CLK_IGNORE_UNUSED,
389
+	GATE(0, "aclk_imem3_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
389390 			RK1808_CLKGATE_CON(7), 13, GFLAGS),
390391 
391
-	COMPOSITE(HSCLK_IMEM, "hsclk_imem", mux_gpll_cpll_p, 0,
392
+	COMPOSITE(HSCLK_IMEM, "hsclk_imem", mux_gpll_cpll_p, CLK_IS_CRITICAL,
392393 			RK1808_CLKSEL_CON(17), 15, 1, MFLAGS, 8, 5, DFLAGS,
393394 			RK1808_CLKGATE_CON(7), 5, GFLAGS),
394395 
....@@ -417,12 +418,12 @@
417418 			RK1808_CLKGATE_CON(8), 5, GFLAGS),
418419 	GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
419420 			RK1808_CLKGATE_CON(8), 6, GFLAGS),
420
-	COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddr_p, CLK_IGNORE_UNUSED,
421
-			RK1808_CLKSEL_CON(3), 7, 1, 0, 5,
422
-			ROCKCHIP_DDRCLK_SIP_V2),
421
+
422
+	COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddr_p, CLK_IGNORE_UNUSED,
423
+			RK1808_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS),
423424 	FACTOR(0, "clk_ddrphy1x_out", "sclk_ddrc", CLK_IGNORE_UNUSED, 1, 1),
424425 
425
-	COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", 0,
426
+	COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IS_CRITICAL,
426427 			RK1808_CLKSEL_CON(3), 8, 5, DFLAGS,
427428 			RK1808_CLKGATE_CON(2), 1, GFLAGS),
428429 	GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
....@@ -433,7 +434,7 @@
433434 			RK1808_CLKGATE_CON(2), 9, GFLAGS),
434435 	GATE(PCLK_STDBY, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
435436 			RK1808_CLKGATE_CON(2), 12, GFLAGS),
436
-	GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
437
+	GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IS_CRITICAL,
437438 			RK1808_CLKGATE_CON(2), 14, GFLAGS),
438439 	GATE(0, "pclk_ddrdfi_ctl", "pclk_ddr", CLK_IGNORE_UNUSED,
439440 			RK1808_CLKGATE_CON(2), 2, GFLAGS),
....@@ -485,7 +486,7 @@
485486 	COMPOSITE_FRACMUX(0, "dclk_vopraw_frac", "dclk_vopraw_src", CLK_SET_RATE_PARENT,
486487 			RK1808_CLKSEL_CON(6), 0,
487488 			RK1808_CLKGATE_CON(3), 2, GFLAGS,
488
-			&rk1808_dclk_vopraw_fracmux, RK1808_VOP_RAW_FRAC_MAX_PRATE),
489
+			&rk1808_dclk_vopraw_fracmux),
489490 	GATE(DCLK_VOPRAW, "dclk_vopraw", "dclk_vopraw_mux", 0,
490491 			RK1808_CLKGATE_CON(3), 3, GFLAGS),
491492 
....@@ -495,7 +496,7 @@
495496 	COMPOSITE_FRACMUX(0, "dclk_voplite_frac", "dclk_voplite_src", CLK_SET_RATE_PARENT,
496497 			RK1808_CLKSEL_CON(8), 0,
497498 			RK1808_CLKGATE_CON(3), 5, GFLAGS,
498
-			&rk1808_dclk_voplite_fracmux, RK1808_VOP_LITE_FRAC_MAX_PRATE),
499
+			&rk1808_dclk_voplite_fracmux),
499500 	GATE(DCLK_VOPLITE, "dclk_voplite", "dclk_voplite_mux", 0,
500501 			RK1808_CLKGATE_CON(3), 6, GFLAGS),
501502 
....@@ -582,18 +583,18 @@
582583 
583584 	/* PD_PHP */
584585 
585
-	COMPOSITE_NODIV(0, "clk_peri_src", mux_gpll_cpll_p, 0,
586
+	COMPOSITE_NODIV(0, "clk_peri_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
586587 			RK1808_CLKSEL_CON(19), 15, 1, MFLAGS,
587588 			RK1808_CLKGATE_CON(8), 0, GFLAGS),
588
-	COMPOSITE_NOMUX(MSCLK_PERI, "msclk_peri", "clk_peri_src", 0,
589
+	COMPOSITE_NOMUX(MSCLK_PERI, "msclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
589590 			RK1808_CLKSEL_CON(19), 0, 5, DFLAGS,
590591 			RK1808_CLKGATE_CON(8), 1, GFLAGS),
591
-	COMPOSITE_NOMUX(LSCLK_PERI, "lsclk_peri", "clk_peri_src", 0,
592
+	COMPOSITE_NOMUX(LSCLK_PERI, "lsclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
592593 			RK1808_CLKSEL_CON(19), 8, 5, DFLAGS,
593594 			RK1808_CLKGATE_CON(8), 2, GFLAGS),
594
-	GATE(0, "msclk_peri_niu", "msclk_peri", CLK_IGNORE_UNUSED,
595
+	GATE(0, "msclk_peri_niu", "msclk_peri", CLK_IS_CRITICAL,
595596 			RK1808_CLKGATE_CON(8), 3, GFLAGS),
596
-	GATE(0, "lsclk_peri_niu", "lsclk_peri", CLK_IGNORE_UNUSED,
597
+	GATE(0, "lsclk_peri_niu", "lsclk_peri", CLK_IS_CRITICAL,
597598 			RK1808_CLKGATE_CON(8), 4, GFLAGS),
598599 
599600 	/* PD_MMC */
....@@ -711,21 +712,21 @@
711712 
712713 	/* PD_BUS */
713714 
714
-	COMPOSITE_NODIV(0, "clk_bus_src", mux_gpll_cpll_p, 0,
715
+	COMPOSITE_NODIV(0, "clk_bus_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
715716 			RK1808_CLKSEL_CON(27), 15, 1, MFLAGS,
716717 			RK1808_CLKGATE_CON(11), 0, GFLAGS),
717
-	COMPOSITE_NOMUX(HSCLK_BUS_PRE, "hsclk_bus_pre", "clk_bus_src", 0,
718
+	COMPOSITE_NOMUX(HSCLK_BUS_PRE, "hsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
718719 			RK1808_CLKSEL_CON(27), 8, 5, DFLAGS,
719720 			RK1808_CLKGATE_CON(11), 1, GFLAGS),
720
-	COMPOSITE_NOMUX(MSCLK_BUS_PRE, "msclk_bus_pre", "clk_bus_src", 0,
721
+	COMPOSITE_NOMUX(MSCLK_BUS_PRE, "msclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
721722 			RK1808_CLKSEL_CON(28), 0, 5, DFLAGS,
722723 			RK1808_CLKGATE_CON(11), 2, GFLAGS),
723
-	COMPOSITE_NOMUX(LSCLK_BUS_PRE, "lsclk_bus_pre", "clk_bus_src", 0,
724
+	COMPOSITE_NOMUX(LSCLK_BUS_PRE, "lsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
724725 			RK1808_CLKSEL_CON(28), 8, 5, DFLAGS,
725726 			RK1808_CLKGATE_CON(11), 3, GFLAGS),
726
-	GATE(0, "hsclk_bus_niu", "hsclk_bus_pre", CLK_IGNORE_UNUSED,
727
+	GATE(0, "hsclk_bus_niu", "hsclk_bus_pre", CLK_IS_CRITICAL,
727728 			RK1808_CLKGATE_CON(15), 0, GFLAGS),
728
-	GATE(0, "msclk_bus_niu", "msclk_bus_pre", CLK_IGNORE_UNUSED,
729
+	GATE(0, "msclk_bus_niu", "msclk_bus_pre", CLK_IS_CRITICAL,
729730 			RK1808_CLKGATE_CON(15), 1, GFLAGS),
730731 	GATE(0, "msclk_sub", "msclk_bus_pre", CLK_IGNORE_UNUSED,
731732 			RK1808_CLKGATE_CON(15), 2, GFLAGS),
....@@ -739,7 +740,7 @@
739740 			RK1808_CLKGATE_CON(15), 6, GFLAGS),
740741 	GATE(ACLK_DCF, "aclk_dcf", "msclk_bus_pre", 0,
741742 			RK1808_CLKGATE_CON(15), 7, GFLAGS),
742
-	GATE(0, "lsclk_bus_niu", "lsclk_bus_pre", CLK_IGNORE_UNUSED,
743
+	GATE(0, "lsclk_bus_niu", "lsclk_bus_pre", CLK_IS_CRITICAL,
743744 			RK1808_CLKGATE_CON(15), 3, GFLAGS),
744745 	GATE(PCLK_DCF, "pclk_dcf", "lsclk_bus_pre", 0,
745746 			RK1808_CLKGATE_CON(15), 8, GFLAGS),
....@@ -803,7 +804,7 @@
803804 			RK1808_CLKGATE_CON(17), 3, GFLAGS),
804805 	GATE(0, "hclk_audio_pre", "msclk_bus_pre", 0,
805806 			RK1808_CLKGATE_CON(17), 8, GFLAGS),
806
-	GATE(0, "pclk_top_pre", "lsclk_bus_pre", 0,
807
+	GATE(0, "pclk_top_pre", "lsclk_bus_pre", CLK_IS_CRITICAL,
807808 			RK1808_CLKGATE_CON(11), 4, GFLAGS),
808809 
809810 	COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_p, 0,
....@@ -822,7 +823,7 @@
822823 	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
823824 			RK1808_CLKSEL_CON(40), 0,
824825 			RK1808_CLKGATE_CON(11), 10, GFLAGS,
825
-			&rk1808_uart1_fracmux, RK1808_UART_FRAC_MAX_PRATE),
826
+			&rk1808_uart1_fracmux),
826827 	GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
827828 			RK1808_CLKGATE_CON(11), 11, GFLAGS),
828829 
....@@ -835,7 +836,7 @@
835836 	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
836837 			RK1808_CLKSEL_CON(43), 0,
837838 			RK1808_CLKGATE_CON(11), 14, GFLAGS,
838
-			&rk1808_uart2_fracmux, RK1808_UART_FRAC_MAX_PRATE),
839
+			&rk1808_uart2_fracmux),
839840 	GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", 0,
840841 			RK1808_CLKGATE_CON(11), 15, GFLAGS),
841842 
....@@ -848,7 +849,7 @@
848849 	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
849850 			RK1808_CLKSEL_CON(46), 0,
850851 			RK1808_CLKGATE_CON(12), 2, GFLAGS,
851
-			&rk1808_uart3_fracmux, RK1808_UART_FRAC_MAX_PRATE),
852
+			&rk1808_uart3_fracmux),
852853 	GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
853854 			RK1808_CLKGATE_CON(12), 3, GFLAGS),
854855 
....@@ -861,7 +862,7 @@
861862 	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
862863 			RK1808_CLKSEL_CON(49), 0,
863864 			RK1808_CLKGATE_CON(12), 6, GFLAGS,
864
-			&rk1808_uart4_fracmux, RK1808_UART_FRAC_MAX_PRATE),
865
+			&rk1808_uart4_fracmux),
865866 	GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
866867 			RK1808_CLKGATE_CON(12), 7, GFLAGS),
867868 
....@@ -874,7 +875,7 @@
874875 	COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
875876 			RK1808_CLKSEL_CON(52), 0,
876877 			RK1808_CLKGATE_CON(12), 10, GFLAGS,
877
-			&rk1808_uart5_fracmux, RK1808_UART_FRAC_MAX_PRATE),
878
+			&rk1808_uart5_fracmux),
878879 	GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", 0,
879880 			RK1808_CLKGATE_CON(12), 11, GFLAGS),
880881 
....@@ -887,7 +888,7 @@
887888 	COMPOSITE_FRACMUX(0, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
888889 			RK1808_CLKSEL_CON(55), 0,
889890 			RK1808_CLKGATE_CON(12), 14, GFLAGS,
890
-			&rk1808_uart6_fracmux, RK1808_UART_FRAC_MAX_PRATE),
891
+			&rk1808_uart6_fracmux),
891892 	GATE(SCLK_UART6, "clk_uart6", "clk_uart6_mux", 0,
892893 			RK1808_CLKGATE_CON(12), 15, GFLAGS),
893894 
....@@ -900,7 +901,7 @@
900901 	COMPOSITE_FRACMUX(0, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
901902 			RK1808_CLKSEL_CON(58), 0,
902903 			RK1808_CLKGATE_CON(13), 2, GFLAGS,
903
-			&rk1808_uart7_fracmux, RK1808_UART_FRAC_MAX_PRATE),
904
+			&rk1808_uart7_fracmux),
904905 	GATE(SCLK_UART7, "clk_uart7", "clk_uart7_mux", 0,
905906 			RK1808_CLKGATE_CON(13), 3, GFLAGS),
906907 
....@@ -1003,7 +1004,7 @@
10031004 	COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
10041005 			RK1808_CLKSEL_CON(31), 0,
10051006 			RK1808_CLKGATE_CON(17), 10, GFLAGS,
1006
-			&rk1808_pdm_fracmux, RK1808_PDM_FRAC_MAX_PRATE),
1007
+			&rk1808_pdm_fracmux),
10071008 	GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
10081009 			RK1808_CLKGATE_CON(17), 11, GFLAGS),
10091010 
....@@ -1013,7 +1014,7 @@
10131014 	COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
10141015 			RK1808_CLKSEL_CON(33), 0,
10151016 			RK1808_CLKGATE_CON(17), 13, GFLAGS,
1016
-			&rk1808_i2s0_8ch_tx_fracmux, RK1808_I2S_FRAC_MAX_PRATE),
1017
+			&rk1808_i2s0_8ch_tx_fracmux),
10171018 	COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
10181019 			RK1808_CLKSEL_CON(32), 12, 1, MFLAGS,
10191020 			RK1808_CLKGATE_CON(17), 14, GFLAGS),
....@@ -1027,7 +1028,7 @@
10271028 	COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
10281029 			RK1808_CLKSEL_CON(35), 0,
10291030 			RK1808_CLKGATE_CON(18), 1, GFLAGS,
1030
-			&rk1808_i2s0_8ch_rx_fracmux, RK1808_I2S_FRAC_MAX_PRATE),
1031
+			&rk1808_i2s0_8ch_rx_fracmux),
10311032 	COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
10321033 			RK1808_CLKSEL_CON(34), 12, 1, MFLAGS,
10331034 			RK1808_CLKGATE_CON(18), 2, GFLAGS),
....@@ -1041,7 +1042,7 @@
10411042 	COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
10421043 			RK1808_CLKSEL_CON(37), 0,
10431044 			RK1808_CLKGATE_CON(18), 5, GFLAGS,
1044
-			&rk1808_i2s1_2ch_fracmux, RK1808_I2S_FRAC_MAX_PRATE),
1045
+			&rk1808_i2s1_2ch_fracmux),
10451046 	GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
10461047 			RK1808_CLKGATE_CON(18), 6, GFLAGS),
10471048 	COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
....@@ -1073,7 +1074,7 @@
10731074 	COMPOSITE_FRACMUX(SCLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
10741075 			RK1808_PMU_CLKSEL_CON(1), 0,
10751076 			RK1808_PMU_CLKGATE_CON(0), 13, GFLAGS,
1076
-			&rk1808_rtc32k_pmu_fracmux, 0),
1077
+			&rk1808_rtc32k_pmu_fracmux),
10771078 
10781079 	COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
10791080 			RK1808_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
....@@ -1095,7 +1096,7 @@
10951096 	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
10961097 			RK1808_PMU_CLKSEL_CON(5), 0,
10971098 			RK1808_PMU_CLKGATE_CON(1), 2, GFLAGS,
1098
-			&rk1808_uart0_pmu_fracmux, RK1808_UART_FRAC_MAX_PRATE),
1099
+			&rk1808_uart0_pmu_fracmux),
10991100 	GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
11001101 			RK1808_PMU_CLKGATE_CON(1), 3, GFLAGS),
11011102 
....@@ -1128,11 +1129,11 @@
11281129 			RK1808_PMU_CLKSEL_CON(7), 4, 1, MFLAGS,
11291130 			RK1808_PMU_CLKGATE_CON(1), 12, GFLAGS),
11301131 
1131
-	COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "ppll", 0,
1132
+	COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "ppll", CLK_IS_CRITICAL,
11321133 			RK1808_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
11331134 			RK1808_PMU_CLKGATE_CON(0), 0, GFLAGS),
11341135 
1135
-	GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 1, GFLAGS),
1136
+	GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IS_CRITICAL, RK1808_PMU_CLKGATE_CON(0), 1, GFLAGS),
11361137 	GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 2, GFLAGS),
11371138 	GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 3, GFLAGS),
11381139 	GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 4, GFLAGS),
....@@ -1144,27 +1145,6 @@
11441145 
11451146 	MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p,  0,
11461147 			RK1808_PMUGRF_SOC_CON0, 0, 1, MFLAGS)
1147
-};
1148
-
1149
-static const char *const rk1808_critical_clocks[] __initconst = {
1150
-	"msclk_core_niu",
1151
-	"aclk_gic_niu",
1152
-	"aclk_npu_niu",
1153
-	"hclk_npu_niu",
1154
-	"aclk_imem0_niu",
1155
-	"aclk_imem1_niu",
1156
-	"aclk_imem2_niu",
1157
-	"aclk_imem3_niu",
1158
-	"msclk_peri_niu",
1159
-	"lsclk_peri_niu",
1160
-	"hsclk_bus_niu",
1161
-	"msclk_bus_niu",
1162
-	"lsclk_bus_niu",
1163
-	"pclk_pmu_niu",
1164
-	"pclk_top_pre",
1165
-	"pclk_ddr_grf",
1166
-	"aclk_gic",
1167
-	"hsclk_imem",
11681148 };
11691149 
11701150 static void __iomem *rk1808_cru_base;
....@@ -1198,6 +1178,7 @@
11981178 {
11991179 	struct rockchip_clk_provider *ctx;
12001180 	void __iomem *reg_base;
1181
+	struct clk **clks;
12011182 
12021183 	reg_base = of_iomap(np, 0);
12031184 	if (!reg_base) {
....@@ -1213,17 +1194,16 @@
12131194 		iounmap(reg_base);
12141195 		return;
12151196 	}
1197
+	clks = ctx->clk_data.clks;
12161198 
12171199 	rockchip_clk_register_plls(ctx, rk1808_pll_clks,
12181200 				   ARRAY_SIZE(rk1808_pll_clks),
12191201 				   RK1808_GRF_SOC_STATUS0);
12201202 	rockchip_clk_register_branches(ctx, rk1808_clk_branches,
12211203 				       ARRAY_SIZE(rk1808_clk_branches));
1222
-	rockchip_clk_protect_critical(rk1808_critical_clocks,
1223
-				      ARRAY_SIZE(rk1808_critical_clocks));
12241204 
12251205 	rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
1226
-				     mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
1206
+				     3, clks[PLL_APLL], clks[PLL_GPLL],
12271207 				     &rk1808_cpuclk_data, rk1808_cpuclk_rates,
12281208 				     ARRAY_SIZE(rk1808_cpuclk_rates));
12291209 
....@@ -1239,3 +1219,31 @@
12391219 }
12401220 
12411221 CLK_OF_DECLARE(rk1808_cru, "rockchip,rk1808-cru", rk1808_clk_init);
1222
+
1223
+static int __init clk_rk1808_probe(struct platform_device *pdev)
1224
+{
1225
+	struct device_node *np = pdev->dev.of_node;
1226
+
1227
+	rk1808_clk_init(np);
1228
+
1229
+	return 0;
1230
+}
1231
+
1232
+static const struct of_device_id clk_rk1808_match_table[] = {
1233
+	{
1234
+		.compatible = "rockchip,rk1808-cru",
1235
+	},
1236
+	{ }
1237
+};
1238
+MODULE_DEVICE_TABLE(of, clk_rk1808_match_table);
1239
+
1240
+static struct platform_driver clk_rk1808_driver = {
1241
+	.driver		= {
1242
+		.name	= "clk-rk1808",
1243
+		.of_match_table = clk_rk1808_match_table,
1244
+	},
1245
+};
1246
+builtin_platform_driver_probe(clk_rk1808_driver, clk_rk1808_probe);
1247
+
1248
+MODULE_DESCRIPTION("Rockchip RK1808 Clock Driver");
1249
+MODULE_LICENSE("GPL");