add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/drivers/clk/rockchip/clk-mmc-phase.c
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@@ -1,16 +1,7 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * Copyright 2014 Google, Inc
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  * Author: Alexandru M Stan <amstan@chromium.org>
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License as published by
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- * the Free Software Foundation; either version 2 of the License, or
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- * (at your option) any later version.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #include <linux/slab.h>
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@@ -55,27 +46,27 @@
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 static int rockchip_mmc_get_phase(struct clk_hw *hw)
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 {
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 	struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
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-	unsigned long rate = clk_get_rate(hw->clk);
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+	unsigned long rate = clk_hw_get_rate(hw);
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 	u32 raw_value;
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 	u16 degrees;
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 	u32 delay_num = 0;
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-	/* See the comment for rockchip_mmc_set_phase below */
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+	/* Constant signal, no measurable phase shift */
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 	if (!rate)
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-		return -EINVAL;
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+		return 0;
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 	raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift);
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 	degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
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 	if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
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-		/* degrees/delaynum * 10000 */
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+		/* degrees/delaynum * 1000000 */
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 		unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
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-					36 * (rate / 1000000);
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+					36 * (rate / 10000);
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 		delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
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 		delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
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-		degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
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+		degrees += DIV_ROUND_CLOSEST(delay_num * factor, 1000000);
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 	}
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 	return degrees % 360;
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@@ -84,7 +75,7 @@
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 static int rockchip_mmc_set_phase(struct clk_hw *hw, int degrees)
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 {
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 	struct rockchip_mmc_clock *mmc_clock = to_mmc_clock(hw);
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-	unsigned long rate = clk_get_rate(hw->clk);
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+	unsigned long rate = clk_hw_get_rate(hw);
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 	u8 nineties, remainder;
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 	u8 delay_num;
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 	u32 raw_value;
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@@ -201,7 +192,7 @@
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 				const char *const *parent_names, u8 num_parents,
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 				void __iomem *reg, int shift)
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 {
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-	struct clk_init_data init = {};
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+	struct clk_init_data init;
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 	struct rockchip_mmc_clock *mmc_clock;
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 	struct clk *clk;
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 	int ret;