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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/clk/rockchip/clk-ddr.c
....@@ -1,19 +1,9 @@
1
+// SPDX-License-Identifier: GPL-2.0-or-later
12 /*
23  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
34  * Author: Lin Huang <hl@rock-chips.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License as published by
7
- * the Free Software Foundation; either version 2 of the License, or
8
- * (at your option) any later version.
9
- *
10
- * This program is distributed in the hope that it will be useful,
11
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13
- * GNU General Public License for more details.
145  */
156 
16
-#include <drm/drmP.h>
177 #include <linux/arm-smccc.h>
188 #include <linux/clk.h>
199 #include <linux/clk-provider.h>
....@@ -21,17 +11,12 @@
2111 #include <linux/of.h>
2212 #include <linux/rockchip/rockchip_sip.h>
2313 #include <linux/slab.h>
24
-#include <soc/rockchip/rockchip_dmc.h>
2514 #include <soc/rockchip/rockchip_sip.h>
26
-#include <soc/rockchip/scpi.h>
27
-#include <uapi/drm/drm_mode.h>
2815 #ifdef CONFIG_ARM
2916 #include <asm/psci.h>
3017 #endif
3118 
3219 #include "clk.h"
33
-
34
-#define MHZ		(1000000)
3520 
3621 struct rockchip_ddrclk {
3722 	struct clk_hw	hw;
....@@ -46,52 +31,29 @@
4631 
4732 #define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw)
4833 
49
-static int rk_drm_get_lcdc_type(void)
34
+struct share_params_ddrclk {
35
+	u32 hz;
36
+	u32 lcdc_type;
37
+};
38
+
39
+struct rockchip_ddrclk_data {
40
+	void __iomem *params;
41
+	int (*dmcfreq_wait_complete)(void);
42
+};
43
+
44
+static struct rockchip_ddrclk_data ddr_data = {NULL, NULL};
45
+
46
+void rockchip_set_ddrclk_params(void __iomem *params)
5047 {
51
-	struct drm_device *drm;
52
-	u32 lcdc_type = 0;
53
-
54
-	drm = drm_device_get_by_name("rockchip");
55
-	if (drm) {
56
-		struct drm_connector *conn;
57
-
58
-		list_for_each_entry(conn, &drm->mode_config.connector_list,
59
-				    head) {
60
-			if (conn->encoder) {
61
-				lcdc_type = conn->connector_type;
62
-				break;
63
-			}
64
-		}
65
-	}
66
-
67
-	switch (lcdc_type) {
68
-	case DRM_MODE_CONNECTOR_DPI:
69
-	case DRM_MODE_CONNECTOR_LVDS:
70
-		lcdc_type = SCREEN_LVDS;
71
-		break;
72
-	case DRM_MODE_CONNECTOR_DisplayPort:
73
-		lcdc_type = SCREEN_DP;
74
-		break;
75
-	case DRM_MODE_CONNECTOR_HDMIA:
76
-	case DRM_MODE_CONNECTOR_HDMIB:
77
-		lcdc_type = SCREEN_HDMI;
78
-		break;
79
-	case DRM_MODE_CONNECTOR_TV:
80
-		lcdc_type = SCREEN_TVOUT;
81
-		break;
82
-	case DRM_MODE_CONNECTOR_eDP:
83
-		lcdc_type = SCREEN_EDP;
84
-		break;
85
-	case DRM_MODE_CONNECTOR_DSI:
86
-		lcdc_type = SCREEN_MIPI;
87
-		break;
88
-	default:
89
-		lcdc_type = SCREEN_NULL;
90
-		break;
91
-	}
92
-
93
-	return lcdc_type;
48
+	ddr_data.params = params;
9449 }
50
+EXPORT_SYMBOL(rockchip_set_ddrclk_params);
51
+
52
+void rockchip_set_ddrclk_dmcfreq_wait_complete(int (*func)(void))
53
+{
54
+	ddr_data.dmcfreq_wait_complete = func;
55
+}
56
+EXPORT_SYMBOL(rockchip_set_ddrclk_dmcfreq_wait_complete);
9557 
9658 static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate,
9759 					unsigned long prate)
....@@ -139,7 +101,7 @@
139101 	struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
140102 	u32 val;
141103 
142
-	val = clk_readl(ddrclk->reg_base +
104
+	val = readl(ddrclk->reg_base +
143105 			ddrclk->mux_offset) >> ddrclk->mux_shift;
144106 	val &= GENMASK(ddrclk->mux_width - 1, 0);
145107 
....@@ -153,116 +115,24 @@
153115 	.get_parent = rockchip_ddrclk_get_parent,
154116 };
155117 
156
-static u32 ddr_clk_cached;
157
-
158
-static int rockchip_ddrclk_scpi_set_rate(struct clk_hw *hw, unsigned long drate,
159
-					 unsigned long prate)
160
-{
161
-	u32 ret;
162
-	u32 lcdc_type;
163
-
164
-	lcdc_type = rk_drm_get_lcdc_type();
165
-
166
-	ret = scpi_ddr_set_clk_rate(drate / MHZ, lcdc_type);
167
-	if (ret) {
168
-		ddr_clk_cached = ret;
169
-		ret = 0;
170
-	} else {
171
-		ddr_clk_cached = 0;
172
-		ret = -1;
173
-	}
174
-
175
-	return ret;
176
-}
177
-
178
-static unsigned long rockchip_ddrclk_scpi_recalc_rate(struct clk_hw *hw,
179
-						      unsigned long parent_rate)
180
-{
181
-	if (ddr_clk_cached)
182
-		return (MHZ * ddr_clk_cached);
183
-	else
184
-		return (MHZ * scpi_ddr_get_clk_rate());
185
-}
186
-
187
-static long rockchip_ddrclk_scpi_round_rate(struct clk_hw *hw,
188
-					    unsigned long rate,
189
-					    unsigned long *prate)
190
-{
191
-	rate = rate / MHZ;
192
-	rate = (rate / 12) * 12;
193
-
194
-	return (rate * MHZ);
195
-}
196
-
197
-static const struct clk_ops rockchip_ddrclk_scpi_ops = {
198
-	.recalc_rate = rockchip_ddrclk_scpi_recalc_rate,
199
-	.set_rate = rockchip_ddrclk_scpi_set_rate,
200
-	.round_rate = rockchip_ddrclk_scpi_round_rate,
201
-	.get_parent = rockchip_ddrclk_get_parent,
202
-};
203
-
204
-struct share_params {
205
-	u32 hz;
206
-	u32 lcdc_type;
207
-	u32 vop;
208
-	u32 vop_dclk_mode;
209
-	u32 sr_idle_en;
210
-	u32 addr_mcu_el3;
211
-	/*
212
-	 * 1: need to wait flag1
213
-	 * 0: never wait flag1
214
-	 */
215
-	u32 wait_flag1;
216
-	/*
217
-	 * 1: need to wait flag1
218
-	 * 0: never wait flag1
219
-	 */
220
-	u32 wait_flag0;
221
-	u32 complt_hwirq;
222
-	 /* if need, add parameter after */
223
-};
224
-
225
-struct rockchip_ddrclk_data {
226
-	u32 inited_flag;
227
-	void __iomem *share_memory;
228
-};
229
-
230
-static struct rockchip_ddrclk_data ddr_data;
231
-
232
-static void rockchip_ddrclk_data_init(void)
233
-{
234
-	struct arm_smccc_res res;
235
-
236
-	res = sip_smc_request_share_mem(1, SHARE_PAGE_TYPE_DDR);
237
-
238
-	if (!res.a0) {
239
-		ddr_data.share_memory =  (void __iomem *)res.a1;
240
-		ddr_data.inited_flag = 1;
241
-	}
242
-}
243
-
244118 static int rockchip_ddrclk_sip_set_rate_v2(struct clk_hw *hw,
245119 					   unsigned long drate,
246120 					   unsigned long prate)
247121 {
248
-	struct share_params *p;
122
+	struct share_params_ddrclk *p;
249123 	struct arm_smccc_res res;
250124 
251
-	if (!ddr_data.inited_flag)
252
-		rockchip_ddrclk_data_init();
253
-
254
-	p = (struct share_params *)ddr_data.share_memory;
255
-
256
-	p->hz = drate;
257
-	p->lcdc_type = rk_drm_get_lcdc_type();
258
-	p->wait_flag1 = 1;
259
-	p->wait_flag0 = 1;
125
+	p = (struct share_params_ddrclk *)ddr_data.params;
126
+	if (p)
127
+		p->hz = drate;
260128 
261129 	res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
262130 			   ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE);
263131 
264
-	if ((int)res.a1 == SIP_RET_SET_RATE_TIMEOUT)
265
-		rockchip_dmcfreq_wait_complete();
132
+	if ((int)res.a1 == SIP_RET_SET_RATE_TIMEOUT) {
133
+		if (ddr_data.dmcfreq_wait_complete)
134
+			ddr_data.dmcfreq_wait_complete();
135
+	}
266136 
267137 	return res.a0;
268138 }
....@@ -284,15 +154,12 @@
284154 					      unsigned long rate,
285155 					      unsigned long *prate)
286156 {
287
-	struct share_params *p;
157
+	struct share_params_ddrclk *p;
288158 	struct arm_smccc_res res;
289159 
290
-	if (!ddr_data.inited_flag)
291
-		rockchip_ddrclk_data_init();
292
-
293
-	p = (struct share_params *)ddr_data.share_memory;
294
-
295
-	p->hz = rate;
160
+	p = (struct share_params_ddrclk *)ddr_data.params;
161
+	if (p)
162
+		p->hz = rate;
296163 
297164 	res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
298165 			   ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE);
....@@ -309,16 +176,15 @@
309176 	.get_parent = rockchip_ddrclk_get_parent,
310177 };
311178 
312
-struct clk * __init
313
-rockchip_clk_register_ddrclk(const char *name, int flags,
314
-			     const char *const *parent_names,
315
-			     u8 num_parents, int mux_offset,
316
-			     int mux_shift, int mux_width,
317
-			     int div_shift, int div_width,
318
-			     int ddr_flag, void __iomem *reg_base)
179
+struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
180
+					 const char *const *parent_names,
181
+					 u8 num_parents, int mux_offset,
182
+					 int mux_shift, int mux_width,
183
+					 int div_shift, int div_width,
184
+					 int ddr_flag, void __iomem *reg_base)
319185 {
320186 	struct rockchip_ddrclk *ddrclk;
321
-	struct clk_init_data init = {};
187
+	struct clk_init_data init;
322188 	struct clk *clk;
323189 
324190 #ifdef CONFIG_ARM
....@@ -343,14 +209,11 @@
343209 		init.ops = &rockchip_ddrclk_sip_ops;
344210 		break;
345211 #endif
346
-#ifdef CONFIG_ROCKCHIP_DDRCLK_SCPI
347
-	case ROCKCHIP_DDRCLK_SCPI:
348
-		init.ops = &rockchip_ddrclk_scpi_ops;
349
-		break;
350
-#endif
212
+#ifdef CONFIG_ROCKCHIP_DDRCLK_SIP_V2
351213 	case ROCKCHIP_DDRCLK_SIP_V2:
352214 		init.ops = &rockchip_ddrclk_sip_ops_v2;
353215 		break;
216
+#endif
354217 	default:
355218 		pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag);
356219 		kfree(ddrclk);
....@@ -372,3 +235,4 @@
372235 
373236 	return clk;
374237 }
238
+EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);