forked from ~ljy/RK356X_SDK_RELEASE

blame | history | patch | commit | commitdiff
hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/drivers/clk/qcom/gcc-msm8996.c
....@@ -1,14 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3
- *
4
- * This software is licensed under the terms of the GNU General Public
5
- * License version 2, as published by the Free Software Foundation, and
6
- * may be copied, distributed, and modified under those terms.
7
- *
8
- * This program is distributed in the hope that it will be useful,
9
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- * GNU General Public License for more details.
124  */
135 
146 #include <linux/kernel.h>
....@@ -221,6 +213,36 @@
221213 		.parent_names = (const char *[]){ "gpll0_early" },
222214 		.num_parents = 1,
223215 		.ops = &clk_alpha_pll_postdiv_ops,
216
+	},
217
+};
218
+
219
+static struct clk_branch gcc_mmss_gpll0_div_clk = {
220
+	.halt_check = BRANCH_HALT_DELAY,
221
+	.clkr = {
222
+		.enable_reg = 0x5200c,
223
+		.enable_mask = BIT(0),
224
+		.hw.init = &(struct clk_init_data){
225
+			.name = "gcc_mmss_gpll0_div_clk",
226
+			.parent_names = (const char *[]){ "gpll0" },
227
+			.num_parents = 1,
228
+			.flags = CLK_SET_RATE_PARENT,
229
+			.ops = &clk_branch2_ops,
230
+		},
231
+	},
232
+};
233
+
234
+static struct clk_branch gcc_mss_gpll0_div_clk = {
235
+	.halt_check = BRANCH_HALT_DELAY,
236
+	.clkr = {
237
+		.enable_reg = 0x5200c,
238
+		.enable_mask = BIT(2),
239
+		.hw.init = &(struct clk_init_data){
240
+			.name = "gcc_mss_gpll0_div_clk",
241
+			.parent_names = (const char *[]){ "gpll0" },
242
+			.num_parents = 1,
243
+			.flags = CLK_SET_RATE_PARENT,
244
+			.ops = &clk_branch2_ops
245
+		},
224246 	},
225247 };
226248 
....@@ -2945,6 +2967,34 @@
29452967 	},
29462968 };
29472969 
2970
+static struct clk_branch gcc_dcc_ahb_clk = {
2971
+	.halt_reg = 0x84004,
2972
+	.clkr = {
2973
+		.enable_reg = 0x84004,
2974
+		.enable_mask = BIT(0),
2975
+		.hw.init = &(struct clk_init_data){
2976
+			.name = "gcc_dcc_ahb_clk",
2977
+			.parent_names = (const char *[]){ "config_noc_clk_src" },
2978
+			.num_parents = 1,
2979
+			.ops = &clk_branch2_ops,
2980
+		},
2981
+	},
2982
+};
2983
+
2984
+static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = {
2985
+	.halt_reg = 0x85000,
2986
+	.clkr = {
2987
+		.enable_reg = 0x85000,
2988
+		.enable_mask = BIT(0),
2989
+		.hw.init = &(struct clk_init_data){
2990
+			.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",
2991
+			.parent_names = (const char *[]){ "config_noc_clk_src" },
2992
+			.num_parents = 1,
2993
+			.ops = &clk_branch2_ops,
2994
+		},
2995
+	},
2996
+};
2997
+
29482998 static struct clk_branch gcc_qspi_ahb_clk = {
29492999 	.halt_reg = 0x8b004,
29503000 	.clkr = {
....@@ -2982,7 +3032,10 @@
29823032 		.enable_mask = BIT(0),
29833033 		.hw.init = &(struct clk_init_data){
29843034 			.name = "gcc_usb3_clkref_clk",
2985
-			.parent_names = (const char *[]){ "xo" },
3035
+			.parent_data = &(const struct clk_parent_data){
3036
+				.fw_name = "cxo2",
3037
+				.name = "xo",
3038
+			},
29863039 			.num_parents = 1,
29873040 			.ops = &clk_branch2_ops,
29883041 		},
....@@ -2996,7 +3049,27 @@
29963049 		.enable_mask = BIT(0),
29973050 		.hw.init = &(struct clk_init_data){
29983051 			.name = "gcc_hdmi_clkref_clk",
2999
-			.parent_names = (const char *[]){ "xo" },
3052
+			.parent_data = &(const struct clk_parent_data){
3053
+				.fw_name = "cxo2",
3054
+				.name = "xo",
3055
+			},
3056
+			.num_parents = 1,
3057
+			.ops = &clk_branch2_ops,
3058
+		},
3059
+	},
3060
+};
3061
+
3062
+static struct clk_branch gcc_edp_clkref_clk = {
3063
+	.halt_reg = 0x88004,
3064
+	.clkr = {
3065
+		.enable_reg = 0x88004,
3066
+		.enable_mask = BIT(0),
3067
+		.hw.init = &(struct clk_init_data){
3068
+			.name = "gcc_edp_clkref_clk",
3069
+			.parent_data = &(const struct clk_parent_data){
3070
+				.fw_name = "cxo2",
3071
+				.name = "xo",
3072
+			},
30003073 			.num_parents = 1,
30013074 			.ops = &clk_branch2_ops,
30023075 		},
....@@ -3010,7 +3083,10 @@
30103083 		.enable_mask = BIT(0),
30113084 		.hw.init = &(struct clk_init_data){
30123085 			.name = "gcc_ufs_clkref_clk",
3013
-			.parent_names = (const char *[]){ "xo" },
3086
+			.parent_data = &(const struct clk_parent_data){
3087
+				.fw_name = "cxo2",
3088
+				.name = "xo",
3089
+			},
30143090 			.num_parents = 1,
30153091 			.ops = &clk_branch2_ops,
30163092 		},
....@@ -3024,7 +3100,10 @@
30243100 		.enable_mask = BIT(0),
30253101 		.hw.init = &(struct clk_init_data){
30263102 			.name = "gcc_pcie_clkref_clk",
3027
-			.parent_names = (const char *[]){ "xo" },
3103
+			.parent_data = &(const struct clk_parent_data){
3104
+				.fw_name = "cxo2",
3105
+				.name = "xo",
3106
+			},
30283107 			.num_parents = 1,
30293108 			.ops = &clk_branch2_ops,
30303109 		},
....@@ -3038,7 +3117,10 @@
30383117 		.enable_mask = BIT(0),
30393118 		.hw.init = &(struct clk_init_data){
30403119 			.name = "gcc_rx2_usb2_clkref_clk",
3041
-			.parent_names = (const char *[]){ "xo" },
3120
+			.parent_data = &(const struct clk_parent_data){
3121
+				.fw_name = "cxo2",
3122
+				.name = "xo",
3123
+			},
30423124 			.num_parents = 1,
30433125 			.ops = &clk_branch2_ops,
30443126 		},
....@@ -3052,7 +3134,66 @@
30523134 		.enable_mask = BIT(0),
30533135 		.hw.init = &(struct clk_init_data){
30543136 			.name = "gcc_rx1_usb2_clkref_clk",
3055
-			.parent_names = (const char *[]){ "xo" },
3137
+			.parent_data = &(const struct clk_parent_data){
3138
+				.fw_name = "cxo2",
3139
+				.name = "xo",
3140
+			},
3141
+			.num_parents = 1,
3142
+			.ops = &clk_branch2_ops,
3143
+		},
3144
+	},
3145
+};
3146
+
3147
+static struct clk_branch gcc_mss_cfg_ahb_clk = {
3148
+	.halt_reg = 0x8a000,
3149
+	.clkr = {
3150
+		.enable_reg = 0x8a000,
3151
+		.enable_mask = BIT(0),
3152
+		.hw.init = &(struct clk_init_data){
3153
+			.name = "gcc_mss_cfg_ahb_clk",
3154
+			.parent_names = (const char *[]){ "config_noc_clk_src" },
3155
+			.num_parents = 1,
3156
+			.ops = &clk_branch2_ops,
3157
+		},
3158
+	},
3159
+};
3160
+
3161
+static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = {
3162
+	.halt_reg = 0x8a004,
3163
+	.clkr = {
3164
+		.enable_reg = 0x8a004,
3165
+		.enable_mask = BIT(0),
3166
+		.hw.init = &(struct clk_init_data){
3167
+			.name = "gcc_mss_mnoc_bimc_axi_clk",
3168
+			.parent_names = (const char *[]){ "system_noc_clk_src" },
3169
+			.num_parents = 1,
3170
+			.ops = &clk_branch2_ops,
3171
+		},
3172
+	},
3173
+};
3174
+
3175
+static struct clk_branch gcc_mss_snoc_axi_clk = {
3176
+	.halt_reg = 0x8a024,
3177
+	.clkr = {
3178
+		.enable_reg = 0x8a024,
3179
+		.enable_mask = BIT(0),
3180
+		.hw.init = &(struct clk_init_data){
3181
+			.name = "gcc_mss_snoc_axi_clk",
3182
+			.parent_names = (const char *[]){ "system_noc_clk_src" },
3183
+			.num_parents = 1,
3184
+			.ops = &clk_branch2_ops,
3185
+		},
3186
+	},
3187
+};
3188
+
3189
+static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
3190
+	.halt_reg = 0x8a028,
3191
+	.clkr = {
3192
+		.enable_reg = 0x8a028,
3193
+		.enable_mask = BIT(0),
3194
+		.hw.init = &(struct clk_init_data){
3195
+			.name = "gcc_mss_q6_bimc_axi_clk",
3196
+			.parent_names = (const char *[]){ "system_noc_clk_src" },
30563197 			.num_parents = 1,
30573198 			.ops = &clk_branch2_ops,
30583199 		},
....@@ -3329,6 +3470,15 @@
33293470 	[GCC_PCIE_CLKREF_CLK] = &gcc_pcie_clkref_clk.clkr,
33303471 	[GCC_RX2_USB2_CLKREF_CLK] = &gcc_rx2_usb2_clkref_clk.clkr,
33313472 	[GCC_RX1_USB2_CLKREF_CLK] = &gcc_rx1_usb2_clkref_clk.clkr,
3473
+	[GCC_EDP_CLKREF_CLK] = &gcc_edp_clkref_clk.clkr,
3474
+	[GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr,
3475
+	[GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
3476
+	[GCC_MSS_SNOC_AXI_CLK] = &gcc_mss_snoc_axi_clk.clkr,
3477
+	[GCC_MSS_MNOC_BIMC_AXI_CLK] = &gcc_mss_mnoc_bimc_axi_clk.clkr,
3478
+	[GCC_DCC_AHB_CLK] = &gcc_dcc_ahb_clk.clkr,
3479
+	[GCC_AGGRE0_NOC_MPU_CFG_AHB_CLK] = &gcc_aggre0_noc_mpu_cfg_ahb_clk.clkr,
3480
+	[GCC_MMSS_GPLL0_DIV_CLK] = &gcc_mmss_gpll0_div_clk.clkr,
3481
+	[GCC_MSS_GPLL0_DIV_CLK] = &gcc_mss_gpll0_div_clk.clkr,
33323482 };
33333483 
33343484 static struct gdsc *gcc_msm8996_gdscs[] = {
....@@ -3468,6 +3618,8 @@
34683618 	.num_resets = ARRAY_SIZE(gcc_msm8996_resets),
34693619 	.gdscs = gcc_msm8996_gdscs,
34703620 	.num_gdscs = ARRAY_SIZE(gcc_msm8996_gdscs),
3621
+	.clk_hws = gcc_msm8996_hws,
3622
+	.num_clk_hws = ARRAY_SIZE(gcc_msm8996_hws),
34713623 };
34723624 
34733625 static const struct of_device_id gcc_msm8996_match_table[] = {
....@@ -3478,8 +3630,6 @@
34783630 
34793631 static int gcc_msm8996_probe(struct platform_device *pdev)
34803632 {
3481
-	struct device *dev = &pdev->dev;
3482
-	int i, ret;
34833633 	struct regmap *regmap;
34843634 
34853635 	regmap = qcom_cc_map(pdev, &gcc_msm8996_desc);
....@@ -3491,12 +3641,6 @@
34913641 	 * turned off by hardware during certain apps low power modes.
34923642 	 */
34933643 	regmap_update_bits(regmap, 0x52008, BIT(21), BIT(21));
3494
-
3495
-	for (i = 0; i < ARRAY_SIZE(gcc_msm8996_hws); i++) {
3496
-		ret = devm_clk_hw_register(dev, gcc_msm8996_hws[i]);
3497
-		if (ret)
3498
-			return ret;
3499
-	}
35003644 
35013645 	return qcom_cc_really_probe(pdev, &gcc_msm8996_desc, regmap);
35023646 }