~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,20 +1,14 @@
	1	+// SPDX-License-Identifier: GPL-2.0
1	2	/*
2	3	* ti-sysc.c - Texas Instruments sysc interconnect target driver
3		- *
4		- * This program is free software; you can redistribute it and/or modify
5		- * it under the terms of the GNU General Public License version 2 as
6		- * published by the Free Software Foundation.
7		- *
8		- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9		- * kind, whether express or implied; without even the implied warranty
10		- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11		- * GNU General Public License for more details.
12	4	*/
13	5
14	6	#include <linux/io.h>
15	7	#include <linux/clk.h>
16	8	#include <linux/clkdev.h>
	9	+#include <linux/cpu_pm.h>
17	10	#include <linux/delay.h>
	11	+#include <linux/list.h>
18	12	#include <linux/module.h>
19	13	#include <linux/platform_device.h>
20	14	#include <linux/pm_domain.h>
..	..	@@ -23,15 +17,56 @@
23	17	#include <linux/of_address.h>
24	18	#include <linux/of_platform.h>
25	19	#include <linux/slab.h>
	20	+#include <linux/sys_soc.h>
	21	+#include <linux/timekeeping.h>
26	22	#include <linux/iopoll.h>
27	23
28	24	#include <linux/platform_data/ti-sysc.h>
29	25
30	26	#include <dt-bindings/bus/ti-sysc.h>
31	27
	28	+#define DIS_ISP BIT(2)
	29	+#define DIS_IVA BIT(1)
	30	+#define DIS_SGX BIT(0)
	31	+
	32	+#define SOC_FLAG(match, flag) { .machine = match, .data = (void *)(flag), }
	33	+
32	34	#define MAX_MODULE_SOFTRESET_WAIT 10000
33	35
34		-static const char * const reg_names[] = { "rev", "sysc", "syss", };
	36	+enum sysc_soc {
	37	+ SOC_UNKNOWN,
	38	+ SOC_2420,
	39	+ SOC_2430,
	40	+ SOC_3430,
	41	+ SOC_AM35,
	42	+ SOC_3630,
	43	+ SOC_4430,
	44	+ SOC_4460,
	45	+ SOC_4470,
	46	+ SOC_5430,
	47	+ SOC_AM3,
	48	+ SOC_AM4,
	49	+ SOC_DRA7,
	50	+};
	51	+
	52	+struct sysc_address {
	53	+ unsigned long base;
	54	+ struct list_head node;
	55	+};
	56	+
	57	+struct sysc_module {
	58	+ struct sysc *ddata;
	59	+ struct list_head node;
	60	+};
	61	+
	62	+struct sysc_soc_info {
	63	+ unsigned long general_purpose:1;
	64	+ enum sysc_soc soc;
	65	+ struct mutex list_lock; /* disabled and restored modules list lock */
	66	+ struct list_head disabled_modules;
	67	+ struct list_head restored_modules;
	68	+ struct notifier_block nb;
	69	+};
35	70
36	71	enum sysc_clocks {
37	72	SYSC_FCK,
..	..	@@ -47,7 +82,12 @@
47	82	SYSC_MAX_CLOCKS,
48	83	};
49	84
50		-static const char * const clock_names[SYSC_ICK + 1] = { "fck", "ick", };
	85	+static struct sysc_soc_info *sysc_soc;
	86	+static const char * const reg_names[] = { "rev", "sysc", "syss", };
	87	+static const char * const clock_names[SYSC_MAX_CLOCKS] = {
	88	+ "fck", "ick", "opt0", "opt1", "opt2", "opt3", "opt4",
	89	+ "opt5", "opt6", "opt7",
	90	+};
51	91
52	92	#define SYSC_IDLEMODE_MASK 3
53	93	#define SYSC_CLOCKACTIVITY_MASK 3
..	..	@@ -59,15 +99,30 @@
59	99	* @module_size: size of the interconnect target module
60	100	* @module_va: virtual address of the interconnect target module
61	101	* @offsets: register offsets from module base
	102	+ * @mdata: ti-sysc to hwmod translation data for a module
62	103	* @clocks: clocks used by the interconnect target module
63	104	* @clock_roles: clock role names for the found clocks
64	105	* @nr_clocks: number of clocks used by the interconnect target module
	106	+ * @rsts: resets used by the interconnect target module
65	107	* @legacy_mode: configured for legacy mode if set
66	108	* @cap: interconnect target module capabilities
67	109	* @cfg: interconnect target module configuration
	110	+ * @cookie: data used by legacy platform callbacks
68	111	* @name: name if available
69	112	* @revision: interconnect target module revision
	113	+ * @reserved: target module is reserved and already in use
	114	+ * @enabled: sysc runtime enabled status
70	115	* @needs_resume: runtime resume needed on resume from suspend
	116	+ * @child_needs_resume: runtime resume needed for child on resume from suspend
	117	+ * @disable_on_idle: status flag used for disabling modules with resets
	118	+ * @idle_work: work structure used to perform delayed idle on a module
	119	+ * @pre_reset_quirk: module specific pre-reset quirk
	120	+ * @post_reset_quirk: module specific post-reset quirk
	121	+ * @reset_done_quirk: module specific reset done quirk
	122	+ * @module_enable_quirk: module specific enable quirk
	123	+ * @module_disable_quirk: module specific disable quirk
	124	+ * @module_unlock_quirk: module specific sysconfig unlock quirk
	125	+ * @module_lock_quirk: module specific sysconfig lock quirk
71	126	*/
72	127	struct sysc {
73	128	struct device *dev;
..	..	@@ -75,6 +130,7 @@
75	130	u32 module_size;
76	131	void __iomem *module_va;
77	132	int offsets[SYSC_MAX_REGS];
	133	+ struct ti_sysc_module_data *mdata;
78	134	struct clk **clocks;
79	135	const char **clock_roles;
80	136	int nr_clocks;
..	..	@@ -85,17 +141,39 @@
85	141	struct ti_sysc_cookie cookie;
86	142	const char *name;
87	143	u32 revision;
88		- bool enabled;
89		- bool needs_resume;
90		- bool child_needs_resume;
	144	+ unsigned int reserved:1;
	145	+ unsigned int enabled:1;
	146	+ unsigned int needs_resume:1;
	147	+ unsigned int child_needs_resume:1;
91	148	struct delayed_work idle_work;
	149	+ void (pre_reset_quirk)(struct sysc sysc);
	150	+ void (post_reset_quirk)(struct sysc sysc);
	151	+ void (reset_done_quirk)(struct sysc sysc);
	152	+ void (module_enable_quirk)(struct sysc sysc);
	153	+ void (module_disable_quirk)(struct sysc sysc);
	154	+ void (module_unlock_quirk)(struct sysc sysc);
	155	+ void (module_lock_quirk)(struct sysc sysc);
92	156	};
93	157
94	158	static void sysc_parse_dts_quirks(struct sysc ddata, struct device_node np,
95	159	bool is_child);
96	160
97		-void sysc_write(struct sysc *ddata, int offset, u32 value)
	161	+static void sysc_write(struct sysc *ddata, int offset, u32 value)
98	162	{
	163	+ if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
	164	+ writew_relaxed(value & 0xffff, ddata->module_va + offset);
	165	+
	166	+ /* Only i2c revision has LO and HI register with stride of 4 */
	167	+ if (ddata->offsets[SYSC_REVISION] >= 0 &&
	168	+ offset == ddata->offsets[SYSC_REVISION]) {
	169	+ u16 hi = value >> 16;
	170	+
	171	+ writew_relaxed(hi, ddata->module_va + offset + 4);
	172	+ }
	173	+
	174	+ return;
	175	+ }
	176	+
99	177	writel_relaxed(value, ddata->module_va + offset);
100	178	}
101	179
..	..	@@ -105,7 +183,14 @@
105	183	u32 val;
106	184
107	185	val = readw_relaxed(ddata->module_va + offset);
108		- val \|= (readw_relaxed(ddata->module_va + offset + 4) << 16);
	186	+
	187	+ /* Only i2c revision has LO and HI register with stride of 4 */
	188	+ if (ddata->offsets[SYSC_REVISION] >= 0 &&
	189	+ offset == ddata->offsets[SYSC_REVISION]) {
	190	+ u16 tmp = readw_relaxed(ddata->module_va + offset + 4);
	191	+
	192	+ val \|= tmp << 16;
	193	+ }
109	194
110	195	return val;
111	196	}
..	..	@@ -126,6 +211,172 @@
126	211	return 0;
127	212
128	213	return sysc_read(ddata, offset);
	214	+}
	215	+
	216	+static u32 sysc_read_sysconfig(struct sysc *ddata)
	217	+{
	218	+ int offset = ddata->offsets[SYSC_SYSCONFIG];
	219	+
	220	+ if (offset < 0)
	221	+ return 0;
	222	+
	223	+ return sysc_read(ddata, offset);
	224	+}
	225	+
	226	+static u32 sysc_read_sysstatus(struct sysc *ddata)
	227	+{
	228	+ int offset = ddata->offsets[SYSC_SYSSTATUS];
	229	+
	230	+ if (offset < 0)
	231	+ return 0;
	232	+
	233	+ return sysc_read(ddata, offset);
	234	+}
	235	+
	236	+static int sysc_poll_reset_sysstatus(struct sysc *ddata)
	237	+{
	238	+ int error, retries;
	239	+ u32 syss_done, rstval;
	240	+
	241	+ if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
	242	+ syss_done = 0;
	243	+ else
	244	+ syss_done = ddata->cfg.syss_mask;
	245	+
	246	+ if (likely(!timekeeping_suspended)) {
	247	+ error = readx_poll_timeout_atomic(sysc_read_sysstatus, ddata,
	248	+ rstval, (rstval & ddata->cfg.syss_mask) ==
	249	+ syss_done, 100, MAX_MODULE_SOFTRESET_WAIT);
	250	+ } else {
	251	+ retries = MAX_MODULE_SOFTRESET_WAIT;
	252	+ while (retries--) {
	253	+ rstval = sysc_read_sysstatus(ddata);
	254	+ if ((rstval & ddata->cfg.syss_mask) == syss_done)
	255	+ return 0;
	256	+ udelay(2); /* Account for udelay flakeyness */
	257	+ }
	258	+ error = -ETIMEDOUT;
	259	+ }
	260	+
	261	+ return error;
	262	+}
	263	+
	264	+static int sysc_poll_reset_sysconfig(struct sysc *ddata)
	265	+{
	266	+ int error, retries;
	267	+ u32 sysc_mask, rstval;
	268	+
	269	+ sysc_mask = BIT(ddata->cap->regbits->srst_shift);
	270	+
	271	+ if (likely(!timekeeping_suspended)) {
	272	+ error = readx_poll_timeout_atomic(sysc_read_sysconfig, ddata,
	273	+ rstval, !(rstval & sysc_mask),
	274	+ 100, MAX_MODULE_SOFTRESET_WAIT);
	275	+ } else {
	276	+ retries = MAX_MODULE_SOFTRESET_WAIT;
	277	+ while (retries--) {
	278	+ rstval = sysc_read_sysconfig(ddata);
	279	+ if (!(rstval & sysc_mask))
	280	+ return 0;
	281	+ udelay(2); /* Account for udelay flakeyness */
	282	+ }
	283	+ error = -ETIMEDOUT;
	284	+ }
	285	+
	286	+ return error;
	287	+}
	288	+
	289	+/* Poll on reset status */
	290	+static int sysc_wait_softreset(struct sysc *ddata)
	291	+{
	292	+ int syss_offset, error = 0;
	293	+
	294	+ if (ddata->cap->regbits->srst_shift < 0)
	295	+ return 0;
	296	+
	297	+ syss_offset = ddata->offsets[SYSC_SYSSTATUS];
	298	+
	299	+ if (syss_offset >= 0)
	300	+ error = sysc_poll_reset_sysstatus(ddata);
	301	+ else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS)
	302	+ error = sysc_poll_reset_sysconfig(ddata);
	303	+
	304	+ return error;
	305	+}
	306	+
	307	+static int sysc_add_named_clock_from_child(struct sysc *ddata,
	308	+ const char *name,
	309	+ const char *optfck_name)
	310	+{
	311	+ struct device_node *np = ddata->dev->of_node;
	312	+ struct device_node *child;
	313	+ struct clk_lookup *cl;
	314	+ struct clk *clock;
	315	+ const char *n;
	316	+
	317	+ if (name)
	318	+ n = name;
	319	+ else
	320	+ n = optfck_name;
	321	+
	322	+ /* Does the clock alias already exist? */
	323	+ clock = of_clk_get_by_name(np, n);
	324	+ if (!IS_ERR(clock)) {
	325	+ clk_put(clock);
	326	+
	327	+ return 0;
	328	+ }
	329	+
	330	+ child = of_get_next_available_child(np, NULL);
	331	+ if (!child)
	332	+ return -ENODEV;
	333	+
	334	+ clock = devm_get_clk_from_child(ddata->dev, child, name);
	335	+ if (IS_ERR(clock))
	336	+ return PTR_ERR(clock);
	337	+
	338	+ /*
	339	+ * Use clkdev_add() instead of clkdev_alloc() to avoid the MAX_DEV_ID
	340	+ * limit for clk_get(). If cl ever needs to be freed, it should be done
	341	+ * with clkdev_drop().
	342	+ */
	343	+ cl = kcalloc(1, sizeof(*cl), GFP_KERNEL);
	344	+ if (!cl)
	345	+ return -ENOMEM;
	346	+
	347	+ cl->con_id = n;
	348	+ cl->dev_id = dev_name(ddata->dev);
	349	+ cl->clk = clock;
	350	+ clkdev_add(cl);
	351	+
	352	+ clk_put(clock);
	353	+
	354	+ return 0;
	355	+}
	356	+
	357	+static int sysc_init_ext_opt_clock(struct sysc ddata, const char name)
	358	+{
	359	+ const char *optfck_name;
	360	+ int error, index;
	361	+
	362	+ if (ddata->nr_clocks < SYSC_OPTFCK0)
	363	+ index = SYSC_OPTFCK0;
	364	+ else
	365	+ index = ddata->nr_clocks;
	366	+
	367	+ if (name)
	368	+ optfck_name = name;
	369	+ else
	370	+ optfck_name = clock_names[index];
	371	+
	372	+ error = sysc_add_named_clock_from_child(ddata, name, optfck_name);
	373	+ if (error)
	374	+ return error;
	375	+
	376	+ ddata->clock_roles[index] = optfck_name;
	377	+ ddata->nr_clocks++;
	378	+
	379	+ return 0;
129	380	}
130	381
131	382	static int sysc_get_one_clock(struct sysc ddata, const char name)
..	..	@@ -153,9 +404,6 @@
153	404
154	405	ddata->clocks[index] = devm_clk_get(ddata->dev, name);
155	406	if (IS_ERR(ddata->clocks[index])) {
156		- if (PTR_ERR(ddata->clocks[index]) == -ENOENT)
157		- return 0;
158		-
159	407	dev_err(ddata->dev, "clock get error for %s: %li\n",
160	408	name, PTR_ERR(ddata->clocks[index]));
161	409
..	..	@@ -199,6 +447,12 @@
199	447	if (ddata->nr_clocks < 1)
200	448	return 0;
201	449
	450	+ if ((ddata->cfg.quirks & SYSC_QUIRK_EXT_OPT_CLOCK)) {
	451	+ error = sysc_init_ext_opt_clock(ddata, NULL);
	452	+ if (error)
	453	+ return error;
	454	+ }
	455	+
202	456	if (ddata->nr_clocks > SYSC_MAX_CLOCKS) {
203	457	dev_err(ddata->dev, "too many clocks for %pOF\n", np);
204	458
..	..	@@ -210,6 +464,12 @@
210	464
211	465	return -EINVAL;
212	466	}
	467	+
	468	+ /* Always add a slot for main clocks fck and ick even if unused */
	469	+ if (!nr_fck)
	470	+ ddata->nr_clocks++;
	471	+ if (!nr_ick)
	472	+ ddata->nr_clocks++;
213	473
214	474	ddata->clocks = devm_kcalloc(ddata->dev,
215	475	ddata->nr_clocks, sizeof(*ddata->clocks),
..	..	@@ -224,47 +484,155 @@
224	484	continue;
225	485
226	486	error = sysc_get_one_clock(ddata, name);
227		- if (error && error != -ENOENT)
	487	+ if (error)
228	488	return error;
229	489	}
230	490
231	491	return 0;
232	492	}
233	493
	494	+static int sysc_enable_main_clocks(struct sysc *ddata)
	495	+{
	496	+ struct clk *clock;
	497	+ int i, error;
	498	+
	499	+ if (!ddata->clocks)
	500	+ return 0;
	501	+
	502	+ for (i = 0; i < SYSC_OPTFCK0; i++) {
	503	+ clock = ddata->clocks[i];
	504	+
	505	+ /* Main clocks may not have ick */
	506	+ if (IS_ERR_OR_NULL(clock))
	507	+ continue;
	508	+
	509	+ error = clk_enable(clock);
	510	+ if (error)
	511	+ goto err_disable;
	512	+ }
	513	+
	514	+ return 0;
	515	+
	516	+err_disable:
	517	+ for (i--; i >= 0; i--) {
	518	+ clock = ddata->clocks[i];
	519	+
	520	+ /* Main clocks may not have ick */
	521	+ if (IS_ERR_OR_NULL(clock))
	522	+ continue;
	523	+
	524	+ clk_disable(clock);
	525	+ }
	526	+
	527	+ return error;
	528	+}
	529	+
	530	+static void sysc_disable_main_clocks(struct sysc *ddata)
	531	+{
	532	+ struct clk *clock;
	533	+ int i;
	534	+
	535	+ if (!ddata->clocks)
	536	+ return;
	537	+
	538	+ for (i = 0; i < SYSC_OPTFCK0; i++) {
	539	+ clock = ddata->clocks[i];
	540	+ if (IS_ERR_OR_NULL(clock))
	541	+ continue;
	542	+
	543	+ clk_disable(clock);
	544	+ }
	545	+}
	546	+
	547	+static int sysc_enable_opt_clocks(struct sysc *ddata)
	548	+{
	549	+ struct clk *clock;
	550	+ int i, error;
	551	+
	552	+ if (!ddata->clocks \|\| ddata->nr_clocks < SYSC_OPTFCK0 + 1)
	553	+ return 0;
	554	+
	555	+ for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
	556	+ clock = ddata->clocks[i];
	557	+
	558	+ /* Assume no holes for opt clocks */
	559	+ if (IS_ERR_OR_NULL(clock))
	560	+ return 0;
	561	+
	562	+ error = clk_enable(clock);
	563	+ if (error)
	564	+ goto err_disable;
	565	+ }
	566	+
	567	+ return 0;
	568	+
	569	+err_disable:
	570	+ for (i--; i >= 0; i--) {
	571	+ clock = ddata->clocks[i];
	572	+ if (IS_ERR_OR_NULL(clock))
	573	+ continue;
	574	+
	575	+ clk_disable(clock);
	576	+ }
	577	+
	578	+ return error;
	579	+}
	580	+
	581	+static void sysc_disable_opt_clocks(struct sysc *ddata)
	582	+{
	583	+ struct clk *clock;
	584	+ int i;
	585	+
	586	+ if (!ddata->clocks \|\| ddata->nr_clocks < SYSC_OPTFCK0 + 1)
	587	+ return;
	588	+
	589	+ for (i = SYSC_OPTFCK0; i < SYSC_MAX_CLOCKS; i++) {
	590	+ clock = ddata->clocks[i];
	591	+
	592	+ /* Assume no holes for opt clocks */
	593	+ if (IS_ERR_OR_NULL(clock))
	594	+ return;
	595	+
	596	+ clk_disable(clock);
	597	+ }
	598	+}
	599	+
	600	+static void sysc_clkdm_deny_idle(struct sysc *ddata)
	601	+{
	602	+ struct ti_sysc_platform_data *pdata;
	603	+
	604	+ if (ddata->legacy_mode \|\| (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
	605	+ return;
	606	+
	607	+ pdata = dev_get_platdata(ddata->dev);
	608	+ if (pdata && pdata->clkdm_deny_idle)
	609	+ pdata->clkdm_deny_idle(ddata->dev, &ddata->cookie);
	610	+}
	611	+
	612	+static void sysc_clkdm_allow_idle(struct sysc *ddata)
	613	+{
	614	+ struct ti_sysc_platform_data *pdata;
	615	+
	616	+ if (ddata->legacy_mode \|\| (ddata->cfg.quirks & SYSC_QUIRK_CLKDM_NOAUTO))
	617	+ return;
	618	+
	619	+ pdata = dev_get_platdata(ddata->dev);
	620	+ if (pdata && pdata->clkdm_allow_idle)
	621	+ pdata->clkdm_allow_idle(ddata->dev, &ddata->cookie);
	622	+}
	623	+
234	624	/**
235		- * sysc_init_resets - reset module on init
	625	+ * sysc_init_resets - init rstctrl reset line if configured
236	626	* @ddata: device driver data
237	627	*
238		- * A module can have both OCP softreset control and external rstctrl.
239		- * If more complicated rstctrl resets are needed, please handle these
240		- * directly from the child device driver and map only the module reset
241		- * for the parent interconnect target module device.
242		- *
243		- * Automatic reset of the module on init can be skipped with the
244		- * "ti,no-reset-on-init" device tree property.
	628	+ * See sysc_rstctrl_reset_deassert().
245	629	*/
246	630	static int sysc_init_resets(struct sysc *ddata)
247	631	{
248		- int error;
249		-
250	632	ddata->rsts =
251		- devm_reset_control_array_get_optional_exclusive(ddata->dev);
252		- if (IS_ERR(ddata->rsts))
253		- return PTR_ERR(ddata->rsts);
	633	+ devm_reset_control_get_optional_shared(ddata->dev, "rstctrl");
254	634
255		- if (ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
256		- goto deassert;
257		-
258		- error = reset_control_assert(ddata->rsts);
259		- if (error)
260		- return error;
261		-
262		-deassert:
263		- error = reset_control_deassert(ddata->rsts);
264		- if (error)
265		- return error;
266		-
267		- return 0;
	635	+ return PTR_ERR_OR_ZERO(ddata->rsts);
268	636	}
269	637
270	638	/**
..	..	@@ -317,6 +685,51 @@
317	685	ddata->module_size = be32_to_cpup(ranges);
318	686
319	687	return 0;
	688	+}
	689	+
	690	+/* Interconnect instances to probe before l4_per instances */
	691	+static struct resource early_bus_ranges[] = {
	692	+ /* am3/4 l4_wkup */
	693	+ { .start = 0x44c00000, .end = 0x44c00000 + 0x300000, },
	694	+ /* omap4/5 and dra7 l4_cfg */
	695	+ { .start = 0x4a000000, .end = 0x4a000000 + 0x300000, },
	696	+ /* omap4 l4_wkup */
	697	+ { .start = 0x4a300000, .end = 0x4a300000 + 0x30000, },
	698	+ /* omap5 and dra7 l4_wkup without dra7 dcan segment */
	699	+ { .start = 0x4ae00000, .end = 0x4ae00000 + 0x30000, },
	700	+};
	701	+
	702	+static atomic_t sysc_defer = ATOMIC_INIT(10);
	703	+
	704	+/**
	705	+ * sysc_defer_non_critical - defer non_critical interconnect probing
	706	+ * @ddata: device driver data
	707	+ *
	708	+ * We want to probe l4_cfg and l4_wkup interconnect instances before any
	709	+ * l4_per instances as l4_per instances depend on resources on l4_cfg and
	710	+ * l4_wkup interconnects.
	711	+ */
	712	+static int sysc_defer_non_critical(struct sysc *ddata)
	713	+{
	714	+ struct resource *res;
	715	+ int i;
	716	+
	717	+ if (!atomic_read(&sysc_defer))
	718	+ return 0;
	719	+
	720	+ for (i = 0; i < ARRAY_SIZE(early_bus_ranges); i++) {
	721	+ res = &early_bus_ranges[i];
	722	+ if (ddata->module_pa >= res->start &&
	723	+ ddata->module_pa <= res->end) {
	724	+ atomic_set(&sysc_defer, 0);
	725	+
	726	+ return 0;
	727	+ }
	728	+ }
	729	+
	730	+ atomic_dec_if_positive(&sysc_defer);
	731	+
	732	+ return -EPROBE_DEFER;
320	733	}
321	734
322	735	static struct device_node *stdout_path;
..	..	@@ -372,33 +785,25 @@
372	785	* node but children have "ti,hwmods". These belong to the interconnect
373	786	* target node and are managed by this driver.
374	787	*/
375		-static int sysc_check_one_child(struct sysc *ddata,
376		- struct device_node *np)
	788	+static void sysc_check_one_child(struct sysc *ddata,
	789	+ struct device_node *np)
377	790	{
378	791	const char *name;
379	792
380	793	name = of_get_property(np, "ti,hwmods", NULL);
381		- if (name)
	794	+ if (name && !of_device_is_compatible(np, "ti,sysc"))
382	795	dev_warn(ddata->dev, "really a child ti,hwmods property?");
383	796
384	797	sysc_check_quirk_stdout(ddata, np);
385	798	sysc_parse_dts_quirks(ddata, np, true);
386		-
387		- return 0;
388	799	}
389	800
390		-static int sysc_check_children(struct sysc *ddata)
	801	+static void sysc_check_children(struct sysc *ddata)
391	802	{
392	803	struct device_node *child;
393		- int error;
394	804
395		- for_each_child_of_node(ddata->dev->of_node, child) {
396		- error = sysc_check_one_child(ddata, child);
397		- if (error)
398		- return error;
399		- }
400		-
401		- return 0;
	805	+ for_each_child_of_node(ddata->dev->of_node, child)
	806	+ sysc_check_one_child(ddata, child);
402	807	}
403	808
404	809	/*
..	..	@@ -489,12 +894,6 @@
489	894	nr_regs++;
490	895	}
491	896
492		- if (nr_regs < 1) {
493		- dev_err(ddata->dev, "missing registers\n");
494		-
495		- return -EINVAL;
496		- }
497		-
498	897	if (nr_matches > nr_regs) {
499	898	dev_err(ddata->dev, "overlapping registers: (%i/%i)",
500	899	nr_regs, nr_matches);
..	..	@@ -520,12 +919,21 @@
520	919	{
521	920	int size;
522	921
523		- size = max3(ddata->offsets[SYSC_REVISION],
524		- ddata->offsets[SYSC_SYSCONFIG],
525		- ddata->offsets[SYSC_SYSSTATUS]);
	922	+ if (ddata->offsets[SYSC_REVISION] < 0 &&
	923	+ ddata->offsets[SYSC_SYSCONFIG] < 0 &&
	924	+ ddata->offsets[SYSC_SYSSTATUS] < 0) {
	925	+ size = ddata->module_size;
	926	+ } else {
	927	+ size = max3(ddata->offsets[SYSC_REVISION],
	928	+ ddata->offsets[SYSC_SYSCONFIG],
	929	+ ddata->offsets[SYSC_SYSSTATUS]);
526	930
527		- if (size < 0 \|\| (size + sizeof(u32)) > ddata->module_size)
528		- return -EINVAL;
	931	+ if (size < SZ_1K)
	932	+ size = SZ_1K;
	933	+
	934	+ if ((size + sizeof(u32)) > ddata->module_size)
	935	+ size = ddata->module_size;
	936	+ }
529	937
530	938	ddata->module_va = devm_ioremap(ddata->dev,
531	939	ddata->module_pa,
..	..	@@ -548,9 +956,11 @@
548	956	if (error)
549	957	return error;
550	958
551		- error = sysc_check_children(ddata);
	959	+ error = sysc_defer_non_critical(ddata);
552	960	if (error)
553	961	return error;
	962	+
	963	+ sysc_check_children(ddata);
554	964
555	965	error = sysc_parse_registers(ddata);
556	966	if (error)
..	..	@@ -622,206 +1032,441 @@
622	1032	buf);
623	1033	}
624	1034
625		-static int __maybe_unused sysc_runtime_suspend(struct device *dev)
	1035	+/**
	1036	+ * sysc_write_sysconfig - handle sysconfig quirks for register write
	1037	+ * @ddata: device driver data
	1038	+ * @value: register value
	1039	+ */
	1040	+static void sysc_write_sysconfig(struct sysc *ddata, u32 value)
	1041	+{
	1042	+ if (ddata->module_unlock_quirk)
	1043	+ ddata->module_unlock_quirk(ddata);
	1044	+
	1045	+ sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], value);
	1046	+
	1047	+ if (ddata->module_lock_quirk)
	1048	+ ddata->module_lock_quirk(ddata);
	1049	+}
	1050	+
	1051	+#define SYSC_IDLE_MASK (SYSC_NR_IDLEMODES - 1)
	1052	+#define SYSC_CLOCACT_ICK 2
	1053	+
	1054	+/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
	1055	+static int sysc_enable_module(struct device *dev)
	1056	+{
	1057	+ struct sysc *ddata;
	1058	+ const struct sysc_regbits *regbits;
	1059	+ u32 reg, idlemodes, best_mode;
	1060	+ int error;
	1061	+
	1062	+ ddata = dev_get_drvdata(dev);
	1063	+
	1064	+ /*
	1065	+ * Some modules like DSS reset automatically on idle. Enable optional
	1066	+ * reset clocks and wait for OCP softreset to complete.
	1067	+ */
	1068	+ if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
	1069	+ error = sysc_enable_opt_clocks(ddata);
	1070	+ if (error) {
	1071	+ dev_err(ddata->dev,
	1072	+ "Optional clocks failed for enable: %i\n",
	1073	+ error);
	1074	+ return error;
	1075	+ }
	1076	+ }
	1077	+ /*
	1078	+ * Some modules like i2c and hdq1w have unusable reset status unless
	1079	+ * the module reset quirk is enabled. Skip status check on enable.
	1080	+ */
	1081	+ if (!(ddata->cfg.quirks & SYSC_MODULE_QUIRK_ENA_RESETDONE)) {
	1082	+ error = sysc_wait_softreset(ddata);
	1083	+ if (error)
	1084	+ dev_warn(ddata->dev, "OCP softreset timed out\n");
	1085	+ }
	1086	+ if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
	1087	+ sysc_disable_opt_clocks(ddata);
	1088	+
	1089	+ /*
	1090	+ * Some subsystem private interconnects, like DSS top level module,
	1091	+ * need only the automatic OCP softreset handling with no sysconfig
	1092	+ * register bits to configure.
	1093	+ */
	1094	+ if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
	1095	+ return 0;
	1096	+
	1097	+ regbits = ddata->cap->regbits;
	1098	+ reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
	1099	+
	1100	+ /*
	1101	+ * Set CLOCKACTIVITY, we only use it for ick. And we only configure it
	1102	+ * based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
	1103	+ * capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
	1104	+ */
	1105	+ if (regbits->clkact_shift >= 0 &&
	1106	+ (ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
	1107	+ reg \|= SYSC_CLOCACT_ICK << regbits->clkact_shift;
	1108	+
	1109	+ /* Set SIDLE mode */
	1110	+ idlemodes = ddata->cfg.sidlemodes;
	1111	+ if (!idlemodes \|\| regbits->sidle_shift < 0)
	1112	+ goto set_midle;
	1113	+
	1114	+ if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_SIDLE \|
	1115	+ SYSC_QUIRK_SWSUP_SIDLE_ACT)) {
	1116	+ best_mode = SYSC_IDLE_NO;
	1117	+
	1118	+ /* Clear WAKEUP */
	1119	+ if (regbits->enwkup_shift >= 0 &&
	1120	+ ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
	1121	+ reg &= ~BIT(regbits->enwkup_shift);
	1122	+ } else {
	1123	+ best_mode = fls(ddata->cfg.sidlemodes) - 1;
	1124	+ if (best_mode > SYSC_IDLE_MASK) {
	1125	+ dev_err(dev, "%s: invalid sidlemode\n", __func__);
	1126	+ return -EINVAL;
	1127	+ }
	1128	+
	1129	+ /* Set WAKEUP */
	1130	+ if (regbits->enwkup_shift >= 0 &&
	1131	+ ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
	1132	+ reg \|= BIT(regbits->enwkup_shift);
	1133	+ }
	1134	+
	1135	+ reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
	1136	+ reg \|= best_mode << regbits->sidle_shift;
	1137	+ sysc_write_sysconfig(ddata, reg);
	1138	+
	1139	+set_midle:
	1140	+ /* Set MIDLE mode */
	1141	+ idlemodes = ddata->cfg.midlemodes;
	1142	+ if (!idlemodes \|\| regbits->midle_shift < 0)
	1143	+ goto set_autoidle;
	1144	+
	1145	+ best_mode = fls(ddata->cfg.midlemodes) - 1;
	1146	+ if (best_mode > SYSC_IDLE_MASK) {
	1147	+ dev_err(dev, "%s: invalid midlemode\n", __func__);
	1148	+ return -EINVAL;
	1149	+ }
	1150	+
	1151	+ if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_MSTANDBY)
	1152	+ best_mode = SYSC_IDLE_NO;
	1153	+
	1154	+ reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
	1155	+ reg \|= best_mode << regbits->midle_shift;
	1156	+ sysc_write_sysconfig(ddata, reg);
	1157	+
	1158	+set_autoidle:
	1159	+ /* Autoidle bit must enabled separately if available */
	1160	+ if (regbits->autoidle_shift >= 0 &&
	1161	+ ddata->cfg.sysc_val & BIT(regbits->autoidle_shift)) {
	1162	+ reg \|= 1 << regbits->autoidle_shift;
	1163	+ sysc_write_sysconfig(ddata, reg);
	1164	+ }
	1165	+
	1166	+ /* Flush posted write */
	1167	+ sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
	1168	+
	1169	+ if (ddata->module_enable_quirk)
	1170	+ ddata->module_enable_quirk(ddata);
	1171	+
	1172	+ return 0;
	1173	+}
	1174	+
	1175	+static int sysc_best_idle_mode(u32 idlemodes, u32 *best_mode)
	1176	+{
	1177	+ if (idlemodes & BIT(SYSC_IDLE_SMART_WKUP))
	1178	+ *best_mode = SYSC_IDLE_SMART_WKUP;
	1179	+ else if (idlemodes & BIT(SYSC_IDLE_SMART))
	1180	+ *best_mode = SYSC_IDLE_SMART;
	1181	+ else if (idlemodes & BIT(SYSC_IDLE_FORCE))
	1182	+ *best_mode = SYSC_IDLE_FORCE;
	1183	+ else
	1184	+ return -EINVAL;
	1185	+
	1186	+ return 0;
	1187	+}
	1188	+
	1189	+/* Caller needs to manage sysc_clkdm_deny_idle() and sysc_clkdm_allow_idle() */
	1190	+static int sysc_disable_module(struct device *dev)
	1191	+{
	1192	+ struct sysc *ddata;
	1193	+ const struct sysc_regbits *regbits;
	1194	+ u32 reg, idlemodes, best_mode;
	1195	+ int ret;
	1196	+
	1197	+ ddata = dev_get_drvdata(dev);
	1198	+ if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
	1199	+ return 0;
	1200	+
	1201	+ if (ddata->module_disable_quirk)
	1202	+ ddata->module_disable_quirk(ddata);
	1203	+
	1204	+ regbits = ddata->cap->regbits;
	1205	+ reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
	1206	+
	1207	+ /* Set MIDLE mode */
	1208	+ idlemodes = ddata->cfg.midlemodes;
	1209	+ if (!idlemodes \|\| regbits->midle_shift < 0)
	1210	+ goto set_sidle;
	1211	+
	1212	+ ret = sysc_best_idle_mode(idlemodes, &best_mode);
	1213	+ if (ret) {
	1214	+ dev_err(dev, "%s: invalid midlemode\n", __func__);
	1215	+ return ret;
	1216	+ }
	1217	+
	1218	+ if (ddata->cfg.quirks & (SYSC_QUIRK_SWSUP_MSTANDBY) \|\|
	1219	+ ddata->cfg.quirks & (SYSC_QUIRK_FORCE_MSTANDBY))
	1220	+ best_mode = SYSC_IDLE_FORCE;
	1221	+
	1222	+ reg &= ~(SYSC_IDLE_MASK << regbits->midle_shift);
	1223	+ reg \|= best_mode << regbits->midle_shift;
	1224	+ sysc_write_sysconfig(ddata, reg);
	1225	+
	1226	+set_sidle:
	1227	+ /* Set SIDLE mode */
	1228	+ idlemodes = ddata->cfg.sidlemodes;
	1229	+ if (!idlemodes \|\| regbits->sidle_shift < 0)
	1230	+ return 0;
	1231	+
	1232	+ if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE) {
	1233	+ best_mode = SYSC_IDLE_FORCE;
	1234	+ } else {
	1235	+ ret = sysc_best_idle_mode(idlemodes, &best_mode);
	1236	+ if (ret) {
	1237	+ dev_err(dev, "%s: invalid sidlemode\n", __func__);
	1238	+ return ret;
	1239	+ }
	1240	+ }
	1241	+
	1242	+ if (ddata->cfg.quirks & SYSC_QUIRK_SWSUP_SIDLE_ACT) {
	1243	+ /* Set WAKEUP */
	1244	+ if (regbits->enwkup_shift >= 0 &&
	1245	+ ddata->cfg.sysc_val & BIT(regbits->enwkup_shift))
	1246	+ reg \|= BIT(regbits->enwkup_shift);
	1247	+ }
	1248	+
	1249	+ reg &= ~(SYSC_IDLE_MASK << regbits->sidle_shift);
	1250	+ reg \|= best_mode << regbits->sidle_shift;
	1251	+ if (regbits->autoidle_shift >= 0 &&
	1252	+ ddata->cfg.sysc_val & BIT(regbits->autoidle_shift))
	1253	+ reg \|= 1 << regbits->autoidle_shift;
	1254	+ sysc_write_sysconfig(ddata, reg);
	1255	+
	1256	+ /* Flush posted write */
	1257	+ sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
	1258	+
	1259	+ return 0;
	1260	+}
	1261	+
	1262	+static int __maybe_unused sysc_runtime_suspend_legacy(struct device *dev,
	1263	+ struct sysc *ddata)
626	1264	{
627	1265	struct ti_sysc_platform_data *pdata;
	1266	+ int error;
	1267	+
	1268	+ pdata = dev_get_platdata(ddata->dev);
	1269	+ if (!pdata)
	1270	+ return 0;
	1271	+
	1272	+ if (!pdata->idle_module)
	1273	+ return -ENODEV;
	1274	+
	1275	+ error = pdata->idle_module(dev, &ddata->cookie);
	1276	+ if (error)
	1277	+ dev_err(dev, "%s: could not idle: %i\n",
	1278	+ __func__, error);
	1279	+
	1280	+ reset_control_assert(ddata->rsts);
	1281	+
	1282	+ return 0;
	1283	+}
	1284	+
	1285	+static int __maybe_unused sysc_runtime_resume_legacy(struct device *dev,
	1286	+ struct sysc *ddata)
	1287	+{
	1288	+ struct ti_sysc_platform_data *pdata;
	1289	+ int error;
	1290	+
	1291	+ pdata = dev_get_platdata(ddata->dev);
	1292	+ if (!pdata)
	1293	+ return 0;
	1294	+
	1295	+ if (!pdata->enable_module)
	1296	+ return -ENODEV;
	1297	+
	1298	+ error = pdata->enable_module(dev, &ddata->cookie);
	1299	+ if (error)
	1300	+ dev_err(dev, "%s: could not enable: %i\n",
	1301	+ __func__, error);
	1302	+
	1303	+ reset_control_deassert(ddata->rsts);
	1304	+
	1305	+ return 0;
	1306	+}
	1307	+
	1308	+static int __maybe_unused sysc_runtime_suspend(struct device *dev)
	1309	+{
628	1310	struct sysc *ddata;
629		- int error = 0, i;
	1311	+ int error = 0;
630	1312
631	1313	ddata = dev_get_drvdata(dev);
632	1314
633	1315	if (!ddata->enabled)
634	1316	return 0;
635	1317
	1318	+ sysc_clkdm_deny_idle(ddata);
	1319	+
636	1320	if (ddata->legacy_mode) {
637		- pdata = dev_get_platdata(ddata->dev);
638		- if (!pdata)
639		- return 0;
640		-
641		- if (!pdata->idle_module)
642		- return -ENODEV;
643		-
644		- error = pdata->idle_module(dev, &ddata->cookie);
	1321	+ error = sysc_runtime_suspend_legacy(dev, ddata);
645	1322	if (error)
646		- dev_err(dev, "%s: could not idle: %i\n",
647		- __func__, error);
648		-
649		- goto idled;
	1323	+ goto err_allow_idle;
	1324	+ } else {
	1325	+ error = sysc_disable_module(dev);
	1326	+ if (error)
	1327	+ goto err_allow_idle;
650	1328	}
651	1329
652		- for (i = 0; i < ddata->nr_clocks; i++) {
653		- if (IS_ERR_OR_NULL(ddata->clocks[i]))
654		- continue;
	1330	+ sysc_disable_main_clocks(ddata);
655	1331
656		- if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata))
657		- break;
	1332	+ if (sysc_opt_clks_needed(ddata))
	1333	+ sysc_disable_opt_clocks(ddata);
658	1334
659		- clk_disable(ddata->clocks[i]);
660		- }
661		-
662		-idled:
663	1335	ddata->enabled = false;
	1336	+
	1337	+err_allow_idle:
	1338	+ reset_control_assert(ddata->rsts);
	1339	+
	1340	+ sysc_clkdm_allow_idle(ddata);
664	1341
665	1342	return error;
666	1343	}
667	1344
668	1345	static int __maybe_unused sysc_runtime_resume(struct device *dev)
669	1346	{
670		- struct ti_sysc_platform_data *pdata;
671	1347	struct sysc *ddata;
672		- int error = 0, i;
	1348	+ int error = 0;
673	1349
674	1350	ddata = dev_get_drvdata(dev);
675	1351
676	1352	if (ddata->enabled)
677	1353	return 0;
678	1354
	1355	+
	1356	+ sysc_clkdm_deny_idle(ddata);
	1357	+
	1358	+ if (sysc_opt_clks_needed(ddata)) {
	1359	+ error = sysc_enable_opt_clocks(ddata);
	1360	+ if (error)
	1361	+ goto err_allow_idle;
	1362	+ }
	1363	+
	1364	+ error = sysc_enable_main_clocks(ddata);
	1365	+ if (error)
	1366	+ goto err_opt_clocks;
	1367	+
	1368	+ reset_control_deassert(ddata->rsts);
	1369	+
679	1370	if (ddata->legacy_mode) {
680		- pdata = dev_get_platdata(ddata->dev);
681		- if (!pdata)
682		- return 0;
683		-
684		- if (!pdata->enable_module)
685		- return -ENODEV;
686		-
687		- error = pdata->enable_module(dev, &ddata->cookie);
	1371	+ error = sysc_runtime_resume_legacy(dev, ddata);
688	1372	if (error)
689		- dev_err(dev, "%s: could not enable: %i\n",
690		- __func__, error);
691		-
692		- goto awake;
	1373	+ goto err_main_clocks;
	1374	+ } else {
	1375	+ error = sysc_enable_module(dev);
	1376	+ if (error)
	1377	+ goto err_main_clocks;
693	1378	}
694	1379
695		- for (i = 0; i < ddata->nr_clocks; i++) {
696		- if (IS_ERR_OR_NULL(ddata->clocks[i]))
697		- continue;
698		-
699		- if (i >= SYSC_OPTFCK0 && !sysc_opt_clks_needed(ddata))
700		- break;
701		-
702		- error = clk_enable(ddata->clocks[i]);
703		- if (error)
704		- return error;
705		- }
706		-
707		-awake:
708	1380	ddata->enabled = true;
	1381	+
	1382	+ sysc_clkdm_allow_idle(ddata);
	1383	+
	1384	+ return 0;
	1385	+
	1386	+err_main_clocks:
	1387	+ sysc_disable_main_clocks(ddata);
	1388	+err_opt_clocks:
	1389	+ if (sysc_opt_clks_needed(ddata))
	1390	+ sysc_disable_opt_clocks(ddata);
	1391	+err_allow_idle:
	1392	+ sysc_clkdm_allow_idle(ddata);
709	1393
710	1394	return error;
711	1395	}
712	1396
713		-#ifdef CONFIG_PM_SLEEP
714		-static int sysc_suspend(struct device *dev)
	1397	+static int sysc_reinit_module(struct sysc *ddata, bool leave_enabled)
	1398	+{
	1399	+ struct device *dev = ddata->dev;
	1400	+ int error;
	1401	+
	1402	+ /* Disable target module if it is enabled */
	1403	+ if (ddata->enabled) {
	1404	+ error = sysc_runtime_suspend(dev);
	1405	+ if (error)
	1406	+ dev_warn(dev, "reinit suspend failed: %i\n", error);
	1407	+ }
	1408	+
	1409	+ /* Enable target module */
	1410	+ error = sysc_runtime_resume(dev);
	1411	+ if (error)
	1412	+ dev_warn(dev, "reinit resume failed: %i\n", error);
	1413	+
	1414	+ if (leave_enabled)
	1415	+ return error;
	1416	+
	1417	+ /* Disable target module if no leave_enabled was set */
	1418	+ error = sysc_runtime_suspend(dev);
	1419	+ if (error)
	1420	+ dev_warn(dev, "reinit suspend failed: %i\n", error);
	1421	+
	1422	+ return error;
	1423	+}
	1424	+
	1425	+static int __maybe_unused sysc_noirq_suspend(struct device *dev)
715	1426	{
716	1427	struct sysc *ddata;
717		- int error;
718	1428
719	1429	ddata = dev_get_drvdata(dev);
720	1430
721		- if (ddata->cfg.quirks & (SYSC_QUIRK_RESOURCE_PROVIDER \|
722		- SYSC_QUIRK_LEGACY_IDLE))
	1431	+ if (ddata->cfg.quirks &
	1432	+ (SYSC_QUIRK_LEGACY_IDLE \| SYSC_QUIRK_NO_IDLE))
723	1433	return 0;
724	1434
725	1435	if (!ddata->enabled)
726	1436	return 0;
727	1437
728		- dev_dbg(ddata->dev, "%s %s\n", __func__,
729		- ddata->name ? ddata->name : "");
730		-
731		- error = pm_runtime_put_sync_suspend(dev);
732		- if (error < 0) {
733		- dev_warn(ddata->dev, "%s not idle %i %s\n",
734		- __func__, error,
735		- ddata->name ? ddata->name : "");
736		-
737		- return 0;
738		- }
739		-
740		- ddata->needs_resume = true;
741		-
742		- return 0;
743		-}
744		-
745		-static int sysc_resume(struct device *dev)
746		-{
747		- struct sysc *ddata;
748		- int error;
749		-
750		- ddata = dev_get_drvdata(dev);
751		-
752		- if (ddata->cfg.quirks & (SYSC_QUIRK_RESOURCE_PROVIDER \|
753		- SYSC_QUIRK_LEGACY_IDLE))
754		- return 0;
755		-
756		- if (ddata->needs_resume) {
757		- dev_dbg(ddata->dev, "%s %s\n", __func__,
758		- ddata->name ? ddata->name : "");
759		-
760		- error = pm_runtime_get_sync(dev);
761		- if (error < 0) {
762		- dev_err(ddata->dev, "%s error %i %s\n",
763		- __func__, error,
764		- ddata->name ? ddata->name : "");
765		-
766		- return error;
767		- }
768		-
769		- ddata->needs_resume = false;
770		- }
771		-
772		- return 0;
773		-}
774		-
775		-static int sysc_noirq_suspend(struct device *dev)
776		-{
777		- struct sysc *ddata;
778		-
779		- ddata = dev_get_drvdata(dev);
780		-
781		- if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
782		- return 0;
783		-
784		- if (!(ddata->cfg.quirks & SYSC_QUIRK_RESOURCE_PROVIDER))
785		- return 0;
786		-
787		- if (!ddata->enabled)
788		- return 0;
789		-
790		- dev_dbg(ddata->dev, "%s %s\n", __func__,
791		- ddata->name ? ddata->name : "");
792		-
793		- ddata->needs_resume = true;
	1438	+ ddata->needs_resume = 1;
794	1439
795	1440	return sysc_runtime_suspend(dev);
796	1441	}
797	1442
798		-static int sysc_noirq_resume(struct device *dev)
	1443	+static int __maybe_unused sysc_noirq_resume(struct device *dev)
799	1444	{
800	1445	struct sysc *ddata;
	1446	+ int error = 0;
801	1447
802	1448	ddata = dev_get_drvdata(dev);
803	1449
804		- if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
	1450	+ if (ddata->cfg.quirks &
	1451	+ (SYSC_QUIRK_LEGACY_IDLE \| SYSC_QUIRK_NO_IDLE))
805	1452	return 0;
806	1453
807		- if (!(ddata->cfg.quirks & SYSC_QUIRK_RESOURCE_PROVIDER))
808		- return 0;
809		-
810		- if (ddata->needs_resume) {
811		- dev_dbg(ddata->dev, "%s %s\n", __func__,
812		- ddata->name ? ddata->name : "");
813		-
814		- ddata->needs_resume = false;
815		-
816		- return sysc_runtime_resume(dev);
	1454	+ if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_RESUME) {
	1455	+ error = sysc_reinit_module(ddata, ddata->needs_resume);
	1456	+ if (error)
	1457	+ dev_warn(dev, "noirq_resume failed: %i\n", error);
	1458	+ } else if (ddata->needs_resume) {
	1459	+ error = sysc_runtime_resume(dev);
	1460	+ if (error)
	1461	+ dev_warn(dev, "noirq_resume failed: %i\n", error);
817	1462	}
818	1463
819		- return 0;
	1464	+ ddata->needs_resume = 0;
	1465	+
	1466	+ return error;
820	1467	}
821		-#endif
822	1468
823	1469	static const struct dev_pm_ops sysc_pm_ops = {
824		- SET_SYSTEM_SLEEP_PM_OPS(sysc_suspend, sysc_resume)
825	1470	SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sysc_noirq_suspend, sysc_noirq_resume)
826	1471	SET_RUNTIME_PM_OPS(sysc_runtime_suspend,
827	1472	sysc_runtime_resume,
..	..	@@ -854,77 +1499,198 @@
854	1499	}
855	1500
856	1501	static const struct sysc_revision_quirk sysc_revision_quirks[] = {
857		- /* These need to use noirq_suspend */
858		- SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff,
859		- SYSC_QUIRK_RESOURCE_PROVIDER),
860		- SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xffffffff,
861		- SYSC_QUIRK_RESOURCE_PROVIDER),
862		- SYSC_QUIRK("mcspi", 0, 0, 0x10, -1, 0x40300a0b, 0xffffffff,
863		- SYSC_QUIRK_RESOURCE_PROVIDER),
864		- SYSC_QUIRK("prcm", 0, 0, -1, -1, 0x40000100, 0xffffffff,
865		- SYSC_QUIRK_RESOURCE_PROVIDER),
866		- SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xffffffff,
867		- SYSC_QUIRK_RESOURCE_PROVIDER),
868		- SYSC_QUIRK("padconf", 0, 0, 0x10, -1, 0x4fff0800, 0xffffffff,
869		- SYSC_QUIRK_RESOURCE_PROVIDER),
870		- SYSC_QUIRK("scm", 0, 0, 0x10, -1, 0x40000900, 0xffffffff,
871		- SYSC_QUIRK_RESOURCE_PROVIDER),
872		- SYSC_QUIRK("scrm", 0, 0, -1, -1, 0x00000010, 0xffffffff,
873		- SYSC_QUIRK_RESOURCE_PROVIDER),
874		- SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff,
875		- SYSC_QUIRK_RESOURCE_PROVIDER),
876		-
877	1502	/* These drivers need to be fixed to not use pm_runtime_irq_safe() */
878		- SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffffffff,
	1503	+ SYSC_QUIRK("gpio", 0, 0, 0x10, 0x114, 0x50600801, 0xffff00ff,
879	1504	SYSC_QUIRK_LEGACY_IDLE \| SYSC_QUIRK_OPT_CLKS_IN_RESET),
880		- SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
881		- SYSC_QUIRK_LEGACY_IDLE),
882		- SYSC_QUIRK("mmu", 0, 0, 0x10, 0x14, 0x00000030, 0xffffffff,
883		- SYSC_QUIRK_LEGACY_IDLE),
884	1505	SYSC_QUIRK("sham", 0, 0x100, 0x110, 0x114, 0x40000c03, 0xffffffff,
885	1506	SYSC_QUIRK_LEGACY_IDLE),
886		- SYSC_QUIRK("smartreflex", 0, -1, 0x24, -1, 0x00000000, 0xffffffff,
	1507	+ SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x24, -ENODEV, 0x00000000, 0xffffffff,
887	1508	SYSC_QUIRK_LEGACY_IDLE),
888		- SYSC_QUIRK("smartreflex", 0, -1, 0x38, -1, 0x00000000, 0xffffffff,
	1509	+ SYSC_QUIRK("smartreflex", 0, -ENODEV, 0x38, -ENODEV, 0x00000000, 0xffffffff,
889	1510	SYSC_QUIRK_LEGACY_IDLE),
890		- SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff,
891		- 0),
892		- /* Some timers on omap4 and later */
893		- SYSC_QUIRK("timer", 0, 0, 0x10, -1, 0x4fff1301, 0xffffffff,
894		- 0),
	1511	+ SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000046, 0xffffffff,
	1512	+ SYSC_QUIRK_SWSUP_SIDLE_ACT \| SYSC_QUIRK_LEGACY_IDLE),
895	1513	SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x00000052, 0xffffffff,
896		- SYSC_QUIRK_LEGACY_IDLE),
	1514	+ SYSC_QUIRK_SWSUP_SIDLE_ACT \| SYSC_QUIRK_LEGACY_IDLE),
897	1515	/* Uarts on omap4 and later */
898		- SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffffffff,
899		- SYSC_QUIRK_LEGACY_IDLE),
	1516	+ SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x50411e03, 0xffff00ff,
	1517	+ SYSC_QUIRK_SWSUP_SIDLE_ACT \| SYSC_QUIRK_LEGACY_IDLE),
	1518	+ SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff,
	1519	+ SYSC_QUIRK_SWSUP_SIDLE_ACT \| SYSC_QUIRK_LEGACY_IDLE),
	1520	+ SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff,
	1521	+ SYSC_QUIRK_SWSUP_SIDLE_ACT \| SYSC_QUIRK_LEGACY_IDLE),
900	1522
901		- /* These devices don't yet suspend properly without legacy setting */
902		- SYSC_QUIRK("sdio", 0, 0, 0x10, -1, 0x40202301, 0xffffffff,
903		- SYSC_QUIRK_LEGACY_IDLE),
904		- SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xffffffff,
905		- SYSC_QUIRK_LEGACY_IDLE),
906		- SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0d00, 0xffffffff,
907		- SYSC_QUIRK_LEGACY_IDLE),
	1523	+ /* Quirks that need to be set based on the module address */
	1524	+ SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff,
	1525	+ SYSC_QUIRK_EXT_OPT_CLOCK \| SYSC_QUIRK_NO_RESET_ON_INIT \|
	1526	+ SYSC_QUIRK_SWSUP_SIDLE),
	1527	+
	1528	+ /* Quirks that need to be set based on detected module */
	1529	+ SYSC_QUIRK("aess", 0, 0, 0x10, -ENODEV, 0x40000000, 0xffffffff,
	1530	+ SYSC_MODULE_QUIRK_AESS),
	1531	+ /* Errata i893 handling for dra7 dcan1 and 2 */
	1532	+ SYSC_QUIRK("dcan", 0x4ae3c000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
	1533	+ SYSC_QUIRK_CLKDM_NOAUTO),
	1534	+ SYSC_QUIRK("dcan", 0x48480000, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff,
	1535	+ SYSC_QUIRK_CLKDM_NOAUTO),
	1536	+ SYSC_QUIRK("dss", 0x4832a000, 0, 0x10, 0x14, 0x00000020, 0xffffffff,
	1537	+ SYSC_QUIRK_OPT_CLKS_IN_RESET \| SYSC_MODULE_QUIRK_DSS_RESET),
	1538	+ SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000040, 0xffffffff,
	1539	+ SYSC_QUIRK_OPT_CLKS_IN_RESET \| SYSC_MODULE_QUIRK_DSS_RESET),
	1540	+ SYSC_QUIRK("dss", 0x58000000, 0, -ENODEV, 0x14, 0x00000061, 0xffffffff,
	1541	+ SYSC_QUIRK_OPT_CLKS_IN_RESET \| SYSC_MODULE_QUIRK_DSS_RESET),
	1542	+ SYSC_QUIRK("dwc3", 0x48880000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
	1543	+ SYSC_QUIRK_CLKDM_NOAUTO),
	1544	+ SYSC_QUIRK("dwc3", 0x488c0000, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff,
	1545	+ SYSC_QUIRK_CLKDM_NOAUTO),
	1546	+ SYSC_QUIRK("gpmc", 0, 0, 0x10, 0x14, 0x00000060, 0xffffffff,
	1547	+ SYSC_QUIRK_GPMC_DEBUG),
	1548	+ SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50030200, 0xffffffff,
	1549	+ SYSC_QUIRK_OPT_CLKS_NEEDED),
	1550	+ SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff,
	1551	+ SYSC_MODULE_QUIRK_HDQ1W \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
	1552	+ SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x0000000a, 0xffffffff,
	1553	+ SYSC_MODULE_QUIRK_HDQ1W \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
	1554	+ SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000036, 0x000000ff,
	1555	+ SYSC_MODULE_QUIRK_I2C \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
	1556	+ SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x0000003c, 0x000000ff,
	1557	+ SYSC_MODULE_QUIRK_I2C \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
	1558	+ SYSC_QUIRK("i2c", 0, 0, 0x20, 0x10, 0x00000040, 0x000000ff,
	1559	+ SYSC_MODULE_QUIRK_I2C \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
	1560	+ SYSC_QUIRK("i2c", 0, 0, 0x10, 0x90, 0x5040000a, 0xfffff0f0,
	1561	+ SYSC_MODULE_QUIRK_I2C \| SYSC_MODULE_QUIRK_ENA_RESETDONE),
	1562	+ SYSC_QUIRK("gpu", 0x50000000, 0x14, -ENODEV, -ENODEV, 0x00010201, 0xffffffff, 0),
	1563	+ SYSC_QUIRK("gpu", 0x50000000, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff,
	1564	+ SYSC_MODULE_QUIRK_SGX),
	1565	+ SYSC_QUIRK("lcdc", 0, 0, 0x54, -ENODEV, 0x4f201000, 0xffffffff,
	1566	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
	1567	+ SYSC_QUIRK("rtc", 0, 0x74, 0x78, -ENODEV, 0x4eb01908, 0xffff00f0,
	1568	+ SYSC_MODULE_QUIRK_RTC_UNLOCK),
	1569	+ SYSC_QUIRK("tptc", 0, 0, 0x10, -ENODEV, 0x40006c00, 0xffffefff,
	1570	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
	1571	+ SYSC_QUIRK("tptc", 0, 0, -ENODEV, -ENODEV, 0x40007c00, 0xffffffff,
	1572	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
	1573	+ SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff,
	1574	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
	1575	+ SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, -ENODEV, 0x50700101, 0xffffffff,
	1576	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
	1577	+ SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
	1578	+ 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY),
	1579	+ SYSC_QUIRK("usb_otg_hs", 0, 0, 0x10, -ENODEV, 0x4ea2080d, 0xffffffff,
	1580	+ SYSC_QUIRK_SWSUP_SIDLE \| SYSC_QUIRK_SWSUP_MSTANDBY \|
	1581	+ SYSC_QUIRK_REINIT_ON_CTX_LOST),
	1582	+ SYSC_QUIRK("wdt", 0, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
	1583	+ SYSC_MODULE_QUIRK_WDT),
	1584	+ /* PRUSS on am3, am4 and am5 */
	1585	+ SYSC_QUIRK("pruss", 0, 0x26000, 0x26004, -ENODEV, 0x47000000, 0xff000000,
	1586	+ SYSC_MODULE_QUIRK_PRUSS),
	1587	+ /* Watchdog on am3 and am4 */
	1588	+ SYSC_QUIRK("wdt", 0x44e35000, 0, 0x10, 0x14, 0x502a0500, 0xfffff0f0,
	1589	+ SYSC_MODULE_QUIRK_WDT \| SYSC_QUIRK_SWSUP_SIDLE),
908	1590
909	1591	#ifdef DEBUG
910		- SYSC_QUIRK("aess", 0, 0, 0x10, -1, 0x40000000, 0xffffffff, 0),
911		- SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -1, 0, 0, 0),
912		- SYSC_QUIRK("hdq1w", 0, 0, 0x14, 0x18, 0x00000006, 0xffffffff, 0),
	1592	+ SYSC_QUIRK("adc", 0, 0, 0x10, -ENODEV, 0x47300001, 0xffffffff, 0),
	1593	+ SYSC_QUIRK("atl", 0, 0, -ENODEV, -ENODEV, 0x0a070100, 0xffffffff, 0),
	1594	+ SYSC_QUIRK("cm", 0, 0, -ENODEV, -ENODEV, 0x40000301, 0xffffffff, 0),
	1595	+ SYSC_QUIRK("control", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
	1596	+ SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
	1597	+ 0xffff00f0, 0),
	1598	+ SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0xa3170504, 0xffffffff, 0),
	1599	+ SYSC_QUIRK("dcan", 0, 0x20, -ENODEV, -ENODEV, 0x4edb1902, 0xffffffff, 0),
	1600	+ SYSC_QUIRK("dispc", 0x4832a400, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
	1601	+ SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
	1602	+ SYSC_QUIRK("dispc", 0x58001000, 0, 0x10, 0x14, 0x00000051, 0xffffffff, 0),
	1603	+ SYSC_QUIRK("dmic", 0, 0, 0x10, -ENODEV, 0x50010000, 0xffffffff, 0),
	1604	+ SYSC_QUIRK("dsi", 0x58004000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
	1605	+ SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000030, 0xffffffff, 0),
	1606	+ SYSC_QUIRK("dsi", 0x58005000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
	1607	+ SYSC_QUIRK("dsi", 0x58009000, 0, 0x10, 0x14, 0x00000040, 0xffffffff, 0),
	1608	+ SYSC_QUIRK("dwc3", 0, 0, 0x10, -ENODEV, 0x500a0200, 0xffffffff, 0),
	1609	+ SYSC_QUIRK("d2d", 0x4a0b6000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
	1610	+ SYSC_QUIRK("d2d", 0x4a0cd000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
	1611	+ SYSC_QUIRK("epwmss", 0, 0, 0x4, -ENODEV, 0x47400001, 0xffffffff, 0),
	1612	+ SYSC_QUIRK("gpu", 0, 0x1fc00, 0x1fc10, -ENODEV, 0, 0, 0),
	1613	+ SYSC_QUIRK("gpu", 0, 0xfe00, 0xfe10, -ENODEV, 0x40000000 , 0xffffffff, 0),
	1614	+ SYSC_QUIRK("hdmi", 0, 0, 0x10, -ENODEV, 0x50031d00, 0xffffffff, 0),
913	1615	SYSC_QUIRK("hsi", 0, 0, 0x10, 0x14, 0x50043101, 0xffffffff, 0),
914		- SYSC_QUIRK("iss", 0, 0, 0x10, -1, 0x40000101, 0xffffffff, 0),
915		- SYSC_QUIRK("mcasp", 0, 0, 0x4, -1, 0x44306302, 0xffffffff, 0),
916		- SYSC_QUIRK("mcbsp", 0, -1, 0x8c, -1, 0, 0, 0),
917		- SYSC_QUIRK("mailbox", 0, 0, 0x10, -1, 0x00000400, 0xffffffff, 0),
918		- SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40000902, 0xffffffff, 0),
919		- SYSC_QUIRK("slimbus", 0, 0, 0x10, -1, 0x40002903, 0xffffffff, 0),
920		- SYSC_QUIRK("spinlock", 0, 0, 0x10, -1, 0x50020000, 0xffffffff, 0),
	1616	+ SYSC_QUIRK("iss", 0, 0, 0x10, -ENODEV, 0x40000101, 0xffffffff, 0),
	1617	+ SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44306302, 0xffffffff, 0),
	1618	+ SYSC_QUIRK("mcasp", 0, 0, 0x4, -ENODEV, 0x44307b02, 0xffffffff, 0),
	1619	+ SYSC_QUIRK("mcbsp", 0, -ENODEV, 0x8c, -ENODEV, 0, 0, 0),
	1620	+ SYSC_QUIRK("mcspi", 0, 0, 0x10, -ENODEV, 0x40300a0b, 0xffff00ff, 0),
	1621	+ SYSC_QUIRK("mcspi", 0, 0, 0x110, 0x114, 0x40300a0b, 0xffffffff, 0),
	1622	+ SYSC_QUIRK("mailbox", 0, 0, 0x10, -ENODEV, 0x00000400, 0xffffffff, 0),
	1623	+ SYSC_QUIRK("m3", 0, 0, -ENODEV, -ENODEV, 0x5f580105, 0x0fff0f00, 0),
	1624	+ SYSC_QUIRK("ocp2scp", 0, 0, 0x10, 0x14, 0x50060005, 0xfffffff0, 0),
	1625	+ SYSC_QUIRK("ocp2scp", 0, 0, -ENODEV, -ENODEV, 0x50060007, 0xffffffff, 0),
	1626	+ SYSC_QUIRK("padconf", 0, 0, 0x10, -ENODEV, 0x4fff0800, 0xffffffff, 0),
	1627	+ SYSC_QUIRK("padconf", 0, 0, -ENODEV, -ENODEV, 0x40001100, 0xffffffff, 0),
	1628	+ SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000100, 0xffffffff, 0),
	1629	+ SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x00004102, 0xffffffff, 0),
	1630	+ SYSC_QUIRK("prcm", 0, 0, -ENODEV, -ENODEV, 0x40000400, 0xffffffff, 0),
	1631	+ SYSC_QUIRK("rfbi", 0x4832a800, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
	1632	+ SYSC_QUIRK("rfbi", 0x58002000, 0, 0x10, 0x14, 0x00000010, 0xffffffff, 0),
	1633	+ SYSC_QUIRK("scm", 0, 0, 0x10, -ENODEV, 0x40000900, 0xffffffff, 0),
	1634	+ SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4e8b0100, 0xffffffff, 0),
	1635	+ SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x4f000100, 0xffffffff, 0),
	1636	+ SYSC_QUIRK("scm", 0, 0, -ENODEV, -ENODEV, 0x40000900, 0xffffffff, 0),
	1637	+ SYSC_QUIRK("scrm", 0, 0, -ENODEV, -ENODEV, 0x00000010, 0xffffffff, 0),
	1638	+ SYSC_QUIRK("sdio", 0, 0, 0x10, -ENODEV, 0x40202301, 0xffff0ff0, 0),
	1639	+ SYSC_QUIRK("sdio", 0, 0x2fc, 0x110, 0x114, 0x31010000, 0xffffffff, 0),
	1640	+ SYSC_QUIRK("sdma", 0, 0, 0x2c, 0x28, 0x00010900, 0xffffffff, 0),
	1641	+ SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40000902, 0xffffffff, 0),
	1642	+ SYSC_QUIRK("slimbus", 0, 0, 0x10, -ENODEV, 0x40002903, 0xffffffff, 0),
	1643	+ SYSC_QUIRK("spinlock", 0, 0, 0x10, -ENODEV, 0x50020000, 0xffffffff, 0),
	1644	+ SYSC_QUIRK("rng", 0, 0x1fe0, 0x1fe4, -ENODEV, 0x00000020, 0xffffffff, 0),
	1645	+ SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000013, 0xffffffff, 0),
	1646	+ SYSC_QUIRK("timer", 0, 0, 0x10, 0x14, 0x00000015, 0xffffffff, 0),
	1647	+ /* Some timers on omap4 and later */
	1648	+ SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x50002100, 0xffffffff, 0),
	1649	+ SYSC_QUIRK("timer", 0, 0, 0x10, -ENODEV, 0x4fff1301, 0xffff00ff, 0),
	1650	+ SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000040, 0xffffffff, 0),
	1651	+ SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000011, 0xffffffff, 0),
	1652	+ SYSC_QUIRK("timer32k", 0, 0, 0x4, -ENODEV, 0x00000060, 0xffffffff, 0),
	1653	+ SYSC_QUIRK("tpcc", 0, 0, -ENODEV, -ENODEV, 0x40014c00, 0xffffffff, 0),
921	1654	SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000004, 0xffffffff, 0),
922		- SYSC_QUIRK("usb_host_hs", 0, 0, 0x10, 0x14, 0x50700100, 0xffffffff, 0),
923		- SYSC_QUIRK("usb_otg_hs", 0, 0x400, 0x404, 0x408, 0x00000050,
924		- 0xffffffff, 0),
	1655	+ SYSC_QUIRK("usbhstll", 0, 0, 0x10, 0x14, 0x00000008, 0xffffffff, 0),
	1656	+ SYSC_QUIRK("venc", 0x58003000, 0, -ENODEV, -ENODEV, 0x00000002, 0xffffffff, 0),
	1657	+ SYSC_QUIRK("vfpe", 0, 0, 0x104, -ENODEV, 0x4d001200, 0xffffffff, 0),
925	1658	#endif
926	1659	};
927	1660
	1661	+/*
	1662	+ * Early quirks based on module base and register offsets only that are
	1663	+ * needed before the module revision can be read
	1664	+ */
	1665	+static void sysc_init_early_quirks(struct sysc *ddata)
	1666	+{
	1667	+ const struct sysc_revision_quirk *q;
	1668	+ int i;
	1669	+
	1670	+ for (i = 0; i < ARRAY_SIZE(sysc_revision_quirks); i++) {
	1671	+ q = &sysc_revision_quirks[i];
	1672	+
	1673	+ if (!q->base)
	1674	+ continue;
	1675	+
	1676	+ if (q->base != ddata->module_pa)
	1677	+ continue;
	1678	+
	1679	+ if (q->rev_offset != ddata->offsets[SYSC_REVISION])
	1680	+ continue;
	1681	+
	1682	+ if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
	1683	+ continue;
	1684	+
	1685	+ if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
	1686	+ continue;
	1687	+
	1688	+ ddata->name = q->name;
	1689	+ ddata->cfg.quirks \|= q->quirks;
	1690	+ }
	1691	+}
	1692	+
	1693	+/* Quirks that also consider the revision register value */
928	1694	static void sysc_init_revision_quirks(struct sysc *ddata)
929	1695	{
930	1696	const struct sysc_revision_quirk *q;
..	..	@@ -936,16 +1702,13 @@
936	1702	if (q->base && q->base != ddata->module_pa)
937	1703	continue;
938	1704
939		- if (q->rev_offset >= 0 &&
940		- q->rev_offset != ddata->offsets[SYSC_REVISION])
	1705	+ if (q->rev_offset != ddata->offsets[SYSC_REVISION])
941	1706	continue;
942	1707
943		- if (q->sysc_offset >= 0 &&
944		- q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
	1708	+ if (q->sysc_offset != ddata->offsets[SYSC_SYSCONFIG])
945	1709	continue;
946	1710
947		- if (q->syss_offset >= 0 &&
948		- q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
	1711	+ if (q->syss_offset != ddata->offsets[SYSC_SYSSTATUS])
949	1712	continue;
950	1713
951	1714	if (q->revision == ddata->revision \|\|
..	..	@@ -957,68 +1720,471 @@
957	1720	}
958	1721	}
959	1722
	1723	+/*
	1724	+ * DSS needs dispc outputs disabled to reset modules. Returns mask of
	1725	+ * enabled DSS interrupts. Eventually we may be able to do this on
	1726	+ * dispc init rather than top-level DSS init.
	1727	+ */
	1728	+static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
	1729	+ bool disable)
	1730	+{
	1731	+ bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
	1732	+ const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
	1733	+ int manager_count;
	1734	+ bool framedonetv_irq = true;
	1735	+ u32 val, irq_mask = 0;
	1736	+
	1737	+ switch (sysc_soc->soc) {
	1738	+ case SOC_2420 ... SOC_3630:
	1739	+ manager_count = 2;
	1740	+ framedonetv_irq = false;
	1741	+ break;
	1742	+ case SOC_4430 ... SOC_4470:
	1743	+ manager_count = 3;
	1744	+ break;
	1745	+ case SOC_5430:
	1746	+ case SOC_DRA7:
	1747	+ manager_count = 4;
	1748	+ break;
	1749	+ case SOC_AM4:
	1750	+ manager_count = 1;
	1751	+ framedonetv_irq = false;
	1752	+ break;
	1753	+ case SOC_UNKNOWN:
	1754	+ default:
	1755	+ return 0;
	1756	+ };
	1757	+
	1758	+ /* Remap the whole module range to be able to reset dispc outputs */
	1759	+ devm_iounmap(ddata->dev, ddata->module_va);
	1760	+ ddata->module_va = devm_ioremap(ddata->dev,
	1761	+ ddata->module_pa,
	1762	+ ddata->module_size);
	1763	+ if (!ddata->module_va)
	1764	+ return -EIO;
	1765	+
	1766	+ /* DISP_CONTROL, shut down lcd and digit on disable if enabled */
	1767	+ val = sysc_read(ddata, dispc_offset + 0x40);
	1768	+ lcd_en = val & lcd_en_mask;
	1769	+ digit_en = val & digit_en_mask;
	1770	+ if (lcd_en)
	1771	+ irq_mask \|= BIT(0); /* FRAMEDONE */
	1772	+ if (digit_en) {
	1773	+ if (framedonetv_irq)
	1774	+ irq_mask \|= BIT(24); /* FRAMEDONETV */
	1775	+ else
	1776	+ irq_mask \|= BIT(2) \| BIT(3); /* EVSYNC bits */
	1777	+ }
	1778	+ if (disable && (lcd_en \|\| digit_en))
	1779	+ sysc_write(ddata, dispc_offset + 0x40,
	1780	+ val & ~(lcd_en_mask \| digit_en_mask));
	1781	+
	1782	+ if (manager_count <= 2)
	1783	+ return irq_mask;
	1784	+
	1785	+ /* DISPC_CONTROL2 */
	1786	+ val = sysc_read(ddata, dispc_offset + 0x238);
	1787	+ lcd2_en = val & lcd_en_mask;
	1788	+ if (lcd2_en)
	1789	+ irq_mask \|= BIT(22); /* FRAMEDONE2 */
	1790	+ if (disable && lcd2_en)
	1791	+ sysc_write(ddata, dispc_offset + 0x238,
	1792	+ val & ~lcd_en_mask);
	1793	+
	1794	+ if (manager_count <= 3)
	1795	+ return irq_mask;
	1796	+
	1797	+ /* DISPC_CONTROL3 */
	1798	+ val = sysc_read(ddata, dispc_offset + 0x848);
	1799	+ lcd3_en = val & lcd_en_mask;
	1800	+ if (lcd3_en)
	1801	+ irq_mask \|= BIT(30); /* FRAMEDONE3 */
	1802	+ if (disable && lcd3_en)
	1803	+ sysc_write(ddata, dispc_offset + 0x848,
	1804	+ val & ~lcd_en_mask);
	1805	+
	1806	+ return irq_mask;
	1807	+}
	1808	+
	1809	+/* DSS needs child outputs disabled and SDI registers cleared for reset */
	1810	+static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
	1811	+{
	1812	+ const int dispc_offset = 0x1000;
	1813	+ int error;
	1814	+ u32 irq_mask, val;
	1815	+
	1816	+ /* Get enabled outputs */
	1817	+ irq_mask = sysc_quirk_dispc(ddata, dispc_offset, false);
	1818	+ if (!irq_mask)
	1819	+ return;
	1820	+
	1821	+ /* Clear IRQSTATUS */
	1822	+ sysc_write(ddata, dispc_offset + 0x18, irq_mask);
	1823	+
	1824	+ /* Disable outputs */
	1825	+ val = sysc_quirk_dispc(ddata, dispc_offset, true);
	1826	+
	1827	+ /* Poll IRQSTATUS */
	1828	+ error = readl_poll_timeout(ddata->module_va + dispc_offset + 0x18,
	1829	+ val, val != irq_mask, 100, 50);
	1830	+ if (error)
	1831	+ dev_warn(ddata->dev, "%s: timed out %08x !+ %08x\n",
	1832	+ __func__, val, irq_mask);
	1833	+
	1834	+ if (sysc_soc->soc == SOC_3430 \|\| sysc_soc->soc == SOC_AM35) {
	1835	+ /* Clear DSS_SDI_CONTROL */
	1836	+ sysc_write(ddata, 0x44, 0);
	1837	+
	1838	+ /* Clear DSS_PLL_CONTROL */
	1839	+ sysc_write(ddata, 0x48, 0);
	1840	+ }
	1841	+
	1842	+ /* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
	1843	+ sysc_write(ddata, 0x40, 0);
	1844	+}
	1845	+
	1846	+/* 1-wire needs module's internal clocks enabled for reset */
	1847	+static void sysc_pre_reset_quirk_hdq1w(struct sysc *ddata)
	1848	+{
	1849	+ int offset = 0x0c; /* HDQ_CTRL_STATUS */
	1850	+ u16 val;
	1851	+
	1852	+ val = sysc_read(ddata, offset);
	1853	+ val \|= BIT(5);
	1854	+ sysc_write(ddata, offset, val);
	1855	+}
	1856	+
	1857	+/* AESS (Audio Engine SubSystem) needs autogating set after enable */
	1858	+static void sysc_module_enable_quirk_aess(struct sysc *ddata)
	1859	+{
	1860	+ int offset = 0x7c; /* AESS_AUTO_GATING_ENABLE */
	1861	+
	1862	+ sysc_write(ddata, offset, 1);
	1863	+}
	1864	+
	1865	+/* I2C needs to be disabled for reset */
	1866	+static void sysc_clk_quirk_i2c(struct sysc *ddata, bool enable)
	1867	+{
	1868	+ int offset;
	1869	+ u16 val;
	1870	+
	1871	+ /* I2C_CON, omap2/3 is different from omap4 and later */
	1872	+ if ((ddata->revision & 0xffffff00) == 0x001f0000)
	1873	+ offset = 0x24;
	1874	+ else
	1875	+ offset = 0xa4;
	1876	+
	1877	+ /* I2C_EN */
	1878	+ val = sysc_read(ddata, offset);
	1879	+ if (enable)
	1880	+ val \|= BIT(15);
	1881	+ else
	1882	+ val &= ~BIT(15);
	1883	+ sysc_write(ddata, offset, val);
	1884	+}
	1885	+
	1886	+static void sysc_pre_reset_quirk_i2c(struct sysc *ddata)
	1887	+{
	1888	+ sysc_clk_quirk_i2c(ddata, false);
	1889	+}
	1890	+
	1891	+static void sysc_post_reset_quirk_i2c(struct sysc *ddata)
	1892	+{
	1893	+ sysc_clk_quirk_i2c(ddata, true);
	1894	+}
	1895	+
	1896	+/* RTC on am3 and 4 needs to be unlocked and locked for sysconfig */
	1897	+static void sysc_quirk_rtc(struct sysc *ddata, bool lock)
	1898	+{
	1899	+ u32 val, kick0_val = 0, kick1_val = 0;
	1900	+ unsigned long flags;
	1901	+ int error;
	1902	+
	1903	+ if (!lock) {
	1904	+ kick0_val = 0x83e70b13;
	1905	+ kick1_val = 0x95a4f1e0;
	1906	+ }
	1907	+
	1908	+ local_irq_save(flags);
	1909	+ /* RTC_STATUS BUSY bit may stay active for 1/32768 seconds (~30 usec) */
	1910	+ error = readl_poll_timeout_atomic(ddata->module_va + 0x44, val,
	1911	+ !(val & BIT(0)), 100, 50);
	1912	+ if (error)
	1913	+ dev_warn(ddata->dev, "rtc busy timeout\n");
	1914	+ /* Now we have ~15 microseconds to read/write various registers */
	1915	+ sysc_write(ddata, 0x6c, kick0_val);
	1916	+ sysc_write(ddata, 0x70, kick1_val);
	1917	+ local_irq_restore(flags);
	1918	+}
	1919	+
	1920	+static void sysc_module_unlock_quirk_rtc(struct sysc *ddata)
	1921	+{
	1922	+ sysc_quirk_rtc(ddata, false);
	1923	+}
	1924	+
	1925	+static void sysc_module_lock_quirk_rtc(struct sysc *ddata)
	1926	+{
	1927	+ sysc_quirk_rtc(ddata, true);
	1928	+}
	1929	+
	1930	+/* 36xx SGX needs a quirk for to bypass OCP IPG interrupt logic */
	1931	+static void sysc_module_enable_quirk_sgx(struct sysc *ddata)
	1932	+{
	1933	+ int offset = 0xff08; /* OCP_DEBUG_CONFIG */
	1934	+ u32 val = BIT(31); /* THALIA_INT_BYPASS */
	1935	+
	1936	+ sysc_write(ddata, offset, val);
	1937	+}
	1938	+
	1939	+/* Watchdog timer needs a disable sequence after reset */
	1940	+static void sysc_reset_done_quirk_wdt(struct sysc *ddata)
	1941	+{
	1942	+ int wps, spr, error;
	1943	+ u32 val;
	1944	+
	1945	+ wps = 0x34;
	1946	+ spr = 0x48;
	1947	+
	1948	+ sysc_write(ddata, spr, 0xaaaa);
	1949	+ error = readl_poll_timeout(ddata->module_va + wps, val,
	1950	+ !(val & 0x10), 100,
	1951	+ MAX_MODULE_SOFTRESET_WAIT);
	1952	+ if (error)
	1953	+ dev_warn(ddata->dev, "wdt disable step1 failed\n");
	1954	+
	1955	+ sysc_write(ddata, spr, 0x5555);
	1956	+ error = readl_poll_timeout(ddata->module_va + wps, val,
	1957	+ !(val & 0x10), 100,
	1958	+ MAX_MODULE_SOFTRESET_WAIT);
	1959	+ if (error)
	1960	+ dev_warn(ddata->dev, "wdt disable step2 failed\n");
	1961	+}
	1962	+
	1963	+/* PRUSS needs to set MSTANDBY_INIT inorder to idle properly */
	1964	+static void sysc_module_disable_quirk_pruss(struct sysc *ddata)
	1965	+{
	1966	+ u32 reg;
	1967	+
	1968	+ reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
	1969	+ reg \|= SYSC_PRUSS_STANDBY_INIT;
	1970	+ sysc_write(ddata, ddata->offsets[SYSC_SYSCONFIG], reg);
	1971	+}
	1972	+
	1973	+static void sysc_init_module_quirks(struct sysc *ddata)
	1974	+{
	1975	+ if (ddata->legacy_mode \|\| !ddata->name)
	1976	+ return;
	1977	+
	1978	+ if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_HDQ1W) {
	1979	+ ddata->pre_reset_quirk = sysc_pre_reset_quirk_hdq1w;
	1980	+
	1981	+ return;
	1982	+ }
	1983	+
	1984	+#ifdef CONFIG_OMAP_GPMC_DEBUG
	1985	+ if (ddata->cfg.quirks & SYSC_QUIRK_GPMC_DEBUG) {
	1986	+ ddata->cfg.quirks \|= SYSC_QUIRK_NO_RESET_ON_INIT;
	1987	+
	1988	+ return;
	1989	+ }
	1990	+#endif
	1991	+
	1992	+ if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_I2C) {
	1993	+ ddata->pre_reset_quirk = sysc_pre_reset_quirk_i2c;
	1994	+ ddata->post_reset_quirk = sysc_post_reset_quirk_i2c;
	1995	+
	1996	+ return;
	1997	+ }
	1998	+
	1999	+ if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_AESS)
	2000	+ ddata->module_enable_quirk = sysc_module_enable_quirk_aess;
	2001	+
	2002	+ if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_DSS_RESET)
	2003	+ ddata->pre_reset_quirk = sysc_pre_reset_quirk_dss;
	2004	+
	2005	+ if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_RTC_UNLOCK) {
	2006	+ ddata->module_unlock_quirk = sysc_module_unlock_quirk_rtc;
	2007	+ ddata->module_lock_quirk = sysc_module_lock_quirk_rtc;
	2008	+
	2009	+ return;
	2010	+ }
	2011	+
	2012	+ if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_SGX)
	2013	+ ddata->module_enable_quirk = sysc_module_enable_quirk_sgx;
	2014	+
	2015	+ if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_WDT) {
	2016	+ ddata->reset_done_quirk = sysc_reset_done_quirk_wdt;
	2017	+ ddata->module_disable_quirk = sysc_reset_done_quirk_wdt;
	2018	+ }
	2019	+
	2020	+ if (ddata->cfg.quirks & SYSC_MODULE_QUIRK_PRUSS)
	2021	+ ddata->module_disable_quirk = sysc_module_disable_quirk_pruss;
	2022	+}
	2023	+
	2024	+static int sysc_clockdomain_init(struct sysc *ddata)
	2025	+{
	2026	+ struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
	2027	+ struct clk fck = NULL, ick = NULL;
	2028	+ int error;
	2029	+
	2030	+ if (!pdata \|\| !pdata->init_clockdomain)
	2031	+ return 0;
	2032	+
	2033	+ switch (ddata->nr_clocks) {
	2034	+ case 2:
	2035	+ ick = ddata->clocks[SYSC_ICK];
	2036	+ fallthrough;
	2037	+ case 1:
	2038	+ fck = ddata->clocks[SYSC_FCK];
	2039	+ break;
	2040	+ case 0:
	2041	+ return 0;
	2042	+ }
	2043	+
	2044	+ error = pdata->init_clockdomain(ddata->dev, fck, ick, &ddata->cookie);
	2045	+ if (!error \|\| error == -ENODEV)
	2046	+ return 0;
	2047	+
	2048	+ return error;
	2049	+}
	2050	+
	2051	+/*
	2052	+ * Note that pdata->init_module() typically does a reset first. After
	2053	+ * pdata->init_module() is done, PM runtime can be used for the interconnect
	2054	+ * target module.
	2055	+ */
	2056	+static int sysc_legacy_init(struct sysc *ddata)
	2057	+{
	2058	+ struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
	2059	+ int error;
	2060	+
	2061	+ if (!pdata \|\| !pdata->init_module)
	2062	+ return 0;
	2063	+
	2064	+ error = pdata->init_module(ddata->dev, ddata->mdata, &ddata->cookie);
	2065	+ if (error == -EEXIST)
	2066	+ error = 0;
	2067	+
	2068	+ return error;
	2069	+}
	2070	+
	2071	+/*
	2072	+ * Note that the caller must ensure the interconnect target module is enabled
	2073	+ * before calling reset. Otherwise reset will not complete.
	2074	+ */
960	2075	static int sysc_reset(struct sysc *ddata)
961	2076	{
962		- int offset = ddata->offsets[SYSC_SYSCONFIG];
963		- int val;
	2077	+ int sysc_offset, sysc_val, error;
	2078	+ u32 sysc_mask;
964	2079
965		- if (ddata->legacy_mode \|\| offset < 0 \|\|
	2080	+ sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
	2081	+
	2082	+ if (ddata->legacy_mode \|\|
	2083	+ ddata->cap->regbits->srst_shift < 0 \|\|
966	2084	ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)
967	2085	return 0;
968	2086
969		- /*
970		- * Currently only support reset status in sysstatus.
971		- * Warn and return error in all other cases
972		- */
973		- if (!ddata->cfg.syss_mask) {
974		- dev_err(ddata->dev, "No ti,syss-mask. Reset failed\n");
975		- return -EINVAL;
	2087	+ sysc_mask = BIT(ddata->cap->regbits->srst_shift);
	2088	+
	2089	+ if (ddata->pre_reset_quirk)
	2090	+ ddata->pre_reset_quirk(ddata);
	2091	+
	2092	+ if (sysc_offset >= 0) {
	2093	+ sysc_val = sysc_read_sysconfig(ddata);
	2094	+ sysc_val \|= sysc_mask;
	2095	+ sysc_write(ddata, sysc_offset, sysc_val);
	2096	+ /* Flush posted write */
	2097	+ sysc_val = sysc_read_sysconfig(ddata);
976	2098	}
977	2099
978		- val = sysc_read(ddata, offset);
979		- val \|= (0x1 << ddata->cap->regbits->srst_shift);
980		- sysc_write(ddata, offset, val);
	2100	+ if (ddata->cfg.srst_udelay)
	2101	+ fsleep(ddata->cfg.srst_udelay);
981	2102
982		- /* Poll on reset status */
983		- offset = ddata->offsets[SYSC_SYSSTATUS];
	2103	+ if (ddata->post_reset_quirk)
	2104	+ ddata->post_reset_quirk(ddata);
984	2105
985		- return readl_poll_timeout(ddata->module_va + offset, val,
986		- (val & ddata->cfg.syss_mask) == 0x0,
987		- 100, MAX_MODULE_SOFTRESET_WAIT);
	2106	+ error = sysc_wait_softreset(ddata);
	2107	+ if (error)
	2108	+ dev_warn(ddata->dev, "OCP softreset timed out\n");
	2109	+
	2110	+ if (ddata->reset_done_quirk)
	2111	+ ddata->reset_done_quirk(ddata);
	2112	+
	2113	+ return error;
988	2114	}
989	2115
990		-/* At this point the module is configured enough to read the revision */
	2116	+/*
	2117	+ * At this point the module is configured enough to read the revision but
	2118	+ * module may not be completely configured yet to use PM runtime. Enable
	2119	+ * all clocks directly during init to configure the quirks needed for PM
	2120	+ * runtime based on the revision register.
	2121	+ */
991	2122	static int sysc_init_module(struct sysc *ddata)
992	2123	{
993		- int error;
	2124	+ int error = 0;
994	2125
995		- if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE_ON_INIT) {
996		- ddata->revision = sysc_read_revision(ddata);
997		- goto rev_quirks;
998		- }
999		-
1000		- error = pm_runtime_get_sync(ddata->dev);
1001		- if (error < 0) {
1002		- pm_runtime_put_noidle(ddata->dev);
1003		-
1004		- return 0;
1005		- }
1006		-
1007		- error = sysc_reset(ddata);
1008		- if (error) {
1009		- dev_err(ddata->dev, "Reset failed with %d\n", error);
1010		- pm_runtime_put_sync(ddata->dev);
1011		-
	2126	+ error = sysc_clockdomain_init(ddata);
	2127	+ if (error)
1012	2128	return error;
	2129	+
	2130	+ sysc_clkdm_deny_idle(ddata);
	2131	+
	2132	+ /*
	2133	+ * Always enable clocks. The bootloader may or may not have enabled
	2134	+ * the related clocks.
	2135	+ */
	2136	+ error = sysc_enable_opt_clocks(ddata);
	2137	+ if (error)
	2138	+ return error;
	2139	+
	2140	+ error = sysc_enable_main_clocks(ddata);
	2141	+ if (error)
	2142	+ goto err_opt_clocks;
	2143	+
	2144	+ if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT)) {
	2145	+ error = reset_control_deassert(ddata->rsts);
	2146	+ if (error)
	2147	+ goto err_main_clocks;
1013	2148	}
1014	2149
1015	2150	ddata->revision = sysc_read_revision(ddata);
1016		- pm_runtime_put_sync(ddata->dev);
1017		-
1018		-rev_quirks:
1019	2151	sysc_init_revision_quirks(ddata);
	2152	+ sysc_init_module_quirks(ddata);
1020	2153
1021		- return 0;
	2154	+ if (ddata->legacy_mode) {
	2155	+ error = sysc_legacy_init(ddata);
	2156	+ if (error)
	2157	+ goto err_reset;
	2158	+ }
	2159	+
	2160	+ if (!ddata->legacy_mode) {
	2161	+ error = sysc_enable_module(ddata->dev);
	2162	+ if (error)
	2163	+ goto err_reset;
	2164	+ }
	2165	+
	2166	+ error = sysc_reset(ddata);
	2167	+ if (error)
	2168	+ dev_err(ddata->dev, "Reset failed with %d\n", error);
	2169	+
	2170	+ if (error && !ddata->legacy_mode)
	2171	+ sysc_disable_module(ddata->dev);
	2172	+
	2173	+err_reset:
	2174	+ if (error && !(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
	2175	+ reset_control_assert(ddata->rsts);
	2176	+
	2177	+err_main_clocks:
	2178	+ if (error)
	2179	+ sysc_disable_main_clocks(ddata);
	2180	+err_opt_clocks:
	2181	+ /* No re-enable of clockdomain autoidle to prevent module autoidle */
	2182	+ if (error) {
	2183	+ sysc_disable_opt_clocks(ddata);
	2184	+ sysc_clkdm_allow_idle(ddata);
	2185	+ }
	2186	+
	2187	+ return error;
1022	2188	}
1023	2189
1024	2190	static int sysc_init_sysc_mask(struct sysc *ddata)
..	..	@@ -1120,9 +2286,8 @@
1120	2286
1121	2287	clk = clk_get(child, name);
1122	2288	if (!IS_ERR(clk)) {
1123		- clk_put(clk);
1124		-
1125		- return -EEXIST;
	2289	+ error = -EEXIST;
	2290	+ goto put_clk;
1126	2291	}
1127	2292
1128	2293	clk = clk_get(ddata->dev, name);
..	..	@@ -1132,7 +2297,7 @@
1132	2297	l = clkdev_create(clk, name, dev_name(child));
1133	2298	if (!l)
1134	2299	error = -ENOMEM;
1135		-
	2300	+put_clk:
1136	2301	clk_put(clk);
1137	2302
1138	2303	return error;
..	..	@@ -1227,8 +2392,8 @@
1227	2392	if (!pm_runtime_status_suspended(dev)) {
1228	2393	error = pm_generic_runtime_suspend(dev);
1229	2394	if (error) {
1230		- dev_warn(dev, "%s busy at %i: %i\n",
1231		- __func__, __LINE__, error);
	2395	+ dev_dbg(dev, "%s busy at %i: %i\n",
	2396	+ __func__, __LINE__, error);
1232	2397
1233	2398	return 0;
1234	2399	}
..	..	@@ -1277,7 +2442,7 @@
1277	2442	}
1278	2443	#endif
1279	2444
1280		-struct dev_pm_domain sysc_child_pm_domain = {
	2445	+static struct dev_pm_domain sysc_child_pm_domain = {
1281	2446	.ops = {
1282	2447	SET_RUNTIME_PM_OPS(sysc_child_runtime_suspend,
1283	2448	sysc_child_runtime_resume,
..	..	@@ -1287,6 +2452,78 @@
1287	2452	sysc_child_resume_noirq)
1288	2453	}
1289	2454	};
	2455	+
	2456	+/* Caller needs to take list_lock if ever used outside of cpu_pm */
	2457	+static void sysc_reinit_modules(struct sysc_soc_info *soc)
	2458	+{
	2459	+ struct sysc_module *module;
	2460	+ struct list_head *pos;
	2461	+ struct sysc *ddata;
	2462	+
	2463	+ list_for_each(pos, &sysc_soc->restored_modules) {
	2464	+ module = list_entry(pos, struct sysc_module, node);
	2465	+ ddata = module->ddata;
	2466	+ sysc_reinit_module(ddata, ddata->enabled);
	2467	+ }
	2468	+}
	2469	+
	2470	+/**
	2471	+ * sysc_context_notifier - optionally reset and restore module after idle
	2472	+ * @nb: notifier block
	2473	+ * @cmd: unused
	2474	+ * @v: unused
	2475	+ *
	2476	+ * Some interconnect target modules need to be restored, or reset and restored
	2477	+ * on CPU_PM CPU_PM_CLUSTER_EXIT notifier. This is needed at least for am335x
	2478	+ * OTG and GPMC target modules even if the modules are unused.
	2479	+ */
	2480	+static int sysc_context_notifier(struct notifier_block *nb, unsigned long cmd,
	2481	+ void *v)
	2482	+{
	2483	+ struct sysc_soc_info *soc;
	2484	+
	2485	+ soc = container_of(nb, struct sysc_soc_info, nb);
	2486	+
	2487	+ switch (cmd) {
	2488	+ case CPU_CLUSTER_PM_ENTER:
	2489	+ break;
	2490	+ case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
	2491	+ break;
	2492	+ case CPU_CLUSTER_PM_EXIT:
	2493	+ sysc_reinit_modules(soc);
	2494	+ break;
	2495	+ }
	2496	+
	2497	+ return NOTIFY_OK;
	2498	+}
	2499	+
	2500	+/**
	2501	+ * sysc_add_restored - optionally add reset and restore quirk hanlling
	2502	+ * @ddata: device data
	2503	+ */
	2504	+static void sysc_add_restored(struct sysc *ddata)
	2505	+{
	2506	+ struct sysc_module *restored_module;
	2507	+
	2508	+ restored_module = kzalloc(sizeof(*restored_module), GFP_KERNEL);
	2509	+ if (!restored_module)
	2510	+ return;
	2511	+
	2512	+ restored_module->ddata = ddata;
	2513	+
	2514	+ mutex_lock(&sysc_soc->list_lock);
	2515	+
	2516	+ list_add(&restored_module->node, &sysc_soc->restored_modules);
	2517	+
	2518	+ if (sysc_soc->nb.notifier_call)
	2519	+ goto out_unlock;
	2520	+
	2521	+ sysc_soc->nb.notifier_call = sysc_context_notifier;
	2522	+ cpu_pm_register_notifier(&sysc_soc->nb);
	2523	+
	2524	+out_unlock:
	2525	+ mutex_unlock(&sysc_soc->list_lock);
	2526	+}
1290	2527
1291	2528	/**
1292	2529	* sysc_legacy_idle_quirk - handle children in omap_device compatible way
..	..	@@ -1303,9 +2540,6 @@
1303	2540	*/
1304	2541	static void sysc_legacy_idle_quirk(struct sysc ddata, struct device child)
1305	2542	{
1306		- if (!ddata->legacy_mode)
1307		- return;
1308		-
1309	2543	if (ddata->cfg.quirks & SYSC_QUIRK_LEGACY_IDLE)
1310	2544	dev_pm_domain_set(child, &sysc_child_pm_domain);
1311	2545	}
..	..	@@ -1350,6 +2584,8 @@
1350	2584	.mask = SYSC_QUIRK_NO_IDLE_ON_INIT, },
1351	2585	{ .name = "ti,no-reset-on-init",
1352	2586	.mask = SYSC_QUIRK_NO_RESET_ON_INIT, },
	2587	+ { .name = "ti,no-idle",
	2588	+ .mask = SYSC_QUIRK_NO_IDLE, },
1353	2589	};
1354	2590
1355	2591	static void sysc_parse_dts_quirks(struct sysc ddata, struct device_node np,
..	..	@@ -1643,33 +2879,44 @@
1643	2879	.type = TI_SYSC_DRA7_MCAN,
1644	2880	.sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP \| SYSC_OMAP4_SOFTRESET,
1645	2881	.regbits = &sysc_regbits_dra7_mcan,
	2882	+ .mod_quirks = SYSS_QUIRK_RESETDONE_INVERTED,
	2883	+};
	2884	+
	2885	+/*
	2886	+ * PRUSS found on some AM33xx, AM437x and AM57xx SoCs
	2887	+ */
	2888	+static const struct sysc_capabilities sysc_pruss = {
	2889	+ .type = TI_SYSC_PRUSS,
	2890	+ .sysc_mask = SYSC_PRUSS_STANDBY_INIT \| SYSC_PRUSS_SUB_MWAIT,
	2891	+ .regbits = &sysc_regbits_omap4_simple,
	2892	+ .mod_quirks = SYSC_MODULE_QUIRK_PRUSS,
1646	2893	};
1647	2894
1648	2895	static int sysc_init_pdata(struct sysc *ddata)
1649	2896	{
1650	2897	struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
1651		- struct ti_sysc_module_data mdata;
1652		- int error = 0;
	2898	+ struct ti_sysc_module_data *mdata;
1653	2899
1654		- if (!pdata \|\| !ddata->legacy_mode)
	2900	+ if (!pdata)
1655	2901	return 0;
1656	2902
1657		- mdata.name = ddata->legacy_mode;
1658		- mdata.module_pa = ddata->module_pa;
1659		- mdata.module_size = ddata->module_size;
1660		- mdata.offsets = ddata->offsets;
1661		- mdata.nr_offsets = SYSC_MAX_REGS;
1662		- mdata.cap = ddata->cap;
1663		- mdata.cfg = &ddata->cfg;
	2903	+ mdata = devm_kzalloc(ddata->dev, sizeof(*mdata), GFP_KERNEL);
	2904	+ if (!mdata)
	2905	+ return -ENOMEM;
1664	2906
1665		- if (!pdata->init_module)
1666		- return -ENODEV;
	2907	+ if (ddata->legacy_mode) {
	2908	+ mdata->name = ddata->legacy_mode;
	2909	+ mdata->module_pa = ddata->module_pa;
	2910	+ mdata->module_size = ddata->module_size;
	2911	+ mdata->offsets = ddata->offsets;
	2912	+ mdata->nr_offsets = SYSC_MAX_REGS;
	2913	+ mdata->cap = ddata->cap;
	2914	+ mdata->cfg = &ddata->cfg;
	2915	+ }
1667	2916
1668		- error = pdata->init_module(ddata->dev, &mdata, &ddata->cookie);
1669		- if (error == -EEXIST)
1670		- error = 0;
	2917	+ ddata->mdata = mdata;
1671	2918
1672		- return error;
	2919	+ return 0;
1673	2920	}
1674	2921
1675	2922	static int sysc_init_match(struct sysc *ddata)
..	..	@@ -1693,8 +2940,236 @@
1693	2940
1694	2941	ddata = container_of(work, struct sysc, idle_work.work);
1695	2942
	2943	+ /*
	2944	+ * One time decrement of clock usage counts if left on from init.
	2945	+ * Note that we disable opt clocks unconditionally in this case
	2946	+ * as they are enabled unconditionally during init without
	2947	+ * considering sysc_opt_clks_needed() at that point.
	2948	+ */
	2949	+ if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE \|
	2950	+ SYSC_QUIRK_NO_IDLE_ON_INIT)) {
	2951	+ sysc_disable_main_clocks(ddata);
	2952	+ sysc_disable_opt_clocks(ddata);
	2953	+ sysc_clkdm_allow_idle(ddata);
	2954	+ }
	2955	+
	2956	+ /* Keep permanent PM runtime usage count for SYSC_QUIRK_NO_IDLE */
	2957	+ if (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE)
	2958	+ return;
	2959	+
	2960	+ /*
	2961	+ * Decrement PM runtime usage count for SYSC_QUIRK_NO_IDLE_ON_INIT
	2962	+ * and SYSC_QUIRK_NO_RESET_ON_INIT
	2963	+ */
1696	2964	if (pm_runtime_active(ddata->dev))
1697	2965	pm_runtime_put_sync(ddata->dev);
	2966	+}
	2967	+
	2968	+/*
	2969	+ * SoC model and features detection. Only needed for SoCs that need
	2970	+ * special handling for quirks, no need to list others.
	2971	+ */
	2972	+static const struct soc_device_attribute sysc_soc_match[] = {
	2973	+ SOC_FLAG("OMAP242*", SOC_2420),
	2974	+ SOC_FLAG("OMAP243*", SOC_2430),
	2975	+ SOC_FLAG("AM35*", SOC_AM35),
	2976	+ SOC_FLAG("OMAP3[45]*", SOC_3430),
	2977	+ SOC_FLAG("OMAP3[67]*", SOC_3630),
	2978	+ SOC_FLAG("OMAP443*", SOC_4430),
	2979	+ SOC_FLAG("OMAP446*", SOC_4460),
	2980	+ SOC_FLAG("OMAP447*", SOC_4470),
	2981	+ SOC_FLAG("OMAP54*", SOC_5430),
	2982	+ SOC_FLAG("AM433", SOC_AM3),
	2983	+ SOC_FLAG("AM43*", SOC_AM4),
	2984	+ SOC_FLAG("DRA7*", SOC_DRA7),
	2985	+
	2986	+ { /* sentinel */ },
	2987	+};
	2988	+
	2989	+/*
	2990	+ * List of SoCs variants with disabled features. By default we assume all
	2991	+ * devices in the device tree are available so no need to list those SoCs.
	2992	+ */
	2993	+static const struct soc_device_attribute sysc_soc_feat_match[] = {
	2994	+ /* OMAP3430/3530 and AM3517 variants with some accelerators disabled */
	2995	+ SOC_FLAG("AM3505", DIS_SGX),
	2996	+ SOC_FLAG("OMAP3525", DIS_SGX),
	2997	+ SOC_FLAG("OMAP3515", DIS_IVA \| DIS_SGX),
	2998	+ SOC_FLAG("OMAP3503", DIS_ISP \| DIS_IVA \| DIS_SGX),
	2999	+
	3000	+ /* OMAP3630/DM3730 variants with some accelerators disabled */
	3001	+ SOC_FLAG("AM3703", DIS_IVA \| DIS_SGX),
	3002	+ SOC_FLAG("DM3725", DIS_SGX),
	3003	+ SOC_FLAG("OMAP3611", DIS_ISP \| DIS_IVA \| DIS_SGX),
	3004	+ SOC_FLAG("OMAP3615/AM3715", DIS_IVA),
	3005	+ SOC_FLAG("OMAP3621", DIS_ISP),
	3006	+
	3007	+ { /* sentinel */ },
	3008	+};
	3009	+
	3010	+static int sysc_add_disabled(unsigned long base)
	3011	+{
	3012	+ struct sysc_address *disabled_module;
	3013	+
	3014	+ disabled_module = kzalloc(sizeof(*disabled_module), GFP_KERNEL);
	3015	+ if (!disabled_module)
	3016	+ return -ENOMEM;
	3017	+
	3018	+ disabled_module->base = base;
	3019	+
	3020	+ mutex_lock(&sysc_soc->list_lock);
	3021	+ list_add(&disabled_module->node, &sysc_soc->disabled_modules);
	3022	+ mutex_unlock(&sysc_soc->list_lock);
	3023	+
	3024	+ return 0;
	3025	+}
	3026	+
	3027	+/*
	3028	+ * One time init to detect the booted SoC, disable unavailable features
	3029	+ * and initialize list for optional cpu_pm notifier.
	3030	+ *
	3031	+ * Note that we initialize static data shared across all ti-sysc instances
	3032	+ * so ddata is only used for SoC type. This can be called from module_init
	3033	+ * once we no longer need to rely on platform data.
	3034	+ */
	3035	+static int sysc_init_static_data(struct sysc *ddata)
	3036	+{
	3037	+ const struct soc_device_attribute *match;
	3038	+ struct ti_sysc_platform_data *pdata;
	3039	+ unsigned long features = 0;
	3040	+
	3041	+ if (sysc_soc)
	3042	+ return 0;
	3043	+
	3044	+ sysc_soc = kzalloc(sizeof(*sysc_soc), GFP_KERNEL);
	3045	+ if (!sysc_soc)
	3046	+ return -ENOMEM;
	3047	+
	3048	+ mutex_init(&sysc_soc->list_lock);
	3049	+ INIT_LIST_HEAD(&sysc_soc->disabled_modules);
	3050	+ INIT_LIST_HEAD(&sysc_soc->restored_modules);
	3051	+ sysc_soc->general_purpose = true;
	3052	+
	3053	+ pdata = dev_get_platdata(ddata->dev);
	3054	+ if (pdata && pdata->soc_type_gp)
	3055	+ sysc_soc->general_purpose = pdata->soc_type_gp();
	3056	+
	3057	+ match = soc_device_match(sysc_soc_match);
	3058	+ if (match && match->data)
	3059	+ sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data;
	3060	+
	3061	+ /* Ignore devices that are not available on HS and EMU SoCs */
	3062	+ if (!sysc_soc->general_purpose) {
	3063	+ switch (sysc_soc->soc) {
	3064	+ case SOC_3430 ... SOC_3630:
	3065	+ sysc_add_disabled(0x48304000); /* timer12 */
	3066	+ break;
	3067	+ case SOC_AM3:
	3068	+ sysc_add_disabled(0x48310000); /* rng */
	3069	+ break;
	3070	+ default:
	3071	+ break;
	3072	+ };
	3073	+ }
	3074	+
	3075	+ match = soc_device_match(sysc_soc_feat_match);
	3076	+ if (!match)
	3077	+ return 0;
	3078	+
	3079	+ if (match->data)
	3080	+ features = (unsigned long)match->data;
	3081	+
	3082	+ /*
	3083	+ * Add disabled devices to the list based on the module base.
	3084	+ * Note that this must be done before we attempt to access the
	3085	+ * device and have module revision checks working.
	3086	+ */
	3087	+ if (features & DIS_ISP)
	3088	+ sysc_add_disabled(0x480bd400);
	3089	+ if (features & DIS_IVA)
	3090	+ sysc_add_disabled(0x5d000000);
	3091	+ if (features & DIS_SGX)
	3092	+ sysc_add_disabled(0x50000000);
	3093	+
	3094	+ return 0;
	3095	+}
	3096	+
	3097	+static void sysc_cleanup_static_data(void)
	3098	+{
	3099	+ struct sysc_module *restored_module;
	3100	+ struct sysc_address *disabled_module;
	3101	+ struct list_head pos, tmp;
	3102	+
	3103	+ if (!sysc_soc)
	3104	+ return;
	3105	+
	3106	+ if (sysc_soc->nb.notifier_call)
	3107	+ cpu_pm_unregister_notifier(&sysc_soc->nb);
	3108	+
	3109	+ mutex_lock(&sysc_soc->list_lock);
	3110	+ list_for_each_safe(pos, tmp, &sysc_soc->restored_modules) {
	3111	+ restored_module = list_entry(pos, struct sysc_module, node);
	3112	+ list_del(pos);
	3113	+ kfree(restored_module);
	3114	+ }
	3115	+ list_for_each_safe(pos, tmp, &sysc_soc->disabled_modules) {
	3116	+ disabled_module = list_entry(pos, struct sysc_address, node);
	3117	+ list_del(pos);
	3118	+ kfree(disabled_module);
	3119	+ }
	3120	+ mutex_unlock(&sysc_soc->list_lock);
	3121	+}
	3122	+
	3123	+static int sysc_check_disabled_devices(struct sysc *ddata)
	3124	+{
	3125	+ struct sysc_address *disabled_module;
	3126	+ struct list_head *pos;
	3127	+ int error = 0;
	3128	+
	3129	+ mutex_lock(&sysc_soc->list_lock);
	3130	+ list_for_each(pos, &sysc_soc->disabled_modules) {
	3131	+ disabled_module = list_entry(pos, struct sysc_address, node);
	3132	+ if (ddata->module_pa == disabled_module->base) {
	3133	+ dev_dbg(ddata->dev, "module disabled for this SoC\n");
	3134	+ error = -ENODEV;
	3135	+ break;
	3136	+ }
	3137	+ }
	3138	+ mutex_unlock(&sysc_soc->list_lock);
	3139	+
	3140	+ return error;
	3141	+}
	3142	+
	3143	+/*
	3144	+ * Ignore timers tagged with no-reset and no-idle. These are likely in use,
	3145	+ * for example by drivers/clocksource/timer-ti-dm-systimer.c. If more checks
	3146	+ * are needed, we could also look at the timer register configuration.
	3147	+ */
	3148	+static int sysc_check_active_timer(struct sysc *ddata)
	3149	+{
	3150	+ int error;
	3151	+
	3152	+ if (ddata->cap->type != TI_SYSC_OMAP2_TIMER &&
	3153	+ ddata->cap->type != TI_SYSC_OMAP4_TIMER)
	3154	+ return 0;
	3155	+
	3156	+ /*
	3157	+ * Quirk for omap3 beagleboard revision A to B4 to use gpt12.
	3158	+ * Revision C and later are fixed with commit 23885389dbbb ("ARM:
	3159	+ * dts: Fix timer regression for beagleboard revision c"). This all
	3160	+ * can be dropped if we stop supporting old beagleboard revisions
	3161	+ * A to B4 at some point.
	3162	+ */
	3163	+ if (sysc_soc->soc == SOC_3430 \|\| sysc_soc->soc == SOC_AM35)
	3164	+ error = -ENXIO;
	3165	+ else
	3166	+ error = -EBUSY;
	3167	+
	3168	+ if ((ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
	3169	+ (ddata->cfg.quirks & SYSC_QUIRK_NO_IDLE))
	3170	+ return error;
	3171	+
	3172	+ return 0;
1698	3173	}
1699	3174
1700	3175	static const struct of_device_id sysc_match_table[] = {
..	..	@@ -1715,15 +3190,15 @@
1715	3190	ddata->dev = &pdev->dev;
1716	3191	platform_set_drvdata(pdev, ddata);
1717	3192
	3193	+ error = sysc_init_static_data(ddata);
	3194	+ if (error)
	3195	+ return error;
	3196	+
1718	3197	error = sysc_init_match(ddata);
1719	3198	if (error)
1720	3199	return error;
1721	3200
1722	3201	error = sysc_init_dts_quirks(ddata);
1723		- if (error)
1724		- return error;
1725		-
1726		- error = sysc_get_clocks(ddata);
1727	3202	if (error)
1728	3203	return error;
1729	3204
..	..	@@ -1747,15 +3222,31 @@
1747	3222	if (error)
1748	3223	return error;
1749	3224
	3225	+ sysc_init_early_quirks(ddata);
	3226	+
	3227	+ error = sysc_check_disabled_devices(ddata);
	3228	+ if (error)
	3229	+ return error;
	3230	+
	3231	+ error = sysc_check_active_timer(ddata);
	3232	+ if (error == -ENXIO)
	3233	+ ddata->reserved = true;
	3234	+ else if (error)
	3235	+ return error;
	3236	+
	3237	+ error = sysc_get_clocks(ddata);
	3238	+ if (error)
	3239	+ return error;
	3240	+
1750	3241	error = sysc_init_resets(ddata);
1751	3242	if (error)
1752	3243	goto unprepare;
1753	3244
1754		- pm_runtime_enable(ddata->dev);
1755	3245	error = sysc_init_module(ddata);
1756	3246	if (error)
1757	3247	goto unprepare;
1758	3248
	3249	+ pm_runtime_enable(ddata->dev);
1759	3250	error = pm_runtime_get_sync(ddata->dev);
1760	3251	if (error < 0) {
1761	3252	pm_runtime_put_noidle(ddata->dev);
..	..	@@ -1763,27 +3254,43 @@
1763	3254	goto unprepare;
1764	3255	}
1765	3256
	3257	+ /* Balance use counts as PM runtime should have enabled these all */
	3258	+ if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT))
	3259	+ reset_control_assert(ddata->rsts);
	3260	+
	3261	+ if (!(ddata->cfg.quirks &
	3262	+ (SYSC_QUIRK_NO_IDLE \| SYSC_QUIRK_NO_IDLE_ON_INIT))) {
	3263	+ sysc_disable_main_clocks(ddata);
	3264	+ sysc_disable_opt_clocks(ddata);
	3265	+ sysc_clkdm_allow_idle(ddata);
	3266	+ }
	3267	+
1766	3268	sysc_show_registers(ddata);
1767	3269
1768	3270	ddata->dev->type = &sysc_device_type;
1769		- error = of_platform_populate(ddata->dev->of_node, sysc_match_table,
1770		- pdata ? pdata->auxdata : NULL,
1771		- ddata->dev);
1772		- if (error)
1773		- goto err;
	3271	+
	3272	+ if (!ddata->reserved) {
	3273	+ error = of_platform_populate(ddata->dev->of_node,
	3274	+ sysc_match_table,
	3275	+ pdata ? pdata->auxdata : NULL,
	3276	+ ddata->dev);
	3277	+ if (error)
	3278	+ goto err;
	3279	+ }
1774	3280
1775	3281	INIT_DELAYED_WORK(&ddata->idle_work, ti_sysc_idle);
1776	3282
1777	3283	/* At least earlycon won't survive without deferred idle */
1778		- if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE_ON_INIT \|
	3284	+ if (ddata->cfg.quirks & (SYSC_QUIRK_NO_IDLE \|
	3285	+ SYSC_QUIRK_NO_IDLE_ON_INIT \|
1779	3286	SYSC_QUIRK_NO_RESET_ON_INIT)) {
1780	3287	schedule_delayed_work(&ddata->idle_work, 3000);
1781	3288	} else {
1782	3289	pm_runtime_put(&pdev->dev);
1783	3290	}
1784	3291
1785		- if (!of_get_available_child_count(ddata->dev->of_node))
1786		- reset_control_assert(ddata->rsts);
	3292	+ if (ddata->cfg.quirks & SYSC_QUIRK_REINIT_ON_CTX_LOST)
	3293	+ sysc_add_restored(ddata);
1787	3294
1788	3295	return 0;
1789	3296
..	..	@@ -1801,7 +3308,9 @@
1801	3308	struct sysc *ddata = platform_get_drvdata(pdev);
1802	3309	int error;
1803	3310
1804		- cancel_delayed_work_sync(&ddata->idle_work);
	3311	+ /* Device can still be enabled, see deferred idle quirk in probe */
	3312	+ if (cancel_delayed_work_sync(&ddata->idle_work))
	3313	+ ti_sysc_idle(&ddata->idle_work.work);
1805	3314
1806	3315	error = pm_runtime_get_sync(ddata->dev);
1807	3316	if (error < 0) {
..	..	@@ -1840,6 +3349,7 @@
1840	3349	{ .compatible = "ti,sysc-usb-host-fs",
1841	3350	.data = &sysc_omap4_usb_host_fs, },
1842	3351	{ .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
	3352	+ { .compatible = "ti,sysc-pruss", .data = &sysc_pruss, },
1843	3353	{ },
1844	3354	};
1845	3355	MODULE_DEVICE_TABLE(of, sysc_match);
..	..	@@ -1866,6 +3376,7 @@
1866	3376	{
1867	3377	bus_unregister_notifier(&platform_bus_type, &sysc_nb);
1868	3378	platform_driver_unregister(&sysc_driver);
	3379	+ sysc_cleanup_static_data();
1869	3380	}
1870	3381	module_exit(sysc_exit);
1871	3382