add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/arch/x86/kernel/asm-offsets.c
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@@ -29,16 +29,13 @@
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 # include "asm-offsets_64.c"
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 #endif
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-void common(void) {
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+static void __used common(void)
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+{
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 	BLANK();
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 	OFFSET(TASK_threadsp, task_struct, thread.sp);
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 #ifdef CONFIG_STACKPROTECTOR
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 	OFFSET(TASK_stack_canary, task_struct, stack_canary);
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 #endif
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-
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-	BLANK();
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-	OFFSET(TASK_TI_flags, task_struct, thread_info.flags);
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-	OFFSET(TASK_addr_limit, task_struct, thread.addr_limit);
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 	BLANK();
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 	OFFSET(crypto_tfm_ctx_offset, crypto_tfm, __crt_ctx);
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@@ -64,21 +61,19 @@
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 	OFFSET(IA32_RT_SIGFRAME_sigcontext, rt_sigframe_ia32, uc.uc_mcontext);
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 #endif
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-#ifdef CONFIG_PARAVIRT
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+#ifdef CONFIG_PARAVIRT_XXL
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 	BLANK();
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-	OFFSET(PARAVIRT_PATCH_pv_cpu_ops, paravirt_patch_template, pv_cpu_ops);
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-	OFFSET(PARAVIRT_PATCH_pv_irq_ops, paravirt_patch_template, pv_irq_ops);
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-	OFFSET(PV_IRQ_irq_disable, pv_irq_ops, irq_disable);
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-	OFFSET(PV_IRQ_irq_enable, pv_irq_ops, irq_enable);
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-	OFFSET(PV_CPU_iret, pv_cpu_ops, iret);
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-	OFFSET(PV_CPU_read_cr0, pv_cpu_ops, read_cr0);
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-	OFFSET(PV_MMU_read_cr2, pv_mmu_ops, read_cr2);
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+	OFFSET(PV_IRQ_irq_disable, paravirt_patch_template, irq.irq_disable);
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+	OFFSET(PV_IRQ_irq_enable, paravirt_patch_template, irq.irq_enable);
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+	OFFSET(PV_CPU_iret, paravirt_patch_template, cpu.iret);
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+	OFFSET(PV_MMU_read_cr2, paravirt_patch_template, mmu.read_cr2);
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 #endif
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 #ifdef CONFIG_XEN
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 	BLANK();
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 	OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask);
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 	OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending);
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+	OFFSET(XEN_vcpu_info_arch_cr2, vcpu_info, arch.cr2);
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 #endif
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 	BLANK();
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@@ -90,7 +85,6 @@
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 	OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment);
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 	OFFSET(BP_init_size, boot_params, hdr.init_size);
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 	OFFSET(BP_pref_address, boot_params, hdr.pref_address);
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-	OFFSET(BP_code32_start, boot_params, hdr.code32_start);
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 	BLANK();
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 	DEFINE(PTREGS_SIZE, sizeof(struct pt_regs));
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@@ -99,13 +93,12 @@
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 	OFFSET(TLB_STATE_user_pcid_flush_mask, tlb_state, user_pcid_flush_mask);
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 	/* Layout info for cpu_entry_area */
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-	OFFSET(CPU_ENTRY_AREA_tss, cpu_entry_area, tss);
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-	OFFSET(CPU_ENTRY_AREA_entry_trampoline, cpu_entry_area, entry_trampoline);
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 	OFFSET(CPU_ENTRY_AREA_entry_stack, cpu_entry_area, entry_stack_page);
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 	DEFINE(SIZEOF_entry_stack, sizeof(struct entry_stack));
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 	DEFINE(MASK_entry_stack, (~(sizeof(struct entry_stack) - 1)));
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-	/* Offset for sp0 and sp1 into the tss_struct */
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+	/* Offset for fields in tss_struct */
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 	OFFSET(TSS_sp0, tss_struct, x86_tss.sp0);
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 	OFFSET(TSS_sp1, tss_struct, x86_tss.sp1);
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+	OFFSET(TSS_sp2, tss_struct, x86_tss.sp2);
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 }