add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/arch/x86/kernel/asm-offsets.c
..
..
@@ -29,17 +29,13 @@
29
29
 # include "asm-offsets_64.c"
30
30
 #endif
31
31
 
32
-void common(void) {
32
+static void __used common(void)
33
+{
33
34
 	BLANK();
34
35
 	OFFSET(TASK_threadsp, task_struct, thread.sp);
35
36
 #ifdef CONFIG_STACKPROTECTOR
36
37
 	OFFSET(TASK_stack_canary, task_struct, stack_canary);
37
38
 #endif
38
-
39
-	BLANK();
40
-	OFFSET(TASK_TI_flags, task_struct, thread_info.flags);
41
-	OFFSET(TASK_TI_preempt_lazy_count, task_struct, thread_info.preempt_lazy_count);
42
-	OFFSET(TASK_addr_limit, task_struct, thread.addr_limit);
43
39
 
44
40
 	BLANK();
45
41
 	OFFSET(crypto_tfm_ctx_offset, crypto_tfm, __crt_ctx);
..
..
@@ -65,21 +61,19 @@
65
61
 	OFFSET(IA32_RT_SIGFRAME_sigcontext, rt_sigframe_ia32, uc.uc_mcontext);
66
62
 #endif
67
63
 
68
-#ifdef CONFIG_PARAVIRT
64
+#ifdef CONFIG_PARAVIRT_XXL
69
65
 	BLANK();
70
-	OFFSET(PARAVIRT_PATCH_pv_cpu_ops, paravirt_patch_template, pv_cpu_ops);
71
-	OFFSET(PARAVIRT_PATCH_pv_irq_ops, paravirt_patch_template, pv_irq_ops);
72
-	OFFSET(PV_IRQ_irq_disable, pv_irq_ops, irq_disable);
73
-	OFFSET(PV_IRQ_irq_enable, pv_irq_ops, irq_enable);
74
-	OFFSET(PV_CPU_iret, pv_cpu_ops, iret);
75
-	OFFSET(PV_CPU_read_cr0, pv_cpu_ops, read_cr0);
76
-	OFFSET(PV_MMU_read_cr2, pv_mmu_ops, read_cr2);
66
+	OFFSET(PV_IRQ_irq_disable, paravirt_patch_template, irq.irq_disable);
67
+	OFFSET(PV_IRQ_irq_enable, paravirt_patch_template, irq.irq_enable);
68
+	OFFSET(PV_CPU_iret, paravirt_patch_template, cpu.iret);
69
+	OFFSET(PV_MMU_read_cr2, paravirt_patch_template, mmu.read_cr2);
77
70
 #endif
78
71
 
79
72
 #ifdef CONFIG_XEN
80
73
 	BLANK();
81
74
 	OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask);
82
75
 	OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending);
76
+	OFFSET(XEN_vcpu_info_arch_cr2, vcpu_info, arch.cr2);
83
77
 #endif
84
78
 
85
79
 	BLANK();
..
..
@@ -91,23 +85,20 @@
91
85
 	OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment);
92
86
 	OFFSET(BP_init_size, boot_params, hdr.init_size);
93
87
 	OFFSET(BP_pref_address, boot_params, hdr.pref_address);
94
-	OFFSET(BP_code32_start, boot_params, hdr.code32_start);
95
88
 
96
89
 	BLANK();
97
90
 	DEFINE(PTREGS_SIZE, sizeof(struct pt_regs));
98
-	DEFINE(_PREEMPT_ENABLED, PREEMPT_ENABLED);
99
91
 
100
92
 	/* TLB state for the entry code */
101
93
 	OFFSET(TLB_STATE_user_pcid_flush_mask, tlb_state, user_pcid_flush_mask);
102
94
 
103
95
 	/* Layout info for cpu_entry_area */
104
-	OFFSET(CPU_ENTRY_AREA_tss, cpu_entry_area, tss);
105
-	OFFSET(CPU_ENTRY_AREA_entry_trampoline, cpu_entry_area, entry_trampoline);
106
96
 	OFFSET(CPU_ENTRY_AREA_entry_stack, cpu_entry_area, entry_stack_page);
107
97
 	DEFINE(SIZEOF_entry_stack, sizeof(struct entry_stack));
108
98
 	DEFINE(MASK_entry_stack, (~(sizeof(struct entry_stack) - 1)));
109
99
 
110
-	/* Offset for sp0 and sp1 into the tss_struct */
100
+	/* Offset for fields in tss_struct */
111
101
 	OFFSET(TSS_sp0, tss_struct, x86_tss.sp0);
112
102
 	OFFSET(TSS_sp1, tss_struct, x86_tss.sp1);
103
+	OFFSET(TSS_sp2, tss_struct, x86_tss.sp2);
113
104
 }