.. | .. |
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17 | 17 | #include <asm/cache.h> |
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18 | 18 | #include <asm/addrspace.h> |
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19 | 19 | #include <asm/machvec.h> |
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20 | | -#include <asm/pgtable.h> |
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| 20 | +#include <asm/page.h> |
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| 21 | +#include <linux/pgtable.h> |
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21 | 22 | #include <asm-generic/iomap.h> |
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22 | 23 | |
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23 | | -#ifdef __KERNEL__ |
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24 | 24 | #define __IO_PREFIX generic |
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25 | 25 | #include <asm/io_generic.h> |
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26 | | -#include <asm/io_trapped.h> |
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| 26 | +#include <asm-generic/pci_iomap.h> |
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27 | 27 | #include <mach/mangle-port.h> |
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28 | 28 | |
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29 | 29 | #define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v)) |
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.. | .. |
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114 | 114 | __BUILD_MEMORY_STRING(__raw_, b, u8) |
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115 | 115 | __BUILD_MEMORY_STRING(__raw_, w, u16) |
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116 | 116 | |
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117 | | -#ifdef CONFIG_SUPERH32 |
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118 | 117 | void __raw_writesl(void __iomem *addr, const void *data, int longlen); |
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119 | 118 | void __raw_readsl(const void __iomem *addr, void *data, int longlen); |
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120 | | -#else |
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121 | | -__BUILD_MEMORY_STRING(__raw_, l, u32) |
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122 | | -#endif |
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123 | 119 | |
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124 | 120 | __BUILD_MEMORY_STRING(__raw_, q, u64) |
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125 | 121 | |
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.. | .. |
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228 | 224 | |
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229 | 225 | #define IO_SPACE_LIMIT 0xffffffff |
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230 | 226 | |
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231 | | -/* synco on SH-4A, otherwise a nop */ |
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232 | | -#define mmiowb() wmb() |
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233 | | - |
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234 | 227 | /* We really want to try and get these to memcpy etc */ |
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235 | 228 | void memcpy_fromio(void *, const volatile void __iomem *, unsigned long); |
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236 | 229 | void memcpy_toio(volatile void __iomem *, const void *, unsigned long); |
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.. | .. |
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249 | 242 | #define phys_to_virt(address) (__va(address)) |
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250 | 243 | #endif |
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251 | 244 | |
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252 | | -/* |
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253 | | - * On 32-bit SH, we traditionally have the whole physical address space |
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254 | | - * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do |
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255 | | - * not need to do anything but place the address in the proper segment. |
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256 | | - * This is true for P1 and P2 addresses, as well as some P3 ones. |
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257 | | - * However, most of the P3 addresses and newer cores using extended |
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258 | | - * addressing need to map through page tables, so the ioremap() |
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259 | | - * implementation becomes a bit more complicated. |
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260 | | - * |
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261 | | - * See arch/sh/mm/ioremap.c for additional notes on this. |
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262 | | - * |
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263 | | - * We cheat a bit and always return uncachable areas until we've fixed |
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264 | | - * the drivers to handle caching properly. |
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265 | | - * |
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266 | | - * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply |
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267 | | - * doesn't exist, so everything must go through page tables. |
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268 | | - */ |
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269 | 245 | #ifdef CONFIG_MMU |
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| 246 | +void iounmap(void __iomem *addr); |
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270 | 247 | void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size, |
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271 | 248 | pgprot_t prot, void *caller); |
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272 | | -void __iounmap(void __iomem *addr); |
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273 | | - |
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274 | | -static inline void __iomem * |
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275 | | -__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot) |
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276 | | -{ |
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277 | | - return __ioremap_caller(offset, size, prot, __builtin_return_address(0)); |
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278 | | -} |
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279 | | - |
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280 | | -static inline void __iomem * |
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281 | | -__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot) |
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282 | | -{ |
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283 | | -#ifdef CONFIG_29BIT |
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284 | | - phys_addr_t last_addr = offset + size - 1; |
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285 | | - |
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286 | | - /* |
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287 | | - * For P1 and P2 space this is trivial, as everything is already |
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288 | | - * mapped. Uncached access for P1 addresses are done through P2. |
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289 | | - * In the P3 case or for addresses outside of the 29-bit space, |
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290 | | - * mapping must be done by the PMB or by using page tables. |
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291 | | - */ |
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292 | | - if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) { |
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293 | | - u64 flags = pgprot_val(prot); |
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294 | | - |
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295 | | - /* |
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296 | | - * Anything using the legacy PTEA space attributes needs |
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297 | | - * to be kicked down to page table mappings. |
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298 | | - */ |
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299 | | - if (unlikely(flags & _PAGE_PCC_MASK)) |
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300 | | - return NULL; |
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301 | | - if (unlikely(flags & _PAGE_CACHABLE)) |
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302 | | - return (void __iomem *)P1SEGADDR(offset); |
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303 | | - |
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304 | | - return (void __iomem *)P2SEGADDR(offset); |
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305 | | - } |
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306 | | - |
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307 | | - /* P4 above the store queues are always mapped. */ |
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308 | | - if (unlikely(offset >= P3_ADDR_MAX)) |
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309 | | - return (void __iomem *)P4SEGADDR(offset); |
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310 | | -#endif |
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311 | | - |
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312 | | - return NULL; |
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313 | | -} |
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314 | | - |
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315 | | -static inline void __iomem * |
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316 | | -__ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot) |
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317 | | -{ |
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318 | | - void __iomem *ret; |
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319 | | - |
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320 | | - ret = __ioremap_trapped(offset, size); |
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321 | | - if (ret) |
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322 | | - return ret; |
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323 | | - |
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324 | | - ret = __ioremap_29bit(offset, size, prot); |
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325 | | - if (ret) |
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326 | | - return ret; |
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327 | | - |
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328 | | - return __ioremap(offset, size, prot); |
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329 | | -} |
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330 | | -#else |
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331 | | -#define __ioremap(offset, size, prot) ((void __iomem *)(offset)) |
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332 | | -#define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset)) |
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333 | | -#define __iounmap(addr) do { } while (0) |
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334 | | -#endif /* CONFIG_MMU */ |
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335 | 249 | |
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336 | 250 | static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size) |
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337 | 251 | { |
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338 | | - return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE); |
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| 252 | + return __ioremap_caller(offset, size, PAGE_KERNEL_NOCACHE, |
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| 253 | + __builtin_return_address(0)); |
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339 | 254 | } |
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340 | 255 | |
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341 | 256 | static inline void __iomem * |
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342 | 257 | ioremap_cache(phys_addr_t offset, unsigned long size) |
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343 | 258 | { |
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344 | | - return __ioremap_mode(offset, size, PAGE_KERNEL); |
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| 259 | + return __ioremap_caller(offset, size, PAGE_KERNEL, |
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| 260 | + __builtin_return_address(0)); |
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345 | 261 | } |
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346 | 262 | #define ioremap_cache ioremap_cache |
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347 | 263 | |
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348 | 264 | #ifdef CONFIG_HAVE_IOREMAP_PROT |
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349 | | -static inline void __iomem * |
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350 | | -ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags) |
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| 265 | +static inline void __iomem *ioremap_prot(phys_addr_t offset, unsigned long size, |
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| 266 | + unsigned long flags) |
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351 | 267 | { |
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352 | | - return __ioremap_mode(offset, size, __pgprot(flags)); |
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| 268 | + return __ioremap_caller(offset, size, __pgprot(flags), |
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| 269 | + __builtin_return_address(0)); |
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353 | 270 | } |
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354 | | -#endif |
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| 271 | +#endif /* CONFIG_HAVE_IOREMAP_PROT */ |
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355 | 272 | |
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356 | | -#ifdef CONFIG_IOREMAP_FIXED |
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357 | | -extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t); |
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358 | | -extern int iounmap_fixed(void __iomem *); |
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359 | | -extern void ioremap_fixed_init(void); |
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360 | | -#else |
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361 | | -static inline void __iomem * |
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362 | | -ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot) |
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| 273 | +#else /* CONFIG_MMU */ |
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| 274 | +static inline void __iomem *ioremap(phys_addr_t offset, size_t size) |
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363 | 275 | { |
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364 | | - BUG(); |
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365 | | - return NULL; |
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| 276 | + return (void __iomem *)(unsigned long)offset; |
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366 | 277 | } |
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367 | 278 | |
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368 | | -static inline void ioremap_fixed_init(void) { } |
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369 | | -static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; } |
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370 | | -#endif |
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| 279 | +static inline void iounmap(volatile void __iomem *addr) { } |
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| 280 | +#endif /* CONFIG_MMU */ |
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371 | 281 | |
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372 | | -#define ioremap_nocache ioremap |
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373 | 282 | #define ioremap_uc ioremap |
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374 | | - |
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375 | | -static inline void iounmap(void __iomem *addr) |
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376 | | -{ |
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377 | | - __iounmap(addr); |
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378 | | -} |
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379 | 283 | |
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380 | 284 | /* |
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381 | 285 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem |
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.. | .. |
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391 | 295 | #define ARCH_HAS_VALID_PHYS_ADDR_RANGE |
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392 | 296 | int valid_phys_addr_range(phys_addr_t addr, size_t size); |
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393 | 297 | int valid_mmap_phys_addr_range(unsigned long pfn, size_t size); |
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394 | | - |
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395 | | -#endif /* __KERNEL__ */ |
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396 | 298 | |
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397 | 299 | #endif /* __ASM_SH_IO_H */ |
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