hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da
kernel/arch/riscv/include/asm/parse_asm.h
....@@ -3,6 +3,9 @@
33 * Copyright (C) 2020 SiFive
44 */
55
6
+#ifndef _ASM_RISCV_INSN_H
7
+#define _ASM_RISCV_INSN_H
8
+
69 #include <linux/bits.h>
710
811 /* The bit field of immediate value in I-type instruction */
....@@ -125,7 +128,7 @@
125128 #define FUNCT3_C_J 0xa000
126129 #define FUNCT3_C_JAL 0x2000
127130 #define FUNCT4_C_JR 0x8000
128
-#define FUNCT4_C_JALR 0xf000
131
+#define FUNCT4_C_JALR 0x9000
129132
130133 #define FUNCT12_SRET 0x10200000
131134
....@@ -217,3 +220,5 @@
217220 (RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \
218221 (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \
219222 (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
223
+
224
+#endif /* _ASM_RISCV_INSN_H */