.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-or-later |
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1 | 2 | /* |
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2 | 3 | * Performance counter support for PPC970-family processors. |
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3 | 4 | * |
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4 | 5 | * Copyright 2008-2009 Paul Mackerras, IBM Corporation. |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or |
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7 | | - * modify it under the terms of the GNU General Public License |
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8 | | - * as published by the Free Software Foundation; either version |
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9 | | - * 2 of the License, or (at your option) any later version. |
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10 | 6 | */ |
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11 | 7 | #include <linux/string.h> |
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12 | 8 | #include <linux/perf_event.h> |
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13 | 9 | #include <asm/reg.h> |
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14 | 10 | #include <asm/cputable.h> |
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| 11 | + |
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| 12 | +#include "internal.h" |
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15 | 13 | |
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16 | 14 | /* |
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17 | 15 | * Bits in event code for PPC970 |
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.. | .. |
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257 | 255 | } |
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258 | 256 | |
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259 | 257 | static int p970_compute_mmcr(u64 event[], int n_ev, |
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260 | | - unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]) |
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| 258 | + unsigned int hwc[], struct mmcr_regs *mmcr, |
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| 259 | + struct perf_event *pevents[]) |
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261 | 260 | { |
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262 | 261 | unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0; |
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263 | 262 | unsigned int pmc, unit, byte, psel; |
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.. | .. |
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397 | 396 | mmcra |= 0x2000; /* mark only one IOP per PPC instruction */ |
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398 | 397 | |
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399 | 398 | /* Return MMCRx values */ |
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400 | | - mmcr[0] = mmcr0; |
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401 | | - mmcr[1] = mmcr1; |
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402 | | - mmcr[2] = mmcra; |
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| 399 | + mmcr->mmcr0 = mmcr0; |
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| 400 | + mmcr->mmcr1 = mmcr1; |
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| 401 | + mmcr->mmcra = mmcra; |
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403 | 402 | return 0; |
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404 | 403 | } |
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405 | 404 | |
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406 | | -static void p970_disable_pmc(unsigned int pmc, unsigned long mmcr[]) |
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| 405 | +static void p970_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr) |
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407 | 406 | { |
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408 | | - int shift, i; |
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| 407 | + int shift; |
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409 | 408 | |
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410 | | - if (pmc <= 1) { |
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411 | | - shift = MMCR0_PMC1SEL_SH - 7 * pmc; |
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412 | | - i = 0; |
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413 | | - } else { |
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414 | | - shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2); |
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415 | | - i = 1; |
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416 | | - } |
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417 | 409 | /* |
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418 | 410 | * Setting the PMCxSEL field to 0x08 disables PMC x. |
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419 | 411 | */ |
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420 | | - mmcr[i] = (mmcr[i] & ~(0x1fUL << shift)) | (0x08UL << shift); |
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| 412 | + if (pmc <= 1) { |
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| 413 | + shift = MMCR0_PMC1SEL_SH - 7 * pmc; |
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| 414 | + mmcr->mmcr0 = (mmcr->mmcr0 & ~(0x1fUL << shift)) | (0x08UL << shift); |
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| 415 | + } else { |
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| 416 | + shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2); |
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| 417 | + mmcr->mmcr1 = (mmcr->mmcr1 & ~(0x1fUL << shift)) | (0x08UL << shift); |
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| 418 | + } |
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421 | 419 | } |
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422 | 420 | |
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423 | 421 | static int ppc970_generic_events[] = { |
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.. | .. |
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436 | 434 | * 0 means not supported, -1 means nonsensical, other values |
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437 | 435 | * are event codes. |
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438 | 436 | */ |
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439 | | -static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { |
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| 437 | +static u64 ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { |
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440 | 438 | [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ |
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441 | 439 | [C(OP_READ)] = { 0x8810, 0x3810 }, |
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442 | 440 | [C(OP_WRITE)] = { 0x7810, 0x813 }, |
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.. | .. |
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490 | 488 | .flags = PPMU_NO_SIPR | PPMU_NO_CONT_SAMPLING, |
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491 | 489 | }; |
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492 | 490 | |
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493 | | -static int __init init_ppc970_pmu(void) |
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| 491 | +int init_ppc970_pmu(void) |
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494 | 492 | { |
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495 | 493 | if (!cur_cpu_spec->oprofile_cpu_type || |
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496 | 494 | (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970") |
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.. | .. |
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499 | 497 | |
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500 | 498 | return register_power_pmu(&ppc970_pmu); |
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501 | 499 | } |
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502 | | - |
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503 | | -early_initcall(init_ppc970_pmu); |
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