.. | .. |
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46 | 46 | PERF_REG_POWERPC_TRAP, |
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47 | 47 | PERF_REG_POWERPC_DAR, |
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48 | 48 | PERF_REG_POWERPC_DSISR, |
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49 | | - PERF_REG_POWERPC_MAX, |
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| 49 | + PERF_REG_POWERPC_SIER, |
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| 50 | + PERF_REG_POWERPC_MMCRA, |
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| 51 | + /* Extended registers */ |
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| 52 | + PERF_REG_POWERPC_MMCR0, |
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| 53 | + PERF_REG_POWERPC_MMCR1, |
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| 54 | + PERF_REG_POWERPC_MMCR2, |
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| 55 | + PERF_REG_POWERPC_MMCR3, |
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| 56 | + PERF_REG_POWERPC_SIER2, |
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| 57 | + PERF_REG_POWERPC_SIER3, |
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| 58 | + /* Max regs without the extended regs */ |
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| 59 | + PERF_REG_POWERPC_MAX = PERF_REG_POWERPC_MMCRA + 1, |
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50 | 60 | }; |
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| 61 | + |
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| 62 | +#define PERF_REG_PMU_MASK ((1ULL << PERF_REG_POWERPC_MAX) - 1) |
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| 63 | + |
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| 64 | +/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_300 */ |
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| 65 | +#define PERF_REG_PMU_MASK_300 (((1ULL << (PERF_REG_POWERPC_MMCR2 + 1)) - 1) - PERF_REG_PMU_MASK) |
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| 66 | +/* PERF_REG_EXTENDED_MASK value for CPU_FTR_ARCH_31 */ |
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| 67 | +#define PERF_REG_PMU_MASK_31 (((1ULL << (PERF_REG_POWERPC_SIER3 + 1)) - 1) - PERF_REG_PMU_MASK) |
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| 68 | + |
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| 69 | +#define PERF_REG_MAX_ISA_300 (PERF_REG_POWERPC_MMCR2 + 1) |
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| 70 | +#define PERF_REG_MAX_ISA_31 (PERF_REG_POWERPC_SIER3 + 1) |
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51 | 71 | #endif /* _UAPI_ASM_POWERPC_PERF_REGS_H */ |
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