hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da
kernel/arch/powerpc/include/asm/reg_8xx.h
....@@ -5,8 +5,6 @@
55 #ifndef _ASM_POWERPC_REG_8xx_H
66 #define _ASM_POWERPC_REG_8xx_H
77
8
-#include <asm/mmu.h>
9
-
108 /* Cache control on the MPC8xx is provided through some additional
119 * special purpose registers.
1210 */
....@@ -37,8 +35,24 @@
3735 #define SPRN_CMPE 152
3836 #define SPRN_CMPF 153
3937 #define SPRN_LCTRL1 156
38
+#define LCTRL1_CTE_GT 0xc0000000
39
+#define LCTRL1_CTF_LT 0x14000000
40
+#define LCTRL1_CRWE_RW 0x00000000
41
+#define LCTRL1_CRWE_RO 0x00040000
42
+#define LCTRL1_CRWE_WO 0x000c0000
43
+#define LCTRL1_CRWF_RW 0x00000000
44
+#define LCTRL1_CRWF_RO 0x00010000
45
+#define LCTRL1_CRWF_WO 0x00030000
4046 #define SPRN_LCTRL2 157
47
+#define LCTRL2_LW0EN 0x80000000
48
+#define LCTRL2_LW0LA_E 0x00000000
49
+#define LCTRL2_LW0LA_F 0x04000000
50
+#define LCTRL2_LW0LA_EandF 0x08000000
51
+#define LCTRL2_LW0LADC 0x02000000
52
+#define LCTRL2_SLW0EN 0x00000002
53
+#ifdef CONFIG_PPC_8xx
4154 #define SPRN_ICTRL 158
55
+#endif
4256 #define SPRN_BAR 159
4357
4458 /* Commands. Only the first few are available to the instruction cache.