add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/arch/powerpc/include/asm/nohash/32/pte-40x.h
..
..
@@ -33,7 +33,7 @@
33
33
  *   is cleared in the TLB miss handler before the TLB entry is loaded.
34
34
  * - All other bits of the PTE are loaded into TLBLO without
35
35
  *   modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
36
- *   software PTE bits.  We actually use use bits 21, 24, 25, and
36
+ *   software PTE bits.  We actually use bits 21, 24, 25, and
37
37
  *   30 respectively for the software bits: ACCESSED, DIRTY, RW, and
38
38
  *   PRESENT.
39
39
  */
..
..
@@ -44,19 +44,45 @@
44
44
 #define	_PAGE_WRITETHRU	0x008	/* W: caching is write-through */
45
45
 #define	_PAGE_USER	0x010	/* matches one of the zone permission bits */
46
46
 #define	_PAGE_SPECIAL	0x020	/* software: Special page */
47
-#define	_PAGE_RW	0x040	/* software: Writes permitted */
48
47
 #define	_PAGE_DIRTY	0x080	/* software: dirty page */
49
-#define _PAGE_HWWRITE	0x100	/* hardware: Dirty & RW, set in exception */
48
+#define _PAGE_RW	0x100	/* hardware: WR, anded with dirty in exception */
50
49
 #define _PAGE_EXEC	0x200	/* hardware: EX permission */
51
50
 #define _PAGE_ACCESSED	0x400	/* software: R: page referenced */
52
51
 
52
+/* No page size encoding in the linux PTE */
53
+#define _PAGE_PSIZE		0
54
+
55
+/* cache related flags non existing on 40x */
56
+#define _PAGE_COHERENT	0
57
+
58
+#define _PAGE_KERNEL_RO		0
59
+#define _PAGE_KERNEL_ROX	_PAGE_EXEC
60
+#define _PAGE_KERNEL_RW		(_PAGE_DIRTY | _PAGE_RW)
61
+#define _PAGE_KERNEL_RWX	(_PAGE_DIRTY | _PAGE_RW | _PAGE_EXEC)
62
+
53
63
 #define _PMD_PRESENT	0x400	/* PMD points to page of PTEs */
64
+#define _PMD_PRESENT_MASK	_PMD_PRESENT
54
65
 #define _PMD_BAD	0x802
55
66
 #define _PMD_SIZE_4M	0x0c0
56
67
 #define _PMD_SIZE_16M	0x0e0
68
+#define _PMD_USER	0
69
+
70
+#define _PTE_NONE_MASK	0
57
71
 
58
72
 /* Until my rework is finished, 40x still needs atomic PTE updates */
59
73
 #define PTE_ATOMIC_UPDATES	1
60
74
 
75
+#define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED)
76
+#define _PAGE_BASE	(_PAGE_BASE_NC)
77
+
78
+/* Permission masks used to generate the __P and __S table */
79
+#define PAGE_NONE	__pgprot(_PAGE_BASE)
80
+#define PAGE_SHARED	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
81
+#define PAGE_SHARED_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
82
+#define PAGE_COPY	__pgprot(_PAGE_BASE | _PAGE_USER)
83
+#define PAGE_COPY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
84
+#define PAGE_READONLY	__pgprot(_PAGE_BASE | _PAGE_USER)
85
+#define PAGE_READONLY_X	__pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
86
+
61
87
 #endif /* __KERNEL__ */
62
88
 #endif /*  _ASM_POWERPC_NOHASH_32_PTE_40x_H */