add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/arch/powerpc/include/asm/exception-64e.h
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@@ -1,12 +1,8 @@
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+/* SPDX-License-Identifier: GPL-2.0-or-later */
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 /*
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  *  Definitions for use by exception code on Book3-E
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  *
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  *  Copyright (C) 2008 Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
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- *
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- *  This program is free software; you can redistribute it and/or
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- *  modify it under the terms of the GNU General Public License
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- *  as published by the Free Software Foundation; either version
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- *  2 of the License, or (at your option) any later version.
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  */
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 #ifndef _ASM_POWERPC_EXCEPTION_64E_H
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 #define _ASM_POWERPC_EXCEPTION_64E_H
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@@ -70,14 +66,7 @@
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 #define EX_TLB_SRR0	(10 * 8)
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 #define EX_TLB_SRR1	(11 * 8)
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 #define EX_TLB_R7	(12 * 8)
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-#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
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-#define EX_TLB_R8	(13 * 8)
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-#define EX_TLB_R9	(14 * 8)
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-#define EX_TLB_LR	(15 * 8)
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-#define EX_TLB_SIZE	(16 * 8)
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-#else
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 #define EX_TLB_SIZE	(13 * 8)
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-#endif
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 #define	START_EXCEPTION(label)						\
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 	.globl exc_##label##_book3e;					\
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@@ -114,8 +103,7 @@
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 	std	r11,EX_TLB_R12(r12);					    \
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 	mtspr	SPRN_SPRG_TLB_EXFRAME,r14;				    \
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 	std	r15,EX_TLB_SRR1(r12);					    \
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-	std	r16,EX_TLB_SRR0(r12);					    \
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-	TLB_MISS_PROLOG_STATS
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+	std	r16,EX_TLB_SRR0(r12);
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 /* And these are the matching epilogs that restores things
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  *
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@@ -147,7 +135,6 @@
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 	mtspr	SPRN_SRR0,r15;						    \
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 	ld	r15,EX_TLB_R15(r12);					    \
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 	mtspr	SPRN_SRR1,r16;						    \
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-	TLB_MISS_RESTORE_STATS						    \
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 	ld	r16,EX_TLB_R16(r12);					    \
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 	ld	r12,EX_TLB_R12(r12);					    \
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@@ -162,53 +149,15 @@
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 	addi	r11,r13,PACA_EXTLB;					    \
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 	TLB_MISS_RESTORE(r11)
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151
 
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-#ifdef CONFIG_BOOK3E_MMU_TLB_STATS
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-#define TLB_MISS_PROLOG_STATS						    \
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-	mflr	r10;							    \
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-	std	r8,EX_TLB_R8(r12);					    \
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-	std	r9,EX_TLB_R9(r12);					    \
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-	std	r10,EX_TLB_LR(r12);
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-#define TLB_MISS_RESTORE_STATS					            \
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-	ld	r16,EX_TLB_LR(r12);					    \
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-	ld	r9,EX_TLB_R9(r12);					    \
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-	ld	r8,EX_TLB_R8(r12);					    \
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-	mtlr	r16;
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-#define TLB_MISS_STATS_D(name)						    \
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-	addi	r9,r13,MMSTAT_DSTATS+name;				    \
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-	bl	tlb_stat_inc;
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-#define TLB_MISS_STATS_I(name)						    \
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-	addi	r9,r13,MMSTAT_ISTATS+name;				    \
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-	bl	tlb_stat_inc;
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-#define TLB_MISS_STATS_X(name)						    \
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-	ld	r8,PACA_EXTLB+EX_TLB_ESR(r13);				    \
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-	cmpdi	cr2,r8,-1;						    \
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-	beq	cr2,61f;						    \
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-	addi	r9,r13,MMSTAT_DSTATS+name;				    \
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-	b	62f;							    \
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-61:	addi	r9,r13,MMSTAT_ISTATS+name;				    \
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-62:	bl	tlb_stat_inc;
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-#define TLB_MISS_STATS_SAVE_INFO					    \
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-	std	r14,EX_TLB_ESR(r12);	/* save ESR */
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-#define TLB_MISS_STATS_SAVE_INFO_BOLTED					    \
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-	std	r14,PACA_EXTLB+EX_TLB_ESR(r13);	/* save ESR */
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-#else
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-#define TLB_MISS_PROLOG_STATS
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-#define TLB_MISS_RESTORE_STATS
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-#define TLB_MISS_PROLOG_STATS_BOLTED
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-#define TLB_MISS_RESTORE_STATS_BOLTED
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-#define TLB_MISS_STATS_D(name)
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-#define TLB_MISS_STATS_I(name)
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-#define TLB_MISS_STATS_X(name)
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-#define TLB_MISS_STATS_Y(name)
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-#define TLB_MISS_STATS_SAVE_INFO
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-#define TLB_MISS_STATS_SAVE_INFO_BOLTED
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-#endif
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-
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 #define SET_IVOR(vector_number, vector_offset)	\
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 	LOAD_REG_ADDR(r3,interrupt_base_book3e);\
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 	ori	r3,r3,vector_offset@l;		\
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 	mtspr	SPRN_IVOR##vector_number,r3;
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-
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+/*
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+ * powerpc relies on return from interrupt/syscall being context synchronising
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+ * (which rfi is) to support ARCH_HAS_MEMBARRIER_SYNC_CORE without additional
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+ * synchronisation instructions.
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+ */
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 #define RFI_TO_KERNEL							\
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 	rfi
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