add wifi6 8852be driver

hc

2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da

 kernel/arch/powerpc/include/asm/book3s/64/hash-4k.h
..
..
@@ -1,15 +1,11 @@
1
1
 /* SPDX-License-Identifier: GPL-2.0 */
2
2
 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
3
3
 #define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
4
-/*
5
- * Entries per page directory level.  The PTE level must use a 64b record
6
- * for each page table entry.  The PMD and PGD level use a 32b record for
7
- * each entry by assuming that each entry is page aligned.
8
- */
9
-#define H_PTE_INDEX_SIZE  9
10
-#define H_PMD_INDEX_SIZE  7
11
-#define H_PUD_INDEX_SIZE  9
12
-#define H_PGD_INDEX_SIZE  9
4
+
5
+#define H_PTE_INDEX_SIZE  9  // size: 8B << 9 = 4KB, maps: 2^9 x   4KB =   2MB
6
+#define H_PMD_INDEX_SIZE  7  // size: 8B << 7 = 1KB, maps: 2^7 x   2MB = 256MB
7
+#define H_PUD_INDEX_SIZE  9  // size: 8B << 9 = 4KB, maps: 2^9 x 256MB = 128GB
8
+#define H_PGD_INDEX_SIZE  9  // size: 8B << 9 = 4KB, maps: 2^9 x 128GB =  64TB
13
9
 
14
10
 /*
15
11
  * Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
..
..
@@ -17,17 +13,36 @@
17
13
  */
18
14
 #define MAX_EA_BITS_PER_CONTEXT		46
19
15
 
16
+
17
+/*
18
+ * Our page table limit us to 64TB. For 64TB physical memory, we only need 64GB
19
+ * of vmemmap space. To better support sparse memory layout, we use 61TB
20
+ * linear map range, 1TB of vmalloc, 1TB of I/O and 1TB of vmememmap.
21
+ */
22
+#define REGION_SHIFT		(40)
23
+#define H_KERN_MAP_SIZE		(ASM_CONST(1) << REGION_SHIFT)
24
+
25
+/*
26
+ * Limits the linear mapping range
27
+ */
28
+#define H_MAX_PHYSMEM_BITS	46
29
+
30
+/*
31
+ * Define the address range of the kernel non-linear virtual area (61TB)
32
+ */
33
+#define H_KERN_VIRT_START	ASM_CONST(0xc0003d0000000000)
34
+
20
35
 #ifndef __ASSEMBLY__
21
36
 #define H_PTE_TABLE_SIZE	(sizeof(pte_t) << H_PTE_INDEX_SIZE)
22
37
 #define H_PMD_TABLE_SIZE	(sizeof(pmd_t) << H_PMD_INDEX_SIZE)
23
38
 #define H_PUD_TABLE_SIZE	(sizeof(pud_t) << H_PUD_INDEX_SIZE)
24
39
 #define H_PGD_TABLE_SIZE	(sizeof(pgd_t) << H_PGD_INDEX_SIZE)
25
40
 
26
-#define H_PAGE_F_GIX_SHIFT	53
27
-#define H_PAGE_F_SECOND	_RPAGE_RPN44	/* HPTE is in 2ndary HPTEG */
28
-#define H_PAGE_F_GIX	(_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
29
-#define H_PAGE_BUSY	_RPAGE_RSV1     /* software: PTE & hash are busy */
30
-#define H_PAGE_HASHPTE	_RPAGE_RSV2     /* software: PTE & hash are busy */
41
+#define H_PAGE_F_GIX_SHIFT	_PAGE_PA_MAX
42
+#define H_PAGE_F_SECOND		_RPAGE_PKEY_BIT0 /* HPTE is in 2ndary HPTEG */
43
+#define H_PAGE_F_GIX		(_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
44
+#define H_PAGE_BUSY		_RPAGE_RSV1
45
+#define H_PAGE_HASHPTE		_RPAGE_PKEY_BIT4
31
46
 
32
47
 /* PTE flags to conserve for HPTE identification */
33
48
 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
..
..
@@ -46,11 +61,12 @@
46
61
 #define H_PMD_FRAG_NR	(PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT)
47
62
 
48
63
 /* memory key bits, only 8 keys supported */
49
-#define H_PTE_PKEY_BIT0	0
50
-#define H_PTE_PKEY_BIT1	0
51
-#define H_PTE_PKEY_BIT2	_RPAGE_RSV3
52
-#define H_PTE_PKEY_BIT3	_RPAGE_RSV4
53
-#define H_PTE_PKEY_BIT4	_RPAGE_RSV5
64
+#define H_PTE_PKEY_BIT4	0
65
+#define H_PTE_PKEY_BIT3	0
66
+#define H_PTE_PKEY_BIT2	_RPAGE_PKEY_BIT3
67
+#define H_PTE_PKEY_BIT1	_RPAGE_PKEY_BIT2
68
+#define H_PTE_PKEY_BIT0	_RPAGE_PKEY_BIT1
69
+
54
70
 
55
71
 /*
56
72
  * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
..
..
@@ -66,7 +82,7 @@
66
82
 	 * if it is not a pte and have hugepd shift mask
67
83
 	 * set, then it is a hugepd directory pointer
68
84
 	 */
69
-	if (!(hpdval & _PAGE_PTE) &&
85
+	if (!(hpdval & _PAGE_PTE) && (hpdval & _PAGE_PRESENT) &&
70
86
 	    ((hpdval & HUGEPD_SHIFT_MASK) != 0))
71
87
 		return true;
72
88
 	return false;