| .. | .. |
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| 34 | 34 | |
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| 35 | 35 | clockgen: global-utilities@e1000 { |
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| 36 | 36 | compatible = "fsl,qoriq-clockgen-1.0"; |
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| 37 | | - ranges = <0x0 0xe1000 0x1000>; |
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| 38 | 37 | reg = <0xe1000 0x1000>; |
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| 39 | | - clock-frequency = <0>; |
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| 40 | | - #address-cells = <1>; |
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| 41 | | - #size-cells = <1>; |
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| 42 | 38 | #clock-cells = <2>; |
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| 43 | | - |
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| 44 | | - sysclk: sysclk { |
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| 45 | | - #clock-cells = <0>; |
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| 46 | | - compatible = "fsl,qoriq-sysclk-1.0", "fixed-clock"; |
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| 47 | | - clock-output-names = "sysclk"; |
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| 48 | | - }; |
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| 49 | | - pll0: pll0@800 { |
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| 50 | | - #clock-cells = <1>; |
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| 51 | | - reg = <0x800 0x4>; |
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| 52 | | - compatible = "fsl,qoriq-core-pll-1.0"; |
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| 53 | | - clocks = <&sysclk>; |
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| 54 | | - clock-output-names = "pll0", "pll0-div2"; |
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| 55 | | - }; |
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| 56 | | - pll1: pll1@820 { |
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| 57 | | - #clock-cells = <1>; |
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| 58 | | - reg = <0x820 0x4>; |
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| 59 | | - compatible = "fsl,qoriq-core-pll-1.0"; |
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| 60 | | - clocks = <&sysclk>; |
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| 61 | | - clock-output-names = "pll1", "pll1-div2"; |
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| 62 | | - }; |
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| 63 | | - mux0: mux0@0 { |
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| 64 | | - #clock-cells = <0>; |
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| 65 | | - reg = <0x0 0x4>; |
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| 66 | | - compatible = "fsl,qoriq-core-mux-1.0"; |
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| 67 | | - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; |
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| 68 | | - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; |
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| 69 | | - clock-output-names = "cmux0"; |
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| 70 | | - }; |
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| 71 | | - mux1: mux1@20 { |
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| 72 | | - #clock-cells = <0>; |
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| 73 | | - reg = <0x20 0x4>; |
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| 74 | | - compatible = "fsl,qoriq-core-mux-1.0"; |
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| 75 | | - clocks = <&pll0 0>, <&pll0 1>, <&pll1 0>, <&pll1 1>; |
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| 76 | | - clock-names = "pll0", "pll0-div2", "pll1", "pll1-div2"; |
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| 77 | | - clock-output-names = "cmux1"; |
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| 78 | | - }; |
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| 79 | | - platform_pll: platform-pll@c00 { |
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| 80 | | - #clock-cells = <1>; |
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| 81 | | - reg = <0xc00 0x4>; |
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| 82 | | - compatible = "fsl,qoriq-platform-pll-1.0"; |
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| 83 | | - clocks = <&sysclk>; |
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| 84 | | - clock-output-names = "platform-pll", "platform-pll-div2"; |
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| 85 | | - }; |
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| 86 | 39 | }; |
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