| .. | .. |
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| 102 | 102 | cpu0: PowerPC,e5500@0 { |
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| 103 | 103 | device_type = "cpu"; |
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| 104 | 104 | reg = <0>; |
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| 105 | | - clocks = <&mux0>; |
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| 105 | + clocks = <&clockgen 1 0>; |
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| 106 | 106 | next-level-cache = <&L2_0>; |
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| 107 | 107 | fsl,portid-mapping = <0x80000000>; |
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| 108 | 108 | L2_0: l2-cache { |
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| .. | .. |
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| 112 | 112 | cpu1: PowerPC,e5500@1 { |
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| 113 | 113 | device_type = "cpu"; |
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| 114 | 114 | reg = <1>; |
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| 115 | | - clocks = <&mux1>; |
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| 115 | + clocks = <&clockgen 1 1>; |
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| 116 | 116 | next-level-cache = <&L2_1>; |
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| 117 | 117 | fsl,portid-mapping = <0x40000000>; |
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| 118 | 118 | L2_1: l2-cache { |
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| .. | .. |
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| 122 | 122 | cpu2: PowerPC,e5500@2 { |
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| 123 | 123 | device_type = "cpu"; |
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| 124 | 124 | reg = <2>; |
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| 125 | | - clocks = <&mux2>; |
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| 125 | + clocks = <&clockgen 1 2>; |
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| 126 | 126 | next-level-cache = <&L2_2>; |
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| 127 | 127 | fsl,portid-mapping = <0x20000000>; |
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| 128 | 128 | L2_2: l2-cache { |
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| .. | .. |
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| 132 | 132 | cpu3: PowerPC,e5500@3 { |
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| 133 | 133 | device_type = "cpu"; |
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| 134 | 134 | reg = <3>; |
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| 135 | | - clocks = <&mux3>; |
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| 135 | + clocks = <&clockgen 1 3>; |
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| 136 | 136 | next-level-cache = <&L2_3>; |
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| 137 | 137 | fsl,portid-mapping = <0x10000000>; |
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| 138 | 138 | L2_3: l2-cache { |
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