| .. | .. |
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| 75 | 75 | cpu0: PowerPC,e6500@0 { |
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| 76 | 76 | device_type = "cpu"; |
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| 77 | 77 | reg = <0 1>; |
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| 78 | | - clocks = <&mux0>; |
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| 78 | + clocks = <&clockgen 1 0>; |
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| 79 | 79 | next-level-cache = <&L2_1>; |
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| 80 | 80 | fsl,portid-mapping = <0x80000000>; |
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| 81 | 81 | }; |
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| 82 | 82 | cpu1: PowerPC,e6500@2 { |
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| 83 | 83 | device_type = "cpu"; |
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| 84 | 84 | reg = <2 3>; |
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| 85 | | - clocks = <&mux0>; |
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| 85 | + clocks = <&clockgen 1 0>; |
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| 86 | 86 | next-level-cache = <&L2_1>; |
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| 87 | 87 | fsl,portid-mapping = <0x80000000>; |
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| 88 | 88 | }; |
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| 89 | 89 | cpu2: PowerPC,e6500@4 { |
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| 90 | 90 | device_type = "cpu"; |
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| 91 | 91 | reg = <4 5>; |
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| 92 | | - clocks = <&mux0>; |
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| 92 | + clocks = <&clockgen 1 0>; |
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| 93 | 93 | next-level-cache = <&L2_1>; |
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| 94 | 94 | fsl,portid-mapping = <0x80000000>; |
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| 95 | 95 | }; |
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| 96 | 96 | cpu3: PowerPC,e6500@6 { |
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| 97 | 97 | device_type = "cpu"; |
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| 98 | 98 | reg = <6 7>; |
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| 99 | | - clocks = <&mux0>; |
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| 99 | + clocks = <&clockgen 1 0>; |
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| 100 | 100 | next-level-cache = <&L2_1>; |
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| 101 | 101 | fsl,portid-mapping = <0x80000000>; |
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| 102 | 102 | }; |
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