.. | .. |
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40 | 40 | |
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41 | 41 | #define FLUSH_RAC 0x100 |
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42 | 42 | |
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43 | | -dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t pa) |
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| 43 | +dma_addr_t phys_to_dma(struct device *dev, phys_addr_t pa) |
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44 | 44 | { |
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45 | 45 | struct bmips_dma_range *r; |
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46 | 46 | |
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.. | .. |
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52 | 52 | return pa; |
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53 | 53 | } |
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54 | 54 | |
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55 | | -phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dma_addr) |
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| 55 | +phys_addr_t dma_to_phys(struct device *dev, dma_addr_t dma_addr) |
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56 | 56 | { |
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57 | 57 | struct bmips_dma_range *r; |
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58 | 58 | |
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.. | .. |
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64 | 64 | return dma_addr; |
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65 | 65 | } |
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66 | 66 | |
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67 | | -void arch_sync_dma_for_cpu_all(struct device *dev) |
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| 67 | +bool bmips_rac_flush_disable; |
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| 68 | + |
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| 69 | +void arch_sync_dma_for_cpu_all(void) |
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68 | 70 | { |
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69 | 71 | void __iomem *cbr = BMIPS_GET_CBR(); |
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70 | 72 | u32 cfg; |
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.. | .. |
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74 | 76 | boot_cpu_type() != CPU_BMIPS4380) |
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75 | 77 | return; |
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76 | 78 | |
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| 79 | + if (unlikely(bmips_rac_flush_disable)) |
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| 80 | + return; |
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| 81 | + |
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77 | 82 | /* Flush stale data out of the readahead cache */ |
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78 | 83 | cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); |
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79 | 84 | __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); |
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