| .. | .. |
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| 14 | 14 | #include <asm/mmu_context.h> |
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| 15 | 15 | #include <asm/page.h> |
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| 16 | 16 | |
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| 17 | +struct ia64_tr_entry { |
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| 18 | + u64 ifa; |
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| 19 | + u64 itir; |
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| 20 | + u64 pte; |
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| 21 | + u64 rr; |
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| 22 | +}; /*Record for tr entry!*/ |
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| 23 | + |
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| 24 | +extern int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size); |
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| 25 | +extern void ia64_ptr_entry(u64 target_mask, int slot); |
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| 26 | +extern struct ia64_tr_entry *ia64_idtrs[NR_CPUS]; |
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| 27 | + |
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| 28 | +/* |
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| 29 | + region register macros |
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| 30 | +*/ |
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| 31 | +#define RR_TO_VE(val) (((val) >> 0) & 0x0000000000000001) |
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| 32 | +#define RR_VE(val) (((val) & 0x0000000000000001) << 0) |
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| 33 | +#define RR_VE_MASK 0x0000000000000001L |
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| 34 | +#define RR_VE_SHIFT 0 |
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| 35 | +#define RR_TO_PS(val) (((val) >> 2) & 0x000000000000003f) |
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| 36 | +#define RR_PS(val) (((val) & 0x000000000000003f) << 2) |
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| 37 | +#define RR_PS_MASK 0x00000000000000fcL |
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| 38 | +#define RR_PS_SHIFT 2 |
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| 39 | +#define RR_RID_MASK 0x00000000ffffff00L |
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| 40 | +#define RR_TO_RID(val) ((val >> 8) & 0xffffff) |
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| 41 | + |
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| 17 | 42 | /* |
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| 18 | 43 | * Now for some TLB flushing routines. This is the kind of stuff that |
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| 19 | 44 | * can be very expensive, so try to avoid them whenever possible. |
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