.. | .. |
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8 | 8 | * VEMotherBoard.lisa |
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9 | 9 | */ |
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10 | 10 | / { |
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11 | | - smb@8000000 { |
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12 | | - motherboard { |
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| 11 | + v2m_clk24mhz: clk24mhz { |
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| 12 | + compatible = "fixed-clock"; |
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| 13 | + #clock-cells = <0>; |
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| 14 | + clock-frequency = <24000000>; |
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| 15 | + clock-output-names = "v2m:clk24mhz"; |
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| 16 | + }; |
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| 17 | + |
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| 18 | + v2m_refclk1mhz: refclk1mhz { |
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| 19 | + compatible = "fixed-clock"; |
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| 20 | + #clock-cells = <0>; |
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| 21 | + clock-frequency = <1000000>; |
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| 22 | + clock-output-names = "v2m:refclk1mhz"; |
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| 23 | + }; |
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| 24 | + |
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| 25 | + v2m_refclk32khz: refclk32khz { |
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| 26 | + compatible = "fixed-clock"; |
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| 27 | + #clock-cells = <0>; |
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| 28 | + clock-frequency = <32768>; |
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| 29 | + clock-output-names = "v2m:refclk32khz"; |
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| 30 | + }; |
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| 31 | + |
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| 32 | + v2m_fixed_3v3: v2m-3v3 { |
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| 33 | + compatible = "regulator-fixed"; |
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| 34 | + regulator-name = "3V3"; |
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| 35 | + regulator-min-microvolt = <3300000>; |
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| 36 | + regulator-max-microvolt = <3300000>; |
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| 37 | + regulator-always-on; |
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| 38 | + }; |
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| 39 | + |
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| 40 | + mcc { |
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| 41 | + compatible = "arm,vexpress,config-bus"; |
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| 42 | + arm,vexpress,config-bridge = <&v2m_sysreg>; |
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| 43 | + |
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| 44 | + v2m_oscclk1: oscclk1 { |
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| 45 | + /* CLCD clock */ |
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| 46 | + compatible = "arm,vexpress-osc"; |
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| 47 | + arm,vexpress-sysreg,func = <1 1>; |
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| 48 | + freq-range = <23750000 63500000>; |
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| 49 | + #clock-cells = <0>; |
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| 50 | + clock-output-names = "v2m:oscclk1"; |
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| 51 | + }; |
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| 52 | + |
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| 53 | + reset { |
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| 54 | + compatible = "arm,vexpress-reset"; |
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| 55 | + arm,vexpress-sysreg,func = <5 0>; |
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| 56 | + }; |
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| 57 | + |
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| 58 | + muxfpga { |
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| 59 | + compatible = "arm,vexpress-muxfpga"; |
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| 60 | + arm,vexpress-sysreg,func = <7 0>; |
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| 61 | + }; |
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| 62 | + |
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| 63 | + shutdown { |
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| 64 | + compatible = "arm,vexpress-shutdown"; |
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| 65 | + arm,vexpress-sysreg,func = <8 0>; |
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| 66 | + }; |
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| 67 | + |
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| 68 | + reboot { |
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| 69 | + compatible = "arm,vexpress-reboot"; |
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| 70 | + arm,vexpress-sysreg,func = <9 0>; |
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| 71 | + }; |
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| 72 | + |
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| 73 | + dvimode { |
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| 74 | + compatible = "arm,vexpress-dvimode"; |
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| 75 | + arm,vexpress-sysreg,func = <11 0>; |
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| 76 | + }; |
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| 77 | + }; |
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| 78 | + |
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| 79 | + bus@8000000 { |
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| 80 | + motherboard-bus { |
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13 | 81 | arm,v2m-memory-map = "rs1"; |
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14 | 82 | compatible = "arm,vexpress,v2m-p1", "simple-bus"; |
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15 | 83 | #address-cells = <2>; /* SMB chipselect number and offset */ |
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.. | .. |
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17 | 85 | #interrupt-cells = <1>; |
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18 | 86 | ranges; |
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19 | 87 | |
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20 | | - flash@0,00000000 { |
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| 88 | + flash@0 { |
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21 | 89 | compatible = "arm,vexpress-flash", "cfi-flash"; |
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22 | 90 | reg = <0 0x00000000 0x04000000>, |
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23 | 91 | <4 0x00000000 0x04000000>; |
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24 | 92 | bank-width = <4>; |
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25 | 93 | }; |
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26 | 94 | |
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27 | | - v2m_video_ram: vram@2,00000000 { |
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28 | | - compatible = "arm,vexpress-vram"; |
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29 | | - reg = <2 0x00000000 0x00800000>; |
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30 | | - }; |
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31 | | - |
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32 | | - ethernet@2,02000000 { |
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| 95 | + ethernet@202000000 { |
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33 | 96 | compatible = "smsc,lan91c111"; |
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34 | 97 | reg = <2 0x02000000 0x10000>; |
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35 | 98 | interrupts = <15>; |
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36 | 99 | }; |
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37 | 100 | |
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38 | | - v2m_clk24mhz: clk24mhz { |
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39 | | - compatible = "fixed-clock"; |
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40 | | - #clock-cells = <0>; |
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41 | | - clock-frequency = <24000000>; |
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42 | | - clock-output-names = "v2m:clk24mhz"; |
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43 | | - }; |
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44 | | - |
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45 | | - v2m_refclk1mhz: refclk1mhz { |
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46 | | - compatible = "fixed-clock"; |
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47 | | - #clock-cells = <0>; |
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48 | | - clock-frequency = <1000000>; |
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49 | | - clock-output-names = "v2m:refclk1mhz"; |
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50 | | - }; |
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51 | | - |
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52 | | - v2m_refclk32khz: refclk32khz { |
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53 | | - compatible = "fixed-clock"; |
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54 | | - #clock-cells = <0>; |
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55 | | - clock-frequency = <32768>; |
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56 | | - clock-output-names = "v2m:refclk32khz"; |
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57 | | - }; |
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58 | | - |
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59 | | - iofpga@3,00000000 { |
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| 101 | + iofpga-bus@300000000 { |
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60 | 102 | compatible = "simple-bus"; |
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61 | 103 | #address-cells = <1>; |
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62 | 104 | #size-cells = <1>; |
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.. | .. |
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91 | 133 | mmci@50000 { |
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92 | 134 | compatible = "arm,pl180", "arm,primecell"; |
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93 | 135 | reg = <0x050000 0x1000>; |
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94 | | - interrupts = <9 10>; |
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| 136 | + interrupts = <9>, <10>; |
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95 | 137 | cd-gpios = <&v2m_sysreg 0 0>; |
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96 | 138 | wp-gpios = <&v2m_sysreg 1 0>; |
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97 | 139 | max-frequency = <12000000>; |
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.. | .. |
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116 | 158 | clock-names = "KMIREFCLK", "apb_pclk"; |
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117 | 159 | }; |
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118 | 160 | |
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119 | | - v2m_serial0: uart@90000 { |
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| 161 | + v2m_serial0: serial@90000 { |
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120 | 162 | compatible = "arm,pl011", "arm,primecell"; |
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121 | 163 | reg = <0x090000 0x1000>; |
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122 | 164 | interrupts = <5>; |
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.. | .. |
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124 | 166 | clock-names = "uartclk", "apb_pclk"; |
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125 | 167 | }; |
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126 | 168 | |
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127 | | - v2m_serial1: uart@a0000 { |
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| 169 | + v2m_serial1: serial@a0000 { |
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128 | 170 | compatible = "arm,pl011", "arm,primecell"; |
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129 | 171 | reg = <0x0a0000 0x1000>; |
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130 | 172 | interrupts = <6>; |
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.. | .. |
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132 | 174 | clock-names = "uartclk", "apb_pclk"; |
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133 | 175 | }; |
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134 | 176 | |
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135 | | - v2m_serial2: uart@b0000 { |
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| 177 | + v2m_serial2: serial@b0000 { |
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136 | 178 | compatible = "arm,pl011", "arm,primecell"; |
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137 | 179 | reg = <0x0b0000 0x1000>; |
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138 | 180 | interrupts = <7>; |
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.. | .. |
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140 | 182 | clock-names = "uartclk", "apb_pclk"; |
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141 | 183 | }; |
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142 | 184 | |
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143 | | - v2m_serial3: uart@c0000 { |
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| 185 | + v2m_serial3: serial@c0000 { |
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144 | 186 | compatible = "arm,pl011", "arm,primecell"; |
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145 | 187 | reg = <0x0c0000 0x1000>; |
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146 | 188 | interrupts = <8>; |
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.. | .. |
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153 | 195 | reg = <0x0f0000 0x1000>; |
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154 | 196 | interrupts = <0>; |
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155 | 197 | clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; |
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156 | | - clock-names = "wdogclk", "apb_pclk"; |
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| 198 | + clock-names = "wdog_clk", "apb_pclk"; |
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157 | 199 | }; |
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158 | 200 | |
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159 | 201 | v2m_timer01: timer@110000 { |
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.. | .. |
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172 | 214 | clock-names = "timclken1", "timclken2", "apb_pclk"; |
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173 | 215 | }; |
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174 | 216 | |
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| 217 | + virtio-block@130000 { |
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| 218 | + compatible = "virtio,mmio"; |
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| 219 | + reg = <0x130000 0x200>; |
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| 220 | + interrupts = <42>; |
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| 221 | + }; |
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| 222 | + |
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175 | 223 | rtc@170000 { |
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176 | 224 | compatible = "arm,pl031", "arm,primecell"; |
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177 | 225 | reg = <0x170000 0x1000>; |
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.. | .. |
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187 | 235 | interrupts = <14>; |
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188 | 236 | clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; |
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189 | 237 | clock-names = "clcdclk", "apb_pclk"; |
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190 | | - arm,pl11x,framebuffer = <0x18000000 0x00180000>; |
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191 | | - memory-region = <&v2m_video_ram>; |
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192 | | - max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ |
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| 238 | + memory-region = <&vram>; |
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193 | 239 | |
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194 | 240 | port { |
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195 | | - v2m_clcd_pads: endpoint { |
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196 | | - remote-endpoint = <&v2m_clcd_panel>; |
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| 241 | + clcd_pads: endpoint { |
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| 242 | + remote-endpoint = <&panel_in>; |
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197 | 243 | arm,pl11x,tft-r0g0b0-pads = <0 8 16>; |
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198 | 244 | }; |
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199 | 245 | }; |
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200 | | - |
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201 | | - panel { |
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202 | | - compatible = "panel-dpi"; |
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203 | | - |
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204 | | - port { |
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205 | | - v2m_clcd_panel: endpoint { |
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206 | | - remote-endpoint = <&v2m_clcd_pads>; |
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207 | | - }; |
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208 | | - }; |
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209 | | - |
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210 | | - panel-timing { |
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211 | | - clock-frequency = <63500127>; |
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212 | | - hactive = <1024>; |
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213 | | - hback-porch = <152>; |
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214 | | - hfront-porch = <48>; |
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215 | | - hsync-len = <104>; |
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216 | | - vactive = <768>; |
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217 | | - vback-porch = <23>; |
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218 | | - vfront-porch = <3>; |
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219 | | - vsync-len = <4>; |
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220 | | - }; |
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221 | | - }; |
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222 | | - }; |
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223 | | - |
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224 | | - virtio-block@130000 { |
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225 | | - compatible = "virtio,mmio"; |
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226 | | - reg = <0x130000 0x200>; |
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227 | | - interrupts = <42>; |
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228 | | - }; |
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229 | | - }; |
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230 | | - |
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231 | | - v2m_fixed_3v3: v2m-3v3 { |
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232 | | - compatible = "regulator-fixed"; |
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233 | | - regulator-name = "3V3"; |
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234 | | - regulator-min-microvolt = <3300000>; |
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235 | | - regulator-max-microvolt = <3300000>; |
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236 | | - regulator-always-on; |
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237 | | - }; |
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238 | | - |
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239 | | - mcc { |
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240 | | - compatible = "arm,vexpress,config-bus"; |
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241 | | - arm,vexpress,config-bridge = <&v2m_sysreg>; |
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242 | | - |
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243 | | - v2m_oscclk1: oscclk1 { |
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244 | | - /* CLCD clock */ |
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245 | | - compatible = "arm,vexpress-osc"; |
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246 | | - arm,vexpress-sysreg,func = <1 1>; |
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247 | | - freq-range = <23750000 63500000>; |
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248 | | - #clock-cells = <0>; |
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249 | | - clock-output-names = "v2m:oscclk1"; |
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250 | | - }; |
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251 | | - |
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252 | | - reset { |
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253 | | - compatible = "arm,vexpress-reset"; |
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254 | | - arm,vexpress-sysreg,func = <5 0>; |
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255 | | - }; |
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256 | | - |
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257 | | - muxfpga { |
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258 | | - compatible = "arm,vexpress-muxfpga"; |
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259 | | - arm,vexpress-sysreg,func = <7 0>; |
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260 | | - }; |
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261 | | - |
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262 | | - shutdown { |
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263 | | - compatible = "arm,vexpress-shutdown"; |
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264 | | - arm,vexpress-sysreg,func = <8 0>; |
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265 | | - }; |
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266 | | - |
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267 | | - reboot { |
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268 | | - compatible = "arm,vexpress-reboot"; |
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269 | | - arm,vexpress-sysreg,func = <9 0>; |
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270 | | - }; |
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271 | | - |
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272 | | - dvimode { |
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273 | | - compatible = "arm,vexpress-dvimode"; |
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274 | | - arm,vexpress-sysreg,func = <11 0>; |
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275 | 246 | }; |
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276 | 247 | }; |
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277 | 248 | }; |
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