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2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da 
 kernel/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
....@@ -10,6 +10,8 @@
1010 
1111 /dts-v1/;
1212 
13
+#include <dt-bindings/interrupt-controller/arm-gic.h>
14
+
1315 /memreserve/ 0x80000000 0x00010000;
1416 
1517 #include "rtsm_ve-motherboard.dtsi"
....@@ -78,8 +80,22 @@
7880 		      <0x00000008 0x80000000 0 0x80000000>;
7981 	};
8082 
83
+	reserved-memory {
84
+		#address-cells = <2>;
85
+		#size-cells = <2>;
86
+		ranges;
87
+
88
+		/* Chipselect 2,00000000 is physically at 0x18000000 */
89
+		vram: vram@18000000 {
90
+			/* 8 MB of designated video RAM */
91
+			compatible = "shared-dma-pool";
92
+			reg = <0x00000000 0x18000000 0 0x00800000>;
93
+			no-map;
94
+		};
95
+	};
96
+
8197 	gic: interrupt-controller@2c001000 {
82
-		compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
98
+		compatible = "arm,gic-400", "arm,cortex-a15-gic";
8399 		#interrupt-cells = <3>;
84100 		#address-cells = <0>;
85101 		interrupt-controller;
....@@ -87,27 +103,36 @@
87103 		      <0x0 0x2c002000 0 0x2000>,
88104 		      <0x0 0x2c004000 0 0x2000>,
89105 		      <0x0 0x2c006000 0 0x2000>;
90
-		interrupts = <1 9 0xf04>;
106
+		interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
91107 	};
92108 
93109 	timer {
94110 		compatible = "arm,armv8-timer";
95
-		interrupts = <1 13 0xf08>,
96
-			     <1 14 0xf08>,
97
-			     <1 11 0xf08>,
98
-			     <1 10 0xf08>;
111
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
112
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
113
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
114
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
99115 		clock-frequency = <100000000>;
100116 	};
101117 
102118 	pmu {
103119 		compatible = "arm,armv8-pmuv3";
104
-		interrupts = <0 60 4>,
105
-			     <0 61 4>,
106
-			     <0 62 4>,
107
-			     <0 63 4>;
120
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
121
+			     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
122
+			     <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
123
+			     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
108124 	};
109125 
110
-	smb@8000000 {
126
+	panel {
127
+		compatible = "arm,rtsm-display";
128
+		port {
129
+			panel_in: endpoint {
130
+				remote-endpoint = <&clcd_pads>;
131
+			};
132
+		};
133
+	};
134
+
135
+	bus@8000000 {
111136 		compatible = "simple-bus";
112137 
113138 		#address-cells = <2>;
....@@ -121,48 +146,48 @@
121146 
122147 		#interrupt-cells = <1>;
123148 		interrupt-map-mask = <0 0 63>;
124
-		interrupt-map = <0 0  0 &gic 0  0 4>,
125
-				<0 0  1 &gic 0  1 4>,
126
-				<0 0  2 &gic 0  2 4>,
127
-				<0 0  3 &gic 0  3 4>,
128
-				<0 0  4 &gic 0  4 4>,
129
-				<0 0  5 &gic 0  5 4>,
130
-				<0 0  6 &gic 0  6 4>,
131
-				<0 0  7 &gic 0  7 4>,
132
-				<0 0  8 &gic 0  8 4>,
133
-				<0 0  9 &gic 0  9 4>,
134
-				<0 0 10 &gic 0 10 4>,
135
-				<0 0 11 &gic 0 11 4>,
136
-				<0 0 12 &gic 0 12 4>,
137
-				<0 0 13 &gic 0 13 4>,
138
-				<0 0 14 &gic 0 14 4>,
139
-				<0 0 15 &gic 0 15 4>,
140
-				<0 0 16 &gic 0 16 4>,
141
-				<0 0 17 &gic 0 17 4>,
142
-				<0 0 18 &gic 0 18 4>,
143
-				<0 0 19 &gic 0 19 4>,
144
-				<0 0 20 &gic 0 20 4>,
145
-				<0 0 21 &gic 0 21 4>,
146
-				<0 0 22 &gic 0 22 4>,
147
-				<0 0 23 &gic 0 23 4>,
148
-				<0 0 24 &gic 0 24 4>,
149
-				<0 0 25 &gic 0 25 4>,
150
-				<0 0 26 &gic 0 26 4>,
151
-				<0 0 27 &gic 0 27 4>,
152
-				<0 0 28 &gic 0 28 4>,
153
-				<0 0 29 &gic 0 29 4>,
154
-				<0 0 30 &gic 0 30 4>,
155
-				<0 0 31 &gic 0 31 4>,
156
-				<0 0 32 &gic 0 32 4>,
157
-				<0 0 33 &gic 0 33 4>,
158
-				<0 0 34 &gic 0 34 4>,
159
-				<0 0 35 &gic 0 35 4>,
160
-				<0 0 36 &gic 0 36 4>,
161
-				<0 0 37 &gic 0 37 4>,
162
-				<0 0 38 &gic 0 38 4>,
163
-				<0 0 39 &gic 0 39 4>,
164
-				<0 0 40 &gic 0 40 4>,
165
-				<0 0 41 &gic 0 41 4>,
166
-				<0 0 42 &gic 0 42 4>;
149
+		interrupt-map = <0 0  0 &gic GIC_SPI  0 IRQ_TYPE_LEVEL_HIGH>,
150
+				<0 0  1 &gic GIC_SPI  1 IRQ_TYPE_LEVEL_HIGH>,
151
+				<0 0  2 &gic GIC_SPI  2 IRQ_TYPE_LEVEL_HIGH>,
152
+				<0 0  3 &gic GIC_SPI  3 IRQ_TYPE_LEVEL_HIGH>,
153
+				<0 0  4 &gic GIC_SPI  4 IRQ_TYPE_LEVEL_HIGH>,
154
+				<0 0  5 &gic GIC_SPI  5 IRQ_TYPE_LEVEL_HIGH>,
155
+				<0 0  6 &gic GIC_SPI  6 IRQ_TYPE_LEVEL_HIGH>,
156
+				<0 0  7 &gic GIC_SPI  7 IRQ_TYPE_LEVEL_HIGH>,
157
+				<0 0  8 &gic GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
158
+				<0 0  9 &gic GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
159
+				<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
160
+				<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
161
+				<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
162
+				<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163
+				<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
164
+				<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
165
+				<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
166
+				<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
167
+				<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
168
+				<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
169
+				<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
170
+				<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
171
+				<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
172
+				<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
173
+				<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
174
+				<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
175
+				<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
176
+				<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
177
+				<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
178
+				<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
179
+				<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
180
+				<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
181
+				<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
182
+				<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
183
+				<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
184
+				<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
185
+				<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
186
+				<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
187
+				<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
188
+				<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
189
+				<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
190
+				<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
191
+				<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
167192 	};
168193 };