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| 1 | +/* SPDX-License-Identifier: GPL-2.0-only */ |
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1 | 2 | /* |
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2 | 3 | * arch/arm/include/asm/cacheflush.h |
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3 | 4 | * |
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4 | 5 | * Copyright (C) 1999-2002 Russell King |
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5 | | - * |
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6 | | - * This program is free software; you can redistribute it and/or modify |
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7 | | - * it under the terms of the GNU General Public License version 2 as |
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8 | | - * published by the Free Software Foundation. |
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9 | 6 | */ |
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10 | 7 | #ifndef _ASMARM_CACHEFLUSH_H |
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11 | 8 | #define _ASMARM_CACHEFLUSH_H |
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.. | .. |
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261 | 258 | #define flush_cache_dup_mm(mm) flush_cache_mm(mm) |
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262 | 259 | |
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263 | 260 | /* |
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264 | | - * flush_cache_user_range is used when we want to ensure that the |
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| 261 | + * flush_icache_user_range is used when we want to ensure that the |
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265 | 262 | * Harvard caches are synchronised for the user space address range. |
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266 | 263 | * This is used for the ARM private sys_cacheflush system call. |
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267 | 264 | */ |
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268 | | -#define flush_cache_user_range(s,e) __cpuc_coherent_user_range(s,e) |
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| 265 | +#define flush_icache_user_range(s,e) __cpuc_coherent_user_range(s,e) |
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269 | 266 | |
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270 | 267 | /* |
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271 | 268 | * Perform necessary cache operations to ensure that data previously |
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.. | .. |
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320 | 317 | |
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321 | 318 | #define flush_dcache_mmap_lock(mapping) xa_lock_irq(&mapping->i_pages) |
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322 | 319 | #define flush_dcache_mmap_unlock(mapping) xa_unlock_irq(&mapping->i_pages) |
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323 | | - |
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324 | | -#define flush_icache_user_range(vma,page,addr,len) \ |
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325 | | - flush_dcache_page(page) |
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326 | 320 | |
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327 | 321 | /* |
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328 | 322 | * We don't appear to need to do anything here. In fact, if we did, we'd |
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.. | .. |
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479 | 473 | void flush_uprobe_xol_access(struct page *page, unsigned long uaddr, |
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480 | 474 | void *kaddr, unsigned long len); |
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481 | 475 | |
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| 476 | + |
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| 477 | +#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND |
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| 478 | +void check_cpu_icache_size(int cpuid); |
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| 479 | +#else |
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| 480 | +static inline void check_cpu_icache_size(int cpuid) { } |
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| 481 | +#endif |
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| 482 | + |
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482 | 483 | #endif |
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