.. | .. |
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7 | 7 | #include <dt-bindings/reset/imx7-reset.h> |
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8 | 8 | |
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9 | 9 | / { |
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| 10 | + aliases { |
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| 11 | + usb0 = &usbotg1; |
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| 12 | + usb1 = &usbotg2; |
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| 13 | + usb2 = &usbh; |
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| 14 | + }; |
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| 15 | + |
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10 | 16 | cpus { |
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11 | 17 | cpu0: cpu@0 { |
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12 | 18 | clock-frequency = <996000000>; |
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13 | 19 | operating-points-v2 = <&cpu0_opp_table>; |
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14 | 20 | #cooling-cells = <2>; |
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| 21 | + nvmem-cells = <&fuse_grade>; |
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| 22 | + nvmem-cell-names = "speed_grade"; |
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15 | 23 | }; |
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16 | 24 | |
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17 | 25 | cpu1: cpu@1 { |
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.. | .. |
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20 | 28 | reg = <1>; |
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21 | 29 | clock-frequency = <996000000>; |
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22 | 30 | operating-points-v2 = <&cpu0_opp_table>; |
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| 31 | + #cooling-cells = <2>; |
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| 32 | + cpu-idle-states = <&cpu_sleep_wait>; |
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23 | 33 | }; |
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| 34 | + }; |
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| 35 | + |
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| 36 | + timer { |
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| 37 | + compatible = "arm,armv7-timer"; |
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| 38 | + interrupt-parent = <&intc>; |
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| 39 | + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
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| 40 | + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
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| 41 | + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
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| 42 | + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; |
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24 | 43 | }; |
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25 | 44 | |
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26 | 45 | cpu0_opp_table: opp-table { |
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.. | .. |
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29 | 48 | |
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30 | 49 | opp-792000000 { |
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31 | 50 | opp-hz = /bits/ 64 <792000000>; |
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32 | | - opp-microvolt = <975000>; |
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| 51 | + opp-microvolt = <1000000>; |
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33 | 52 | clock-latency-ns = <150000>; |
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| 53 | + opp-supported-hw = <0xd>, <0x7>; |
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| 54 | + opp-suspend; |
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34 | 55 | }; |
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35 | 56 | |
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36 | 57 | opp-996000000 { |
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37 | 58 | opp-hz = /bits/ 64 <996000000>; |
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38 | | - opp-microvolt = <1075000>; |
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| 59 | + opp-microvolt = <1100000>; |
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39 | 60 | clock-latency-ns = <150000>; |
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| 61 | + opp-supported-hw = <0xc>, <0x7>; |
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| 62 | + opp-suspend; |
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| 63 | + }; |
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| 64 | + |
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| 65 | + opp-1200000000 { |
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| 66 | + opp-hz = /bits/ 64 <1200000000>; |
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| 67 | + opp-microvolt = <1225000>; |
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| 68 | + clock-latency-ns = <150000>; |
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| 69 | + opp-supported-hw = <0x8>, <0x3>; |
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40 | 70 | opp-suspend; |
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41 | 71 | }; |
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42 | 72 | }; |
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.. | .. |
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63 | 93 | clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; |
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64 | 94 | clock-names = "apb_pclk"; |
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65 | 95 | |
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66 | | - port { |
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67 | | - etm1_out_port: endpoint { |
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68 | | - remote-endpoint = <&ca_funnel_in_port1>; |
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| 96 | + out-ports { |
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| 97 | + port { |
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| 98 | + etm1_out_port: endpoint { |
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| 99 | + remote-endpoint = <&ca_funnel_in_port1>; |
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| 100 | + }; |
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69 | 101 | }; |
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70 | 102 | }; |
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71 | 103 | }; |
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| 104 | + |
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| 105 | + intc: interrupt-controller@31001000 { |
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| 106 | + compatible = "arm,cortex-a7-gic"; |
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| 107 | + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
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| 108 | + #interrupt-cells = <3>; |
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| 109 | + interrupt-controller; |
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| 110 | + interrupt-parent = <&intc>; |
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| 111 | + reg = <0x31001000 0x1000>, |
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| 112 | + <0x31002000 0x2000>, |
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| 113 | + <0x31004000 0x2000>, |
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| 114 | + <0x31006000 0x2000>; |
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| 115 | + }; |
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| 116 | + }; |
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| 117 | +}; |
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| 118 | + |
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| 119 | +&aips2 { |
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| 120 | + pcie_phy: pcie-phy@306d0000 { |
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| 121 | + compatible = "fsl,imx7d-pcie-phy"; |
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| 122 | + reg = <0x306d0000 0x10000>; |
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| 123 | + status = "disabled"; |
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72 | 124 | }; |
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73 | 125 | }; |
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74 | 126 | |
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.. | .. |
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105 | 157 | <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; |
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106 | 158 | clock-names = "ipg", "ahb", "ptp", |
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107 | 159 | "enet_clk_ref", "enet_out"; |
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108 | | - fsl,num-tx-queues=<3>; |
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109 | | - fsl,num-rx-queues=<3>; |
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| 160 | + fsl,num-tx-queues = <3>; |
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| 161 | + fsl,num-rx-queues = <3>; |
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| 162 | + fsl,stop-mode = <&gpr 0x10 4>; |
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110 | 163 | status = "disabled"; |
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111 | 164 | }; |
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112 | 165 | |
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.. | .. |
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122 | 175 | ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ |
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123 | 176 | 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ |
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124 | 177 | num-lanes = <1>; |
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| 178 | + num-viewport = <4>; |
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125 | 179 | interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
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126 | 180 | interrupt-names = "msi"; |
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127 | 181 | #interrupt-cells = <1>; |
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.. | .. |
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146 | 200 | fsl,max-link-speed = <2>; |
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147 | 201 | power-domains = <&pgc_pcie_phy>; |
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148 | 202 | resets = <&src IMX7_RESET_PCIEPHY>, |
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149 | | - <&src IMX7_RESET_PCIE_CTRL_APPS_EN>; |
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150 | | - reset-names = "pciephy", "apps"; |
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| 203 | + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, |
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| 204 | + <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; |
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| 205 | + reset-names = "pciephy", "apps", "turnoff"; |
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| 206 | + fsl,imx7d-pcie-phy = <&pcie_phy>; |
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151 | 207 | status = "disabled"; |
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152 | 208 | }; |
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153 | 209 | }; |
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154 | 210 | |
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155 | | -&ca_funnel_ports { |
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| 211 | +&ca_funnel_in_ports { |
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| 212 | + #address-cells = <1>; |
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| 213 | + #size-cells = <0>; |
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| 214 | + |
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156 | 215 | port@1 { |
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157 | 216 | reg = <1>; |
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158 | 217 | ca_funnel_in_port1: endpoint { |
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159 | | - slave-mode; |
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160 | 218 | remote-endpoint = <&etm1_out_port>; |
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161 | 219 | }; |
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162 | 220 | }; |
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