hc
2024-12-19 9370bb92b2d16684ee45cf24e879c93c509162da
kernel/arch/arm/boot/dts/armada-38x.dtsi
....@@ -9,13 +9,15 @@
99 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
1010 */
1111
12
-#include "skeleton.dtsi"
1312 #include <dt-bindings/interrupt-controller/arm-gic.h>
1413 #include <dt-bindings/interrupt-controller/irq.h>
1514
1615 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
1716
1817 / {
18
+ #address-cells = <1>;
19
+ #size-cells = <1>;
20
+
1921 model = "Marvell Armada 38x family SoC";
2022 compatible = "marvell,armada380";
2123
....@@ -101,6 +103,11 @@
101103 #size-cells = <1>;
102104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
103105
106
+ sdramc: sdramc@1400 {
107
+ compatible = "marvell,armada-xp-sdram-controller";
108
+ reg = <0x1400 0x500>;
109
+ };
110
+
104111 L2: cache-controller@8000 {
105112 compatible = "arm,pl310-cache";
106113 reg = <0x8000 0x1000>;
....@@ -146,7 +153,6 @@
146153 #address-cells = <1>;
147154 #size-cells = <0>;
148155 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
149
- timeout-ms = <1000>;
150156 clocks = <&coreclk 0>;
151157 status = "disabled";
152158 };
....@@ -157,7 +163,6 @@
157163 #address-cells = <1>;
158164 #size-cells = <0>;
159165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
160
- timeout-ms = <1000>;
161166 clocks = <&coreclk 0>;
162167 status = "disabled";
163168 };
....@@ -335,6 +340,44 @@
335340 #clock-cells = <1>;
336341 };
337342
343
+ comphy: phy@18300 {
344
+ compatible = "marvell,armada-380-comphy";
345
+ reg-names = "comphy", "conf";
346
+ reg = <0x18300 0x100>, <0x18460 4>;
347
+ #address-cells = <1>;
348
+ #size-cells = <0>;
349
+
350
+ comphy0: phy@0 {
351
+ reg = <0>;
352
+ #phy-cells = <1>;
353
+ };
354
+
355
+ comphy1: phy@1 {
356
+ reg = <1>;
357
+ #phy-cells = <1>;
358
+ };
359
+
360
+ comphy2: phy@2 {
361
+ reg = <2>;
362
+ #phy-cells = <1>;
363
+ };
364
+
365
+ comphy3: phy@3 {
366
+ reg = <3>;
367
+ #phy-cells = <1>;
368
+ };
369
+
370
+ comphy4: phy@4 {
371
+ reg = <4>;
372
+ #phy-cells = <1>;
373
+ };
374
+
375
+ comphy5: phy@5 {
376
+ reg = <5>;
377
+ #phy-cells = <1>;
378
+ };
379
+ };
380
+
338381 coreclk: mvebu-sar@18600 {
339382 compatible = "marvell,armada-380-core-clock";
340383 reg = <0x18600 0x04>;
....@@ -376,6 +419,8 @@
376419 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
377420 clocks = <&coreclk 2>, <&refclk>;
378421 clock-names = "nbclk", "fixed";
422
+ interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
423
+ <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
379424 };
380425
381426 cpurst: cpurst@20800 {