.. | .. |
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9 | 9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> |
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10 | 10 | */ |
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11 | 11 | |
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12 | | -#include "skeleton.dtsi" |
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13 | 12 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
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14 | 13 | #include <dt-bindings/interrupt-controller/irq.h> |
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15 | 14 | |
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16 | 15 | #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) |
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17 | 16 | |
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18 | 17 | / { |
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| 18 | + #address-cells = <1>; |
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| 19 | + #size-cells = <1>; |
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| 20 | + |
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19 | 21 | model = "Marvell Armada 38x family SoC"; |
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20 | 22 | compatible = "marvell,armada380"; |
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21 | 23 | |
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.. | .. |
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101 | 103 | #size-cells = <1>; |
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102 | 104 | ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>; |
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103 | 105 | |
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| 106 | + sdramc: sdramc@1400 { |
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| 107 | + compatible = "marvell,armada-xp-sdram-controller"; |
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| 108 | + reg = <0x1400 0x500>; |
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| 109 | + }; |
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| 110 | + |
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104 | 111 | L2: cache-controller@8000 { |
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105 | 112 | compatible = "arm,pl310-cache"; |
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106 | 113 | reg = <0x8000 0x1000>; |
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.. | .. |
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146 | 153 | #address-cells = <1>; |
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147 | 154 | #size-cells = <0>; |
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148 | 155 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
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149 | | - timeout-ms = <1000>; |
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150 | 156 | clocks = <&coreclk 0>; |
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151 | 157 | status = "disabled"; |
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152 | 158 | }; |
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.. | .. |
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157 | 163 | #address-cells = <1>; |
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158 | 164 | #size-cells = <0>; |
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159 | 165 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
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160 | | - timeout-ms = <1000>; |
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161 | 166 | clocks = <&coreclk 0>; |
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162 | 167 | status = "disabled"; |
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163 | 168 | }; |
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.. | .. |
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335 | 340 | #clock-cells = <1>; |
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336 | 341 | }; |
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337 | 342 | |
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| 343 | + comphy: phy@18300 { |
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| 344 | + compatible = "marvell,armada-380-comphy"; |
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| 345 | + reg-names = "comphy", "conf"; |
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| 346 | + reg = <0x18300 0x100>, <0x18460 4>; |
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| 347 | + #address-cells = <1>; |
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| 348 | + #size-cells = <0>; |
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| 349 | + |
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| 350 | + comphy0: phy@0 { |
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| 351 | + reg = <0>; |
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| 352 | + #phy-cells = <1>; |
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| 353 | + }; |
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| 354 | + |
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| 355 | + comphy1: phy@1 { |
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| 356 | + reg = <1>; |
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| 357 | + #phy-cells = <1>; |
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| 358 | + }; |
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| 359 | + |
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| 360 | + comphy2: phy@2 { |
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| 361 | + reg = <2>; |
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| 362 | + #phy-cells = <1>; |
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| 363 | + }; |
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| 364 | + |
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| 365 | + comphy3: phy@3 { |
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| 366 | + reg = <3>; |
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| 367 | + #phy-cells = <1>; |
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| 368 | + }; |
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| 369 | + |
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| 370 | + comphy4: phy@4 { |
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| 371 | + reg = <4>; |
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| 372 | + #phy-cells = <1>; |
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| 373 | + }; |
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| 374 | + |
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| 375 | + comphy5: phy@5 { |
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| 376 | + reg = <5>; |
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| 377 | + #phy-cells = <1>; |
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| 378 | + }; |
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| 379 | + }; |
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| 380 | + |
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338 | 381 | coreclk: mvebu-sar@18600 { |
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339 | 382 | compatible = "marvell,armada-380-core-clock"; |
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340 | 383 | reg = <0x18600 0x04>; |
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.. | .. |
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376 | 419 | reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>; |
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377 | 420 | clocks = <&coreclk 2>, <&refclk>; |
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378 | 421 | clock-names = "nbclk", "fixed"; |
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| 422 | + interrupts-extended = <&gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, |
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| 423 | + <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
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379 | 424 | }; |
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380 | 425 | |
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381 | 426 | cpurst: cpurst@20800 { |
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