| .. | .. |
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| 54 | 54 | Contact: Linux Memory Management list <linux-mm@kvack.org> |
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| 55 | 55 | Description: |
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| 56 | 56 | Provides information about the node's distribution and memory |
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| 57 | | - utilization. Similar to /proc/meminfo, see Documentation/filesystems/proc.txt |
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| 57 | + utilization. Similar to /proc/meminfo, see Documentation/filesystems/proc.rst |
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| 58 | 58 | |
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| 59 | 59 | What: /sys/devices/system/node/nodeX/numastat |
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| 60 | 60 | Date: October 2002 |
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| 61 | 61 | Contact: Linux Memory Management list <linux-mm@kvack.org> |
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| 62 | 62 | Description: |
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| 63 | 63 | The node's hit/miss statistics, in units of pages. |
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| 64 | | - See Documentation/numastat.txt |
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| 64 | + See Documentation/admin-guide/numastat.rst |
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| 65 | 65 | |
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| 66 | 66 | What: /sys/devices/system/node/nodeX/distance |
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| 67 | 67 | Date: October 2002 |
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| .. | .. |
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| 90 | 90 | Contact: Lee Schermerhorn <lee.schermerhorn@hp.com> |
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| 91 | 91 | Description: |
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| 92 | 92 | The node's huge page size control/query attributes. |
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| 93 | | - See Documentation/admin-guide/mm/hugetlbpage.rst |
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| 93 | + See Documentation/admin-guide/mm/hugetlbpage.rst |
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| 94 | + |
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| 95 | +What: /sys/devices/system/node/nodeX/accessY/ |
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| 96 | +Date: December 2018 |
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| 97 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 98 | +Description: |
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| 99 | + The node's relationship to other nodes for access class "Y". |
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| 100 | + |
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| 101 | +What: /sys/devices/system/node/nodeX/accessY/initiators/ |
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| 102 | +Date: December 2018 |
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| 103 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 104 | +Description: |
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| 105 | + The directory containing symlinks to memory initiator |
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| 106 | + nodes that have class "Y" access to this target node's |
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| 107 | + memory. CPUs and other memory initiators in nodes not in |
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| 108 | + the list accessing this node's memory may have different |
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| 109 | + performance. |
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| 110 | + |
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| 111 | +What: /sys/devices/system/node/nodeX/accessY/targets/ |
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| 112 | +Date: December 2018 |
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| 113 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 114 | +Description: |
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| 115 | + The directory containing symlinks to memory targets that |
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| 116 | + this initiator node has class "Y" access. |
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| 117 | + |
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| 118 | +What: /sys/devices/system/node/nodeX/accessY/initiators/read_bandwidth |
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| 119 | +Date: December 2018 |
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| 120 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 121 | +Description: |
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| 122 | + This node's read bandwidth in MB/s when accessed from |
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| 123 | + nodes found in this access class's linked initiators. |
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| 124 | + |
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| 125 | +What: /sys/devices/system/node/nodeX/accessY/initiators/read_latency |
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| 126 | +Date: December 2018 |
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| 127 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 128 | +Description: |
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| 129 | + This node's read latency in nanoseconds when accessed |
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| 130 | + from nodes found in this access class's linked initiators. |
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| 131 | + |
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| 132 | +What: /sys/devices/system/node/nodeX/accessY/initiators/write_bandwidth |
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| 133 | +Date: December 2018 |
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| 134 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 135 | +Description: |
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| 136 | + This node's write bandwidth in MB/s when accessed from |
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| 137 | + found in this access class's linked initiators. |
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| 138 | + |
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| 139 | +What: /sys/devices/system/node/nodeX/accessY/initiators/write_latency |
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| 140 | +Date: December 2018 |
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| 141 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 142 | +Description: |
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| 143 | + This node's write latency in nanoseconds when access |
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| 144 | + from nodes found in this class's linked initiators. |
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| 145 | + |
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| 146 | +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/ |
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| 147 | +Date: December 2018 |
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| 148 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 149 | +Description: |
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| 150 | + The directory containing attributes for the memory-side cache |
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| 151 | + level 'Y'. |
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| 152 | + |
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| 153 | +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/indexing |
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| 154 | +Date: December 2018 |
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| 155 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 156 | +Description: |
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| 157 | + The caches associativity indexing: 0 for direct mapped, |
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| 158 | + non-zero if indexed. |
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| 159 | + |
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| 160 | +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/line_size |
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| 161 | +Date: December 2018 |
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| 162 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 163 | +Description: |
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| 164 | + The number of bytes accessed from the next cache level on a |
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| 165 | + cache miss. |
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| 166 | + |
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| 167 | +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/size |
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| 168 | +Date: December 2018 |
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| 169 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 170 | +Description: |
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| 171 | + The size of this memory side cache in bytes. |
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| 172 | + |
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| 173 | +What: /sys/devices/system/node/nodeX/memory_side_cache/indexY/write_policy |
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| 174 | +Date: December 2018 |
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| 175 | +Contact: Keith Busch <keith.busch@intel.com> |
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| 176 | +Description: |
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| 177 | + The cache write policy: 0 for write-back, 1 for write-through, |
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| 178 | + other or unknown. |
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