.. | .. |
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| 1 | +// SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | /* |
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2 | 3 | * dice_stream.c - a part of driver for DICE based devices |
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3 | 4 | * |
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4 | 5 | * Copyright (c) Clemens Ladisch <clemens@ladisch.de> |
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5 | 6 | * Copyright (c) 2014 Takashi Sakamoto <o-takashi@sakamocchi.jp> |
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6 | | - * |
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7 | | - * Licensed under the terms of the GNU General Public License, version 2. |
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8 | 7 | */ |
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9 | 8 | |
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10 | 9 | #include "dice.h" |
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.. | .. |
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138 | 137 | |
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139 | 138 | static void release_resources(struct snd_dice *dice) |
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140 | 139 | { |
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141 | | - unsigned int i; |
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| 140 | + int i; |
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142 | 141 | |
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143 | | - for (i = 0; i < MAX_STREAMS; i++) { |
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144 | | - if (amdtp_stream_running(&dice->tx_stream[i])) { |
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145 | | - amdtp_stream_pcm_abort(&dice->tx_stream[i]); |
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146 | | - amdtp_stream_stop(&dice->tx_stream[i]); |
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147 | | - } |
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148 | | - if (amdtp_stream_running(&dice->rx_stream[i])) { |
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149 | | - amdtp_stream_pcm_abort(&dice->rx_stream[i]); |
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150 | | - amdtp_stream_stop(&dice->rx_stream[i]); |
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151 | | - } |
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152 | | - |
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| 142 | + for (i = 0; i < MAX_STREAMS; ++i) { |
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153 | 143 | fw_iso_resources_free(&dice->tx_resources[i]); |
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154 | 144 | fw_iso_resources_free(&dice->rx_resources[i]); |
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155 | 145 | } |
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.. | .. |
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175 | 165 | } |
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176 | 166 | } |
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177 | 167 | |
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178 | | -static int keep_resources(struct snd_dice *dice, |
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179 | | - enum amdtp_stream_direction dir, unsigned int index, |
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180 | | - unsigned int rate, unsigned int pcm_chs, |
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181 | | - unsigned int midi_ports) |
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| 168 | +static int keep_resources(struct snd_dice *dice, struct amdtp_stream *stream, |
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| 169 | + struct fw_iso_resources *resources, unsigned int rate, |
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| 170 | + unsigned int pcm_chs, unsigned int midi_ports) |
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182 | 171 | { |
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183 | | - struct amdtp_stream *stream; |
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184 | | - struct fw_iso_resources *resources; |
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185 | 172 | bool double_pcm_frames; |
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186 | 173 | unsigned int i; |
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187 | 174 | int err; |
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188 | 175 | |
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189 | | - if (dir == AMDTP_IN_STREAM) { |
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190 | | - stream = &dice->tx_stream[index]; |
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191 | | - resources = &dice->tx_resources[index]; |
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192 | | - } else { |
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193 | | - stream = &dice->rx_stream[index]; |
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194 | | - resources = &dice->rx_resources[index]; |
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195 | | - } |
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196 | | - |
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197 | | - /* |
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198 | | - * At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in |
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199 | | - * one data block of AMDTP packet. Thus sampling transfer frequency is |
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200 | | - * a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are |
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201 | | - * transferred on AMDTP packets at 96 kHz. Two successive samples of a |
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202 | | - * channel are stored consecutively in the packet. This quirk is called |
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203 | | - * as 'Dual Wire'. |
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204 | | - * For this quirk, blocking mode is required and PCM buffer size should |
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205 | | - * be aligned to SYT_INTERVAL. |
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206 | | - */ |
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| 176 | + // At 176.4/192.0 kHz, Dice has a quirk to transfer two PCM frames in |
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| 177 | + // one data block of AMDTP packet. Thus sampling transfer frequency is |
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| 178 | + // a half of PCM sampling frequency, i.e. PCM frames at 192.0 kHz are |
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| 179 | + // transferred on AMDTP packets at 96 kHz. Two successive samples of a |
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| 180 | + // channel are stored consecutively in the packet. This quirk is called |
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| 181 | + // as 'Dual Wire'. |
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| 182 | + // For this quirk, blocking mode is required and PCM buffer size should |
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| 183 | + // be aligned to SYT_INTERVAL. |
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207 | 184 | double_pcm_frames = rate > 96000; |
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208 | 185 | if (double_pcm_frames) { |
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209 | 186 | rate /= 2; |
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.. | .. |
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230 | 207 | fw_parent_device(dice->unit)->max_speed); |
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231 | 208 | } |
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232 | 209 | |
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233 | | -static int start_streams(struct snd_dice *dice, enum amdtp_stream_direction dir, |
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234 | | - unsigned int rate, struct reg_params *params) |
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| 210 | +static int keep_dual_resources(struct snd_dice *dice, unsigned int rate, |
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| 211 | + enum amdtp_stream_direction dir, |
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| 212 | + struct reg_params *params) |
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235 | 213 | { |
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236 | | - __be32 reg[2]; |
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237 | 214 | enum snd_dice_rate_mode mode; |
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238 | | - unsigned int i, pcm_chs, midi_ports; |
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239 | | - struct amdtp_stream *streams; |
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240 | | - struct fw_iso_resources *resources; |
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241 | | - struct fw_device *fw_dev = fw_parent_device(dice->unit); |
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242 | | - int err = 0; |
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243 | | - |
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244 | | - if (dir == AMDTP_IN_STREAM) { |
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245 | | - streams = dice->tx_stream; |
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246 | | - resources = dice->tx_resources; |
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247 | | - } else { |
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248 | | - streams = dice->rx_stream; |
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249 | | - resources = dice->rx_resources; |
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250 | | - } |
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| 215 | + int i; |
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| 216 | + int err; |
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251 | 217 | |
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252 | 218 | err = snd_dice_stream_get_rate_mode(dice, rate, &mode); |
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253 | 219 | if (err < 0) |
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254 | 220 | return err; |
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255 | 221 | |
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256 | | - for (i = 0; i < params->count; i++) { |
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| 222 | + for (i = 0; i < params->count; ++i) { |
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| 223 | + __be32 reg[2]; |
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| 224 | + struct amdtp_stream *stream; |
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| 225 | + struct fw_iso_resources *resources; |
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257 | 226 | unsigned int pcm_cache; |
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258 | | - unsigned int midi_cache; |
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| 227 | + unsigned int pcm_chs; |
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| 228 | + unsigned int midi_ports; |
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259 | 229 | |
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260 | 230 | if (dir == AMDTP_IN_STREAM) { |
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| 231 | + stream = &dice->tx_stream[i]; |
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| 232 | + resources = &dice->tx_resources[i]; |
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| 233 | + |
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261 | 234 | pcm_cache = dice->tx_pcm_chs[i][mode]; |
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262 | | - midi_cache = dice->tx_midi_ports[i]; |
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263 | 235 | err = snd_dice_transaction_read_tx(dice, |
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264 | 236 | params->size * i + TX_NUMBER_AUDIO, |
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265 | 237 | reg, sizeof(reg)); |
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266 | 238 | } else { |
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| 239 | + stream = &dice->rx_stream[i]; |
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| 240 | + resources = &dice->rx_resources[i]; |
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| 241 | + |
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267 | 242 | pcm_cache = dice->rx_pcm_chs[i][mode]; |
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268 | | - midi_cache = dice->rx_midi_ports[i]; |
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269 | 243 | err = snd_dice_transaction_read_rx(dice, |
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270 | 244 | params->size * i + RX_NUMBER_AUDIO, |
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271 | 245 | reg, sizeof(reg)); |
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.. | .. |
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275 | 249 | pcm_chs = be32_to_cpu(reg[0]); |
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276 | 250 | midi_ports = be32_to_cpu(reg[1]); |
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277 | 251 | |
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278 | | - /* These are important for developer of this driver. */ |
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279 | | - if (pcm_chs != pcm_cache || midi_ports != midi_cache) { |
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| 252 | + // These are important for developer of this driver. |
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| 253 | + if (pcm_chs != pcm_cache) { |
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280 | 254 | dev_info(&dice->unit->device, |
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281 | | - "cache mismatch: pcm: %u:%u, midi: %u:%u\n", |
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282 | | - pcm_chs, pcm_cache, midi_ports, midi_cache); |
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| 255 | + "cache mismatch: pcm: %u:%u, midi: %u\n", |
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| 256 | + pcm_chs, pcm_cache, midi_ports); |
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283 | 257 | return -EPROTO; |
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284 | 258 | } |
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285 | 259 | |
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286 | | - err = keep_resources(dice, dir, i, rate, pcm_chs, midi_ports); |
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287 | | - if (err < 0) |
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288 | | - return err; |
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289 | | - |
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290 | | - reg[0] = cpu_to_be32(resources[i].channel); |
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291 | | - if (dir == AMDTP_IN_STREAM) { |
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292 | | - err = snd_dice_transaction_write_tx(dice, |
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293 | | - params->size * i + TX_ISOCHRONOUS, |
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294 | | - reg, sizeof(reg[0])); |
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295 | | - } else { |
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296 | | - err = snd_dice_transaction_write_rx(dice, |
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297 | | - params->size * i + RX_ISOCHRONOUS, |
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298 | | - reg, sizeof(reg[0])); |
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299 | | - } |
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300 | | - if (err < 0) |
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301 | | - return err; |
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302 | | - |
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303 | | - if (dir == AMDTP_IN_STREAM) { |
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304 | | - reg[0] = cpu_to_be32(fw_dev->max_speed); |
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305 | | - err = snd_dice_transaction_write_tx(dice, |
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306 | | - params->size * i + TX_SPEED, |
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307 | | - reg, sizeof(reg[0])); |
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308 | | - if (err < 0) |
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309 | | - return err; |
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310 | | - } |
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311 | | - |
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312 | | - err = amdtp_stream_start(&streams[i], resources[i].channel, |
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313 | | - fw_dev->max_speed); |
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| 260 | + err = keep_resources(dice, stream, resources, rate, pcm_chs, |
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| 261 | + midi_ports); |
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314 | 262 | if (err < 0) |
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315 | 263 | return err; |
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316 | 264 | } |
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317 | 265 | |
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318 | | - return err; |
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| 266 | + return 0; |
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319 | 267 | } |
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320 | 268 | |
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321 | | -static int start_duplex_streams(struct snd_dice *dice, unsigned int rate) |
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| 269 | +static void finish_session(struct snd_dice *dice, struct reg_params *tx_params, |
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| 270 | + struct reg_params *rx_params) |
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322 | 271 | { |
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323 | | - struct reg_params tx_params, rx_params; |
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324 | | - int i; |
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| 272 | + stop_streams(dice, AMDTP_IN_STREAM, tx_params); |
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| 273 | + stop_streams(dice, AMDTP_OUT_STREAM, rx_params); |
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| 274 | + |
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| 275 | + snd_dice_transaction_clear_enable(dice); |
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| 276 | +} |
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| 277 | + |
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| 278 | +int snd_dice_stream_reserve_duplex(struct snd_dice *dice, unsigned int rate, |
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| 279 | + unsigned int events_per_period, |
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| 280 | + unsigned int events_per_buffer) |
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| 281 | +{ |
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| 282 | + unsigned int curr_rate; |
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325 | 283 | int err; |
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326 | 284 | |
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327 | | - err = get_register_params(dice, &tx_params, &rx_params); |
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| 285 | + // Check sampling transmission frequency. |
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| 286 | + err = snd_dice_transaction_get_rate(dice, &curr_rate); |
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328 | 287 | if (err < 0) |
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329 | 288 | return err; |
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| 289 | + if (rate == 0) |
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| 290 | + rate = curr_rate; |
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330 | 291 | |
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331 | | - /* Stop transmission. */ |
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332 | | - stop_streams(dice, AMDTP_IN_STREAM, &tx_params); |
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333 | | - stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); |
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334 | | - snd_dice_transaction_clear_enable(dice); |
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335 | | - release_resources(dice); |
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| 292 | + if (dice->substreams_counter == 0 || curr_rate != rate) { |
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| 293 | + struct reg_params tx_params, rx_params; |
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336 | 294 | |
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337 | | - err = ensure_phase_lock(dice, rate); |
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338 | | - if (err < 0) { |
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339 | | - dev_err(&dice->unit->device, "fail to ensure phase lock\n"); |
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340 | | - return err; |
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341 | | - } |
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| 295 | + amdtp_domain_stop(&dice->domain); |
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342 | 296 | |
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343 | | - /* Likely to have changed stream formats. */ |
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344 | | - err = get_register_params(dice, &tx_params, &rx_params); |
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345 | | - if (err < 0) |
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346 | | - return err; |
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| 297 | + err = get_register_params(dice, &tx_params, &rx_params); |
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| 298 | + if (err < 0) |
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| 299 | + return err; |
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| 300 | + finish_session(dice, &tx_params, &rx_params); |
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347 | 301 | |
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348 | | - /* Start both streams. */ |
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349 | | - err = start_streams(dice, AMDTP_IN_STREAM, rate, &tx_params); |
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350 | | - if (err < 0) |
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351 | | - goto error; |
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352 | | - err = start_streams(dice, AMDTP_OUT_STREAM, rate, &rx_params); |
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353 | | - if (err < 0) |
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354 | | - goto error; |
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| 302 | + release_resources(dice); |
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355 | 303 | |
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356 | | - err = snd_dice_transaction_set_enable(dice); |
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357 | | - if (err < 0) { |
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358 | | - dev_err(&dice->unit->device, "fail to enable interface\n"); |
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359 | | - goto error; |
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360 | | - } |
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| 304 | + // Just after owning the unit (GLOBAL_OWNER), the unit can |
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| 305 | + // return invalid stream formats. Selecting clock parameters |
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| 306 | + // have an effect for the unit to refine it. |
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| 307 | + err = ensure_phase_lock(dice, rate); |
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| 308 | + if (err < 0) |
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| 309 | + return err; |
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361 | 310 | |
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362 | | - for (i = 0; i < MAX_STREAMS; i++) { |
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363 | | - if ((i < tx_params.count && |
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364 | | - !amdtp_stream_wait_callback(&dice->tx_stream[i], |
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365 | | - CALLBACK_TIMEOUT)) || |
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366 | | - (i < rx_params.count && |
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367 | | - !amdtp_stream_wait_callback(&dice->rx_stream[i], |
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368 | | - CALLBACK_TIMEOUT))) { |
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369 | | - err = -ETIMEDOUT; |
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| 311 | + // After changing sampling transfer frequency, the value of |
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| 312 | + // register can be changed. |
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| 313 | + err = get_register_params(dice, &tx_params, &rx_params); |
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| 314 | + if (err < 0) |
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| 315 | + return err; |
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| 316 | + |
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| 317 | + err = keep_dual_resources(dice, rate, AMDTP_IN_STREAM, |
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| 318 | + &tx_params); |
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| 319 | + if (err < 0) |
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370 | 320 | goto error; |
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371 | | - } |
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| 321 | + |
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| 322 | + err = keep_dual_resources(dice, rate, AMDTP_OUT_STREAM, |
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| 323 | + &rx_params); |
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| 324 | + if (err < 0) |
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| 325 | + goto error; |
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| 326 | + |
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| 327 | + err = amdtp_domain_set_events_per_period(&dice->domain, |
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| 328 | + events_per_period, events_per_buffer); |
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| 329 | + if (err < 0) |
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| 330 | + goto error; |
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372 | 331 | } |
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373 | 332 | |
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374 | 333 | return 0; |
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375 | 334 | error: |
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376 | | - stop_streams(dice, AMDTP_IN_STREAM, &tx_params); |
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377 | | - stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); |
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378 | | - snd_dice_transaction_clear_enable(dice); |
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379 | 335 | release_resources(dice); |
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380 | 336 | return err; |
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| 337 | +} |
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| 338 | + |
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| 339 | +static int start_streams(struct snd_dice *dice, enum amdtp_stream_direction dir, |
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| 340 | + unsigned int rate, struct reg_params *params) |
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| 341 | +{ |
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| 342 | + unsigned int max_speed = fw_parent_device(dice->unit)->max_speed; |
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| 343 | + int i; |
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| 344 | + int err; |
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| 345 | + |
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| 346 | + for (i = 0; i < params->count; i++) { |
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| 347 | + struct amdtp_stream *stream; |
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| 348 | + struct fw_iso_resources *resources; |
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| 349 | + __be32 reg; |
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| 350 | + |
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| 351 | + if (dir == AMDTP_IN_STREAM) { |
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| 352 | + stream = dice->tx_stream + i; |
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| 353 | + resources = dice->tx_resources + i; |
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| 354 | + } else { |
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| 355 | + stream = dice->rx_stream + i; |
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| 356 | + resources = dice->rx_resources + i; |
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| 357 | + } |
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| 358 | + |
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| 359 | + reg = cpu_to_be32(resources->channel); |
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| 360 | + if (dir == AMDTP_IN_STREAM) { |
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| 361 | + err = snd_dice_transaction_write_tx(dice, |
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| 362 | + params->size * i + TX_ISOCHRONOUS, |
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| 363 | + ®, sizeof(reg)); |
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| 364 | + } else { |
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| 365 | + err = snd_dice_transaction_write_rx(dice, |
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| 366 | + params->size * i + RX_ISOCHRONOUS, |
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| 367 | + ®, sizeof(reg)); |
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| 368 | + } |
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| 369 | + if (err < 0) |
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| 370 | + return err; |
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| 371 | + |
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| 372 | + if (dir == AMDTP_IN_STREAM) { |
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| 373 | + reg = cpu_to_be32(max_speed); |
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| 374 | + err = snd_dice_transaction_write_tx(dice, |
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| 375 | + params->size * i + TX_SPEED, |
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| 376 | + ®, sizeof(reg)); |
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| 377 | + if (err < 0) |
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| 378 | + return err; |
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| 379 | + } |
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| 380 | + |
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| 381 | + err = amdtp_domain_add_stream(&dice->domain, stream, |
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| 382 | + resources->channel, max_speed); |
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| 383 | + if (err < 0) |
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| 384 | + return err; |
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| 385 | + } |
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| 386 | + |
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| 387 | + return 0; |
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381 | 388 | } |
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382 | 389 | |
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383 | 390 | /* |
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.. | .. |
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385 | 392 | * - None streams are running. |
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386 | 393 | * - All streams are running. |
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387 | 394 | */ |
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388 | | -int snd_dice_stream_start_duplex(struct snd_dice *dice, unsigned int rate) |
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| 395 | +int snd_dice_stream_start_duplex(struct snd_dice *dice) |
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389 | 396 | { |
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390 | | - unsigned int curr_rate; |
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| 397 | + unsigned int generation = dice->rx_resources[0].generation; |
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| 398 | + struct reg_params tx_params, rx_params; |
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391 | 399 | unsigned int i; |
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| 400 | + unsigned int rate; |
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392 | 401 | enum snd_dice_rate_mode mode; |
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393 | 402 | int err; |
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394 | 403 | |
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395 | 404 | if (dice->substreams_counter == 0) |
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396 | 405 | return -EIO; |
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397 | 406 | |
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398 | | - /* Check sampling transmission frequency. */ |
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399 | | - err = snd_dice_transaction_get_rate(dice, &curr_rate); |
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400 | | - if (err < 0) { |
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401 | | - dev_err(&dice->unit->device, |
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402 | | - "fail to get sampling rate\n"); |
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| 407 | + err = get_register_params(dice, &tx_params, &rx_params); |
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| 408 | + if (err < 0) |
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403 | 409 | return err; |
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404 | | - } |
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405 | | - if (rate == 0) |
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406 | | - rate = curr_rate; |
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407 | | - if (rate != curr_rate) |
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408 | | - goto restart; |
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409 | 410 | |
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410 | | - /* Check error of packet streaming. */ |
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| 411 | + // Check error of packet streaming. |
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411 | 412 | for (i = 0; i < MAX_STREAMS; ++i) { |
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412 | | - if (amdtp_streaming_error(&dice->tx_stream[i])) |
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| 413 | + if (amdtp_streaming_error(&dice->tx_stream[i]) || |
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| 414 | + amdtp_streaming_error(&dice->rx_stream[i])) { |
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| 415 | + amdtp_domain_stop(&dice->domain); |
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| 416 | + finish_session(dice, &tx_params, &rx_params); |
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413 | 417 | break; |
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414 | | - if (amdtp_streaming_error(&dice->rx_stream[i])) |
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415 | | - break; |
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| 418 | + } |
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416 | 419 | } |
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417 | | - if (i < MAX_STREAMS) |
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418 | | - goto restart; |
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419 | 420 | |
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420 | | - /* Check required streams are running or not. */ |
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| 421 | + if (generation != fw_parent_device(dice->unit)->card->generation) { |
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| 422 | + for (i = 0; i < MAX_STREAMS; ++i) { |
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| 423 | + if (i < tx_params.count) |
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| 424 | + fw_iso_resources_update(dice->tx_resources + i); |
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| 425 | + if (i < rx_params.count) |
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| 426 | + fw_iso_resources_update(dice->rx_resources + i); |
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| 427 | + } |
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| 428 | + } |
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| 429 | + |
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| 430 | + // Check required streams are running or not. |
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| 431 | + err = snd_dice_transaction_get_rate(dice, &rate); |
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| 432 | + if (err < 0) |
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| 433 | + return err; |
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421 | 434 | err = snd_dice_stream_get_rate_mode(dice, rate, &mode); |
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422 | 435 | if (err < 0) |
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423 | 436 | return err; |
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.. | .. |
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429 | 442 | !amdtp_stream_running(&dice->rx_stream[i])) |
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430 | 443 | break; |
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431 | 444 | } |
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432 | | - if (i < MAX_STREAMS) |
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433 | | - goto restart; |
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| 445 | + if (i < MAX_STREAMS) { |
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| 446 | + // Start both streams. |
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| 447 | + err = start_streams(dice, AMDTP_IN_STREAM, rate, &tx_params); |
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| 448 | + if (err < 0) |
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| 449 | + goto error; |
---|
| 450 | + |
---|
| 451 | + err = start_streams(dice, AMDTP_OUT_STREAM, rate, &rx_params); |
---|
| 452 | + if (err < 0) |
---|
| 453 | + goto error; |
---|
| 454 | + |
---|
| 455 | + err = snd_dice_transaction_set_enable(dice); |
---|
| 456 | + if (err < 0) { |
---|
| 457 | + dev_err(&dice->unit->device, |
---|
| 458 | + "fail to enable interface\n"); |
---|
| 459 | + goto error; |
---|
| 460 | + } |
---|
| 461 | + |
---|
| 462 | + err = amdtp_domain_start(&dice->domain, 0); |
---|
| 463 | + if (err < 0) |
---|
| 464 | + goto error; |
---|
| 465 | + |
---|
| 466 | + for (i = 0; i < MAX_STREAMS; i++) { |
---|
| 467 | + if ((i < tx_params.count && |
---|
| 468 | + !amdtp_stream_wait_callback(&dice->tx_stream[i], |
---|
| 469 | + CALLBACK_TIMEOUT)) || |
---|
| 470 | + (i < rx_params.count && |
---|
| 471 | + !amdtp_stream_wait_callback(&dice->rx_stream[i], |
---|
| 472 | + CALLBACK_TIMEOUT))) { |
---|
| 473 | + err = -ETIMEDOUT; |
---|
| 474 | + goto error; |
---|
| 475 | + } |
---|
| 476 | + } |
---|
| 477 | + } |
---|
434 | 478 | |
---|
435 | 479 | return 0; |
---|
436 | | -restart: |
---|
437 | | - return start_duplex_streams(dice, rate); |
---|
| 480 | +error: |
---|
| 481 | + amdtp_domain_stop(&dice->domain); |
---|
| 482 | + finish_session(dice, &tx_params, &rx_params); |
---|
| 483 | + return err; |
---|
438 | 484 | } |
---|
439 | 485 | |
---|
440 | 486 | /* |
---|
.. | .. |
---|
446 | 492 | { |
---|
447 | 493 | struct reg_params tx_params, rx_params; |
---|
448 | 494 | |
---|
449 | | - if (dice->substreams_counter > 0) |
---|
450 | | - return; |
---|
| 495 | + if (dice->substreams_counter == 0) { |
---|
| 496 | + if (get_register_params(dice, &tx_params, &rx_params) >= 0) |
---|
| 497 | + finish_session(dice, &tx_params, &rx_params); |
---|
451 | 498 | |
---|
452 | | - snd_dice_transaction_clear_enable(dice); |
---|
453 | | - |
---|
454 | | - if (get_register_params(dice, &tx_params, &rx_params) == 0) { |
---|
455 | | - stop_streams(dice, AMDTP_IN_STREAM, &tx_params); |
---|
456 | | - stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); |
---|
| 499 | + amdtp_domain_stop(&dice->domain); |
---|
| 500 | + release_resources(dice); |
---|
457 | 501 | } |
---|
458 | | - |
---|
459 | | - release_resources(dice); |
---|
460 | 502 | } |
---|
461 | 503 | |
---|
462 | 504 | static int init_stream(struct snd_dice *dice, enum amdtp_stream_direction dir, |
---|
.. | .. |
---|
531 | 573 | destroy_stream(dice, AMDTP_OUT_STREAM, i); |
---|
532 | 574 | for (i = 0; i < MAX_STREAMS; i++) |
---|
533 | 575 | destroy_stream(dice, AMDTP_IN_STREAM, i); |
---|
534 | | - break; |
---|
| 576 | + goto end; |
---|
| 577 | + } |
---|
| 578 | + } |
---|
| 579 | + |
---|
| 580 | + err = amdtp_domain_init(&dice->domain); |
---|
| 581 | + if (err < 0) { |
---|
| 582 | + for (i = 0; i < MAX_STREAMS; ++i) { |
---|
| 583 | + destroy_stream(dice, AMDTP_OUT_STREAM, i); |
---|
| 584 | + destroy_stream(dice, AMDTP_IN_STREAM, i); |
---|
535 | 585 | } |
---|
536 | 586 | } |
---|
537 | 587 | end: |
---|
.. | .. |
---|
546 | 596 | destroy_stream(dice, AMDTP_IN_STREAM, i); |
---|
547 | 597 | destroy_stream(dice, AMDTP_OUT_STREAM, i); |
---|
548 | 598 | } |
---|
| 599 | + |
---|
| 600 | + amdtp_domain_destroy(&dice->domain); |
---|
549 | 601 | } |
---|
550 | 602 | |
---|
551 | 603 | void snd_dice_stream_update_duplex(struct snd_dice *dice) |
---|
.. | .. |
---|
563 | 615 | dice->global_enabled = false; |
---|
564 | 616 | |
---|
565 | 617 | if (get_register_params(dice, &tx_params, &rx_params) == 0) { |
---|
| 618 | + amdtp_domain_stop(&dice->domain); |
---|
| 619 | + |
---|
566 | 620 | stop_streams(dice, AMDTP_IN_STREAM, &tx_params); |
---|
567 | 621 | stop_streams(dice, AMDTP_OUT_STREAM, &rx_params); |
---|
568 | 622 | } |
---|