add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/include/dt-bindings/sound/qcom,q6afe.h
..
..
@@ -106,6 +106,101 @@
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 #define QUINARY_TDM_TX_6	101
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 #define QUINARY_TDM_RX_7	102
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 #define QUINARY_TDM_TX_7	103
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+#define DISPLAY_PORT_RX		104
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+#define WSA_CODEC_DMA_RX_0	105
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+#define WSA_CODEC_DMA_TX_0	106
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+#define WSA_CODEC_DMA_RX_1	107
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+#define WSA_CODEC_DMA_TX_1	108
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+#define WSA_CODEC_DMA_TX_2	109
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+#define VA_CODEC_DMA_TX_0	110
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+#define VA_CODEC_DMA_TX_1	111
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+#define VA_CODEC_DMA_TX_2	112
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+#define RX_CODEC_DMA_RX_0	113
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+#define TX_CODEC_DMA_TX_0	114
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+#define RX_CODEC_DMA_RX_1	115
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+#define TX_CODEC_DMA_TX_1	116
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+#define RX_CODEC_DMA_RX_2	117
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+#define TX_CODEC_DMA_TX_2	118
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+#define RX_CODEC_DMA_RX_3	119
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+#define TX_CODEC_DMA_TX_3	120
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+#define RX_CODEC_DMA_RX_4	121
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+#define TX_CODEC_DMA_TX_4	122
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+#define RX_CODEC_DMA_RX_5	123
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+#define TX_CODEC_DMA_TX_5	124
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+#define RX_CODEC_DMA_RX_6	125
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+#define RX_CODEC_DMA_RX_7	126
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+
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+#define LPASS_CLK_ID_PRI_MI2S_IBIT	1
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+#define LPASS_CLK_ID_PRI_MI2S_EBIT	2
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+#define LPASS_CLK_ID_SEC_MI2S_IBIT	3
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+#define LPASS_CLK_ID_SEC_MI2S_EBIT	4
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+#define LPASS_CLK_ID_TER_MI2S_IBIT	5
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+#define LPASS_CLK_ID_TER_MI2S_EBIT	6
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+#define LPASS_CLK_ID_QUAD_MI2S_IBIT	7
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+#define LPASS_CLK_ID_QUAD_MI2S_EBIT	8
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+#define LPASS_CLK_ID_SPEAKER_I2S_IBIT	9
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+#define LPASS_CLK_ID_SPEAKER_I2S_EBIT	10
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+#define LPASS_CLK_ID_SPEAKER_I2S_OSR	11
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+#define LPASS_CLK_ID_QUI_MI2S_IBIT	12
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+#define LPASS_CLK_ID_QUI_MI2S_EBIT	13
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+#define LPASS_CLK_ID_SEN_MI2S_IBIT	14
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+#define LPASS_CLK_ID_SEN_MI2S_EBIT	15
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+#define LPASS_CLK_ID_INT0_MI2S_IBIT	16
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+#define LPASS_CLK_ID_INT1_MI2S_IBIT	17
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+#define LPASS_CLK_ID_INT2_MI2S_IBIT	18
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+#define LPASS_CLK_ID_INT3_MI2S_IBIT	19
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+#define LPASS_CLK_ID_INT4_MI2S_IBIT	20
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+#define LPASS_CLK_ID_INT5_MI2S_IBIT	21
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+#define LPASS_CLK_ID_INT6_MI2S_IBIT	22
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+#define LPASS_CLK_ID_QUI_MI2S_OSR	23
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+#define LPASS_CLK_ID_PRI_PCM_IBIT	24
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+#define LPASS_CLK_ID_PRI_PCM_EBIT	25
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+#define LPASS_CLK_ID_SEC_PCM_IBIT	26
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+#define LPASS_CLK_ID_SEC_PCM_EBIT	27
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+#define LPASS_CLK_ID_TER_PCM_IBIT	28
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+#define LPASS_CLK_ID_TER_PCM_EBIT	29
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+#define LPASS_CLK_ID_QUAD_PCM_IBIT	30
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+#define LPASS_CLK_ID_QUAD_PCM_EBIT	31
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+#define LPASS_CLK_ID_QUIN_PCM_IBIT	32
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+#define LPASS_CLK_ID_QUIN_PCM_EBIT	33
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+#define LPASS_CLK_ID_QUI_PCM_OSR	34
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+#define LPASS_CLK_ID_PRI_TDM_IBIT	35
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+#define LPASS_CLK_ID_PRI_TDM_EBIT	36
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+#define LPASS_CLK_ID_SEC_TDM_IBIT	37
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+#define LPASS_CLK_ID_SEC_TDM_EBIT	38
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+#define LPASS_CLK_ID_TER_TDM_IBIT	39
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+#define LPASS_CLK_ID_TER_TDM_EBIT	40
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+#define LPASS_CLK_ID_QUAD_TDM_IBIT	41
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+#define LPASS_CLK_ID_QUAD_TDM_EBIT	42
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+#define LPASS_CLK_ID_QUIN_TDM_IBIT	43
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+#define LPASS_CLK_ID_QUIN_TDM_EBIT	44
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+#define LPASS_CLK_ID_QUIN_TDM_OSR	45
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+#define LPASS_CLK_ID_MCLK_1		46
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+#define LPASS_CLK_ID_MCLK_2		47
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+#define LPASS_CLK_ID_MCLK_3		48
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+#define LPASS_CLK_ID_MCLK_4		49
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+#define LPASS_CLK_ID_INTERNAL_DIGITAL_CODEC_CORE	50
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+#define LPASS_CLK_ID_INT_MCLK_0		51
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+#define LPASS_CLK_ID_INT_MCLK_1		52
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+#define LPASS_CLK_ID_MCLK_5		53
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+#define LPASS_CLK_ID_WSA_CORE_MCLK	54
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+#define LPASS_CLK_ID_WSA_CORE_NPL_MCLK	55
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+#define LPASS_CLK_ID_VA_CORE_MCLK	56
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+#define LPASS_CLK_ID_TX_CORE_MCLK	57
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+#define LPASS_CLK_ID_TX_CORE_NPL_MCLK	58
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+#define LPASS_CLK_ID_RX_CORE_MCLK	59
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+#define LPASS_CLK_ID_RX_CORE_NPL_MCLK	60
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+#define LPASS_CLK_ID_VA_CORE_2X_MCLK	61
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+
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+#define LPASS_HW_AVTIMER_VOTE		101
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+#define LPASS_HW_MACRO_VOTE		102
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+#define LPASS_HW_DCODEC_VOTE		103
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+
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+#define Q6AFE_MAX_CLK_ID			104
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+
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+#define LPASS_CLK_ATTRIBUTE_INVALID		0x0
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+#define LPASS_CLK_ATTRIBUTE_COUPLE_NO		0x1
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+#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVIDEND	0x2
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+#define LPASS_CLK_ATTRIBUTE_COUPLE_DIVISOR	0x3
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 #endif /* __DT_BINDINGS_Q6_AFE_H__ */
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