add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/include/dt-bindings/memory/tegra186-mc.h
..
..
@@ -108,4 +108,143 @@
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 #define TEGRA186_SID_SE_VM6		0x4e
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 #define TEGRA186_SID_SE_VM7		0x4f
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+/*
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+ * memory client IDs
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+ */
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+
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+/* Misses from System Memory Management Unit (SMMU) Page Table Cache (PTC) */
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+#define TEGRA186_MEMORY_CLIENT_PTCR 0x00
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+/* PCIE reads */
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+#define TEGRA186_MEMORY_CLIENT_AFIR 0x0e
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+/* High-definition audio (HDA) reads */
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+#define TEGRA186_MEMORY_CLIENT_HDAR 0x15
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+/* Host channel data reads */
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+#define TEGRA186_MEMORY_CLIENT_HOST1XDMAR 0x16
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+#define TEGRA186_MEMORY_CLIENT_NVENCSRD 0x1c
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+/* SATA reads */
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+#define TEGRA186_MEMORY_CLIENT_SATAR 0x1f
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+/* Reads from Cortex-A9 4 CPU cores via the L2 cache */
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+#define TEGRA186_MEMORY_CLIENT_MPCORER 0x27
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+#define TEGRA186_MEMORY_CLIENT_NVENCSWR 0x2b
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+/* PCIE writes */
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+#define TEGRA186_MEMORY_CLIENT_AFIW 0x31
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+/* High-definition audio (HDA) writes */
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+#define TEGRA186_MEMORY_CLIENT_HDAW 0x35
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+/* Writes from Cortex-A9 4 CPU cores via the L2 cache */
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+#define TEGRA186_MEMORY_CLIENT_MPCOREW 0x39
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+/* SATA writes */
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+#define TEGRA186_MEMORY_CLIENT_SATAW 0x3d
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+/* ISP Read client for Crossbar A */
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+#define TEGRA186_MEMORY_CLIENT_ISPRA 0x44
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+/* ISP Write client for Crossbar A */
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+#define TEGRA186_MEMORY_CLIENT_ISPWA 0x46
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+/* ISP Write client Crossbar B */
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+#define TEGRA186_MEMORY_CLIENT_ISPWB 0x47
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+/* XUSB reads */
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+#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTR 0x4a
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+/* XUSB_HOST writes */
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+#define TEGRA186_MEMORY_CLIENT_XUSB_HOSTW 0x4b
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+/* XUSB reads */
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+#define TEGRA186_MEMORY_CLIENT_XUSB_DEVR 0x4c
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+/* XUSB_DEV writes */
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+#define TEGRA186_MEMORY_CLIENT_XUSB_DEVW 0x4d
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+/* TSEC Memory Return Data Client Description */
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+#define TEGRA186_MEMORY_CLIENT_TSECSRD 0x54
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+/* TSEC Memory Write Client Description */
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+#define TEGRA186_MEMORY_CLIENT_TSECSWR 0x55
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+/* 3D, ltcx reads instance 0 */
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+#define TEGRA186_MEMORY_CLIENT_GPUSRD 0x58
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+/* 3D, ltcx writes instance 0 */
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+#define TEGRA186_MEMORY_CLIENT_GPUSWR 0x59
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+/* sdmmca memory read client */
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+#define TEGRA186_MEMORY_CLIENT_SDMMCRA 0x60
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+/* sdmmcbmemory read client */
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+#define TEGRA186_MEMORY_CLIENT_SDMMCRAA 0x61
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+/* sdmmc memory read client */
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+#define TEGRA186_MEMORY_CLIENT_SDMMCR 0x62
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+/* sdmmcd memory read client */
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+#define TEGRA186_MEMORY_CLIENT_SDMMCRAB 0x63
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+/* sdmmca memory write client */
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+#define TEGRA186_MEMORY_CLIENT_SDMMCWA 0x64
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+/* sdmmcb memory write client */
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+#define TEGRA186_MEMORY_CLIENT_SDMMCWAA 0x65
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+/* sdmmc memory write client */
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+#define TEGRA186_MEMORY_CLIENT_SDMMCW 0x66
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+/* sdmmcd memory write client */
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+#define TEGRA186_MEMORY_CLIENT_SDMMCWAB 0x67
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+#define TEGRA186_MEMORY_CLIENT_VICSRD 0x6c
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+#define TEGRA186_MEMORY_CLIENT_VICSWR 0x6d
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+/* VI Write client */
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+#define TEGRA186_MEMORY_CLIENT_VIW 0x72
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+#define TEGRA186_MEMORY_CLIENT_NVDECSRD 0x78
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+#define TEGRA186_MEMORY_CLIENT_NVDECSWR 0x79
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+/* Audio Processing (APE) engine reads */
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+#define TEGRA186_MEMORY_CLIENT_APER 0x7a
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+/* Audio Processing (APE) engine writes */
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+#define TEGRA186_MEMORY_CLIENT_APEW 0x7b
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+#define TEGRA186_MEMORY_CLIENT_NVJPGSRD 0x7e
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+#define TEGRA186_MEMORY_CLIENT_NVJPGSWR 0x7f
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+/* SE Memory Return Data Client Description */
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+#define TEGRA186_MEMORY_CLIENT_SESRD 0x80
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+/* SE Memory Write Client Description */
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+#define TEGRA186_MEMORY_CLIENT_SESWR 0x81
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+/* ETR reads */
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+#define TEGRA186_MEMORY_CLIENT_ETRR 0x84
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+/* ETR writes */
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+#define TEGRA186_MEMORY_CLIENT_ETRW 0x85
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+/* TSECB Memory Return Data Client Description */
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+#define TEGRA186_MEMORY_CLIENT_TSECSRDB 0x86
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+/* TSECB Memory Write Client Description */
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+#define TEGRA186_MEMORY_CLIENT_TSECSWRB 0x87
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+/* 3D, ltcx reads instance 1 */
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+#define TEGRA186_MEMORY_CLIENT_GPUSRD2 0x88
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+/* 3D, ltcx writes instance 1 */
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+#define TEGRA186_MEMORY_CLIENT_GPUSWR2 0x89
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+/* AXI Switch read client */
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+#define TEGRA186_MEMORY_CLIENT_AXISR 0x8c
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+/* AXI Switch write client */
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+#define TEGRA186_MEMORY_CLIENT_AXISW 0x8d
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+/* EQOS read client */
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+#define TEGRA186_MEMORY_CLIENT_EQOSR 0x8e
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+/* EQOS write client */
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+#define TEGRA186_MEMORY_CLIENT_EQOSW 0x8f
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+/* UFSHC read client */
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+#define TEGRA186_MEMORY_CLIENT_UFSHCR 0x90
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+/* UFSHC write client */
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+#define TEGRA186_MEMORY_CLIENT_UFSHCW 0x91
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+/* NVDISPLAY read client */
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+#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR 0x92
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+/* BPMP read client */
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+#define TEGRA186_MEMORY_CLIENT_BPMPR 0x93
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+/* BPMP write client */
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+#define TEGRA186_MEMORY_CLIENT_BPMPW 0x94
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+/* BPMPDMA read client */
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+#define TEGRA186_MEMORY_CLIENT_BPMPDMAR 0x95
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+/* BPMPDMA write client */
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+#define TEGRA186_MEMORY_CLIENT_BPMPDMAW 0x96
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+/* AON read client */
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+#define TEGRA186_MEMORY_CLIENT_AONR 0x97
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+/* AON write client */
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+#define TEGRA186_MEMORY_CLIENT_AONW 0x98
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+/* AONDMA read client */
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+#define TEGRA186_MEMORY_CLIENT_AONDMAR 0x99
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+/* AONDMA write client */
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+#define TEGRA186_MEMORY_CLIENT_AONDMAW 0x9a
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+/* SCE read client */
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+#define TEGRA186_MEMORY_CLIENT_SCER 0x9b
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+/* SCE write client */
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+#define TEGRA186_MEMORY_CLIENT_SCEW 0x9c
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+/* SCEDMA read client */
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+#define TEGRA186_MEMORY_CLIENT_SCEDMAR 0x9d
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+/* SCEDMA write client */
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+#define TEGRA186_MEMORY_CLIENT_SCEDMAW 0x9e
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+/* APEDMA read client */
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+#define TEGRA186_MEMORY_CLIENT_APEDMAR 0x9f
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+/* APEDMA write client */
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+#define TEGRA186_MEMORY_CLIENT_APEDMAW 0xa0
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+/* NVDISPLAY read client instance 2 */
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+#define TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 0xa1
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+#define TEGRA186_MEMORY_CLIENT_VICSRD1 0xa2
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+#define TEGRA186_MEMORY_CLIENT_NVDECSRD1 0xa3
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+
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 #endif