hc
2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2
kernel/include/dt-bindings/clock/tegra210-car.h
....@@ -262,6 +262,8 @@
262262 #define TEGRA210_CLK_CLK_M 233
263263 #define TEGRA210_CLK_CLK_M_DIV2 234
264264 #define TEGRA210_CLK_CLK_M_DIV4 235
265
+#define TEGRA210_CLK_OSC_DIV2 234
266
+#define TEGRA210_CLK_OSC_DIV4 235
265267 #define TEGRA210_CLK_PLL_REF 236
266268 #define TEGRA210_CLK_PLL_C 237
267269 #define TEGRA210_CLK_PLL_C_OUT1 238
....@@ -304,12 +306,12 @@
304306 #define TEGRA210_CLK_AUDIO3 274
305307 #define TEGRA210_CLK_AUDIO4 275
306308 #define TEGRA210_CLK_SPDIF 276
307
-#define TEGRA210_CLK_CLK_OUT_1 277
308
-#define TEGRA210_CLK_CLK_OUT_2 278
309
-#define TEGRA210_CLK_CLK_OUT_3 279
310
-#define TEGRA210_CLK_BLINK 280
311
-/* 281 */
312
-#define TEGRA210_CLK_SOR1_SRC 282
309
+/* 277 */
310
+/* 278 */
311
+/* 279 */
312
+/* 280 */
313
+#define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
314
+#define TEGRA210_CLK_SOR0_OUT 281
313315 #define TEGRA210_CLK_SOR1_OUT 282
314316 /* 283 */
315317 #define TEGRA210_CLK_XUSB_HOST_SRC 284
....@@ -349,14 +351,14 @@
349351 #define TEGRA210_CLK_PLL_P_OUT_XUSB 317
350352 #define TEGRA210_CLK_XUSB_SSP_SRC 318
351353 #define TEGRA210_CLK_PLL_RE_OUT1 319
352
-/* 320 */
353
-/* 321 */
354
+#define TEGRA210_CLK_PLL_MB_UD 320
355
+#define TEGRA210_CLK_PLL_P_UD 321
354356 #define TEGRA210_CLK_ISP 322
355357 #define TEGRA210_CLK_PLL_A_OUT_ADSP 323
356358 #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
357359 /* 325 */
358
-/* 326 */
359
-/* 327 */
360
+#define TEGRA210_CLK_OSC 326
361
+#define TEGRA210_CLK_CSI_TPG 327
360362 /* 328 */
361363 /* 329 */
362364 /* 330 */
....@@ -386,12 +388,12 @@
386388 #define TEGRA210_CLK_AUDIO3_MUX 353
387389 #define TEGRA210_CLK_AUDIO4_MUX 354
388390 #define TEGRA210_CLK_SPDIF_MUX 355
389
-#define TEGRA210_CLK_CLK_OUT_1_MUX 356
390
-#define TEGRA210_CLK_CLK_OUT_2_MUX 357
391
-#define TEGRA210_CLK_CLK_OUT_3_MUX 358
391
+/* 356 */
392
+/* 357 */
393
+/* 358 */
392394 #define TEGRA210_CLK_DSIA_MUX 359
393395 #define TEGRA210_CLK_DSIB_MUX 360
394
-#define TEGRA210_CLK_SOR0_LVDS 361
396
+/* 361 */
395397 #define TEGRA210_CLK_XUSB_SS_DIV2 362
396398
397399 #define TEGRA210_CLK_PLL_M_UD 363