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hc
2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 
 kernel/include/drm/drm_dp_helper.h
....@@ -23,9 +23,12 @@
2323 #ifndef _DRM_DP_HELPER_H_
2424 #define _DRM_DP_HELPER_H_
2525 
26
-#include <linux/types.h>
27
-#include <linux/i2c.h>
2826 #include <linux/delay.h>
27
+#include <linux/i2c.h>
28
+#include <linux/types.h>
29
+#include <drm/drm_connector.h>
30
+
31
+struct drm_device;
2932 
3033 /*
3134  * Unless otherwise noted, all values are from the DP 1.1a spec.  Note that
....@@ -41,6 +44,48 @@
4144  *
4245  * 1.2 formally includes both eDP and DPI definitions.
4346  */
47
+
48
+/* MSA (Main Stream Attribute) MISC bits (as MISC1<<8|MISC0) */
49
+#define DP_MSA_MISC_SYNC_CLOCK			(1 << 0)
50
+#define DP_MSA_MISC_INTERLACE_VTOTAL_EVEN	(1 << 8)
51
+#define DP_MSA_MISC_STEREO_NO_3D		(0 << 9)
52
+#define DP_MSA_MISC_STEREO_PROG_RIGHT_EYE	(1 << 9)
53
+#define DP_MSA_MISC_STEREO_PROG_LEFT_EYE	(3 << 9)
54
+/* bits per component for non-RAW */
55
+#define DP_MSA_MISC_6_BPC			(0 << 5)
56
+#define DP_MSA_MISC_8_BPC			(1 << 5)
57
+#define DP_MSA_MISC_10_BPC			(2 << 5)
58
+#define DP_MSA_MISC_12_BPC			(3 << 5)
59
+#define DP_MSA_MISC_16_BPC			(4 << 5)
60
+/* bits per component for RAW */
61
+#define DP_MSA_MISC_RAW_6_BPC			(1 << 5)
62
+#define DP_MSA_MISC_RAW_7_BPC			(2 << 5)
63
+#define DP_MSA_MISC_RAW_8_BPC			(3 << 5)
64
+#define DP_MSA_MISC_RAW_10_BPC			(4 << 5)
65
+#define DP_MSA_MISC_RAW_12_BPC			(5 << 5)
66
+#define DP_MSA_MISC_RAW_14_BPC			(6 << 5)
67
+#define DP_MSA_MISC_RAW_16_BPC			(7 << 5)
68
+/* pixel encoding/colorimetry format */
69
+#define _DP_MSA_MISC_COLOR(misc1_7, misc0_21, misc0_3, misc0_4) \
70
+	((misc1_7) << 15 | (misc0_4) << 4 | (misc0_3) << 3 | ((misc0_21) << 1))
71
+#define DP_MSA_MISC_COLOR_RGB			_DP_MSA_MISC_COLOR(0, 0, 0, 0)
72
+#define DP_MSA_MISC_COLOR_CEA_RGB		_DP_MSA_MISC_COLOR(0, 0, 1, 0)
73
+#define DP_MSA_MISC_COLOR_RGB_WIDE_FIXED	_DP_MSA_MISC_COLOR(0, 3, 0, 0)
74
+#define DP_MSA_MISC_COLOR_RGB_WIDE_FLOAT	_DP_MSA_MISC_COLOR(0, 3, 0, 1)
75
+#define DP_MSA_MISC_COLOR_Y_ONLY		_DP_MSA_MISC_COLOR(1, 0, 0, 0)
76
+#define DP_MSA_MISC_COLOR_RAW			_DP_MSA_MISC_COLOR(1, 1, 0, 0)
77
+#define DP_MSA_MISC_COLOR_YCBCR_422_BT601	_DP_MSA_MISC_COLOR(0, 1, 1, 0)
78
+#define DP_MSA_MISC_COLOR_YCBCR_422_BT709	_DP_MSA_MISC_COLOR(0, 1, 1, 1)
79
+#define DP_MSA_MISC_COLOR_YCBCR_444_BT601	_DP_MSA_MISC_COLOR(0, 2, 1, 0)
80
+#define DP_MSA_MISC_COLOR_YCBCR_444_BT709	_DP_MSA_MISC_COLOR(0, 2, 1, 1)
81
+#define DP_MSA_MISC_COLOR_XVYCC_422_BT601	_DP_MSA_MISC_COLOR(0, 1, 0, 0)
82
+#define DP_MSA_MISC_COLOR_XVYCC_422_BT709	_DP_MSA_MISC_COLOR(0, 1, 0, 1)
83
+#define DP_MSA_MISC_COLOR_XVYCC_444_BT601	_DP_MSA_MISC_COLOR(0, 2, 0, 0)
84
+#define DP_MSA_MISC_COLOR_XVYCC_444_BT709	_DP_MSA_MISC_COLOR(0, 2, 0, 1)
85
+#define DP_MSA_MISC_COLOR_OPRGB			_DP_MSA_MISC_COLOR(0, 0, 1, 1)
86
+#define DP_MSA_MISC_COLOR_DCI_P3		_DP_MSA_MISC_COLOR(0, 3, 1, 0)
87
+#define DP_MSA_MISC_COLOR_COLOR_PROFILE		_DP_MSA_MISC_COLOR(0, 3, 1, 1)
88
+#define DP_MSA_MISC_COLOR_VSC_SDP		(1 << 14)
4489 
4590 #define DP_AUX_MAX_PAYLOAD_BYTES	16
4691 
....@@ -95,6 +140,7 @@
95140 # define DP_DETAILED_CAP_INFO_AVAILABLE	    (1 << 4) /* DPI */
96141 
97142 #define DP_MAIN_LINK_CHANNEL_CODING         0x006
143
+# define DP_CAP_ANSI_8B10B		    (1 << 0)
98144 
99145 #define DP_DOWN_STREAM_PORT_COUNT	    0x007
100146 # define DP_PORT_COUNT_MASK		    0x0f
....@@ -123,8 +169,9 @@
123169 # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
124170 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
125171 
126
-#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
127
-# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
172
+#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
173
+# define DP_TRAINING_AUX_RD_MASK                0x7F    /* DP 1.3 */
174
+# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT	(1 << 7) /* DP 1.3 */
128175 
129176 #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
130177 # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
....@@ -248,6 +295,7 @@
248295 #define DP_DSC_PEAK_THROUGHPUT              0x06B
249296 # define DP_DSC_THROUGHPUT_MODE_0_MASK      (0xf << 0)
250297 # define DP_DSC_THROUGHPUT_MODE_0_SHIFT     0
298
+# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0
251299 # define DP_DSC_THROUGHPUT_MODE_0_340       (1 << 0)
252300 # define DP_DSC_THROUGHPUT_MODE_0_400       (2 << 0)
253301 # define DP_DSC_THROUGHPUT_MODE_0_450       (3 << 0)
....@@ -262,8 +310,10 @@
262310 # define DP_DSC_THROUGHPUT_MODE_0_900       (12 << 0)
263311 # define DP_DSC_THROUGHPUT_MODE_0_950       (13 << 0)
264312 # define DP_DSC_THROUGHPUT_MODE_0_1000      (14 << 0)
313
+# define DP_DSC_THROUGHPUT_MODE_0_170       (15 << 0) /* 1.4a */
265314 # define DP_DSC_THROUGHPUT_MODE_1_MASK      (0xf << 4)
266315 # define DP_DSC_THROUGHPUT_MODE_1_SHIFT     4
316
+# define DP_DSC_THROUGHPUT_MODE_1_UNSUPPORTED 0
267317 # define DP_DSC_THROUGHPUT_MODE_1_340       (1 << 4)
268318 # define DP_DSC_THROUGHPUT_MODE_1_400       (2 << 4)
269319 # define DP_DSC_THROUGHPUT_MODE_1_450       (3 << 4)
....@@ -278,6 +328,7 @@
278328 # define DP_DSC_THROUGHPUT_MODE_1_900       (12 << 4)
279329 # define DP_DSC_THROUGHPUT_MODE_1_950       (13 << 4)
280330 # define DP_DSC_THROUGHPUT_MODE_1_1000      (14 << 4)
331
+# define DP_DSC_THROUGHPUT_MODE_1_170       (15 << 4)
281332 
282333 #define DP_DSC_MAX_SLICE_WIDTH              0x06C
283334 #define DP_DSC_MIN_SLICE_WIDTH_VALUE        2560
....@@ -313,6 +364,10 @@
313364 # define DP_PSR_SETUP_TIME_SHIFT            1
314365 # define DP_PSR2_SU_Y_COORDINATE_REQUIRED   (1 << 4)  /* eDP 1.4a */
315366 # define DP_PSR2_SU_GRANULARITY_REQUIRED    (1 << 5)  /* eDP 1.4b */
367
+
368
+#define DP_PSR2_SU_X_GRANULARITY	    0x072 /* eDP 1.4b */
369
+#define DP_PSR2_SU_Y_GRANULARITY	    0x074 /* eDP 1.4b */
370
+
316371 /*
317372  * 0x80-0x8f describe downstream port capabilities, but there are two layouts
318373  * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set.  If it was not,
....@@ -332,13 +387,32 @@
332387 # define DP_DS_PORT_TYPE_DP_DUALMODE        5
333388 # define DP_DS_PORT_TYPE_WIRELESS           6
334389 # define DP_DS_PORT_HPD			    (1 << 3)
390
+# define DP_DS_NON_EDID_MASK		    (0xf << 4)
391
+# define DP_DS_NON_EDID_720x480i_60	    (1 << 4)
392
+# define DP_DS_NON_EDID_720x480i_50	    (2 << 4)
393
+# define DP_DS_NON_EDID_1920x1080i_60	    (3 << 4)
394
+# define DP_DS_NON_EDID_1920x1080i_50	    (4 << 4)
395
+# define DP_DS_NON_EDID_1280x720_60	    (5 << 4)
396
+# define DP_DS_NON_EDID_1280x720_50	    (7 << 4)
335397 /* offset 1 for VGA is maximum megapixels per second / 8 */
336
-/* offset 2 */
398
+/* offset 1 for DVI/HDMI is maximum TMDS clock in Mbps / 2.5 */
399
+/* offset 2 for VGA/DVI/HDMI */
337400 # define DP_DS_MAX_BPC_MASK	            (3 << 0)
338401 # define DP_DS_8BPC		            0
339402 # define DP_DS_10BPC		            1
340403 # define DP_DS_12BPC		            2
341404 # define DP_DS_16BPC		            3
405
+/* offset 3 for DVI */
406
+# define DP_DS_DVI_DUAL_LINK		    (1 << 1)
407
+# define DP_DS_DVI_HIGH_COLOR_DEPTH	    (1 << 2)
408
+/* offset 3 for HDMI */
409
+# define DP_DS_HDMI_FRAME_SEQ_TO_FRAME_PACK (1 << 0)
410
+# define DP_DS_HDMI_YCBCR422_PASS_THROUGH   (1 << 1)
411
+# define DP_DS_HDMI_YCBCR420_PASS_THROUGH   (1 << 2)
412
+# define DP_DS_HDMI_YCBCR444_TO_422_CONV    (1 << 3)
413
+# define DP_DS_HDMI_YCBCR444_TO_420_CONV    (1 << 4)
414
+
415
+#define DP_MAX_DOWNSTREAM_PORTS		    0x10
342416 
343417 /* DP Forward error Correction Registers */
344418 #define DP_FEC_CAPABILITY		    0x090    /* 1.4 */
....@@ -346,6 +420,11 @@
346420 # define DP_FEC_UNCORR_BLK_ERROR_COUNT_CAP  (1 << 1)
347421 # define DP_FEC_CORR_BLK_ERROR_COUNT_CAP    (1 << 2)
348422 # define DP_FEC_BIT_ERROR_COUNT_CAP	    (1 << 3)
423
+
424
+/* DP Extended DSC Capabilities */
425
+#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0  0x0a0   /* DP 1.4a SCR */
426
+#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1  0x0a1
427
+#define DP_DSC_BRANCH_MAX_LINE_WIDTH        0x0a2
349428 
350429 /* link configuration */
351430 #define	DP_LINK_BW_SET		            0x100
....@@ -548,6 +627,14 @@
548627 # define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT  6
549628 
550629 #define DP_ADJUST_REQUEST_POST_CURSOR2      0x20c
630
+# define DP_ADJUST_POST_CURSOR2_LANE0_MASK  0x03
631
+# define DP_ADJUST_POST_CURSOR2_LANE0_SHIFT 0
632
+# define DP_ADJUST_POST_CURSOR2_LANE1_MASK  0x0c
633
+# define DP_ADJUST_POST_CURSOR2_LANE1_SHIFT 2
634
+# define DP_ADJUST_POST_CURSOR2_LANE2_MASK  0x30
635
+# define DP_ADJUST_POST_CURSOR2_LANE2_SHIFT 4
636
+# define DP_ADJUST_POST_CURSOR2_LANE3_MASK  0xc0
637
+# define DP_ADJUST_POST_CURSOR2_LANE3_SHIFT 6
551638 
552639 #define DP_TEST_REQUEST			    0x218
553640 # define DP_TEST_LINK_TRAINING		    (1 << 0)
....@@ -555,6 +642,8 @@
555642 # define DP_TEST_LINK_EDID_READ		    (1 << 2)
556643 # define DP_TEST_LINK_PHY_TEST_PATTERN	    (1 << 3) /* DPCD >= 1.1 */
557644 # define DP_TEST_LINK_FAUX_PATTERN	    (1 << 4) /* DPCD >= 1.2 */
645
+# define DP_TEST_LINK_AUDIO_PATTERN         (1 << 5) /* DPCD >= 1.2 */
646
+# define DP_TEST_LINK_AUDIO_DISABLED_VIDEO  (1 << 6) /* DPCD >= 1.2 */
558647 
559648 #define DP_TEST_LINK_RATE		    0x219
560649 # define DP_LINK_RATE_162		    (0x6)
....@@ -603,6 +692,7 @@
603692 # define DP_COLOR_FORMAT_RGB                (0 << 1)
604693 # define DP_COLOR_FORMAT_YCbCr422           (1 << 1)
605694 # define DP_COLOR_FORMAT_YCbCr444           (2 << 1)
695
+# define DP_TEST_DYNAMIC_RANGE_VESA         (0 << 3)
606696 # define DP_TEST_DYNAMIC_RANGE_CEA          (1 << 3)
607697 # define DP_TEST_YCBCR_COEFFICIENTS         (1 << 4)
608698 # define DP_YCBCR_COEFFICIENTS_ITU601       (0 << 4)
....@@ -631,15 +721,16 @@
631721 # define DP_TEST_CRC_SUPPORTED		    (1 << 5)
632722 # define DP_TEST_COUNT_MASK		    0xf
633723 
634
-#define DP_TEST_PHY_PATTERN                 0x248
635
-# define DP_TEST_PHY_PATTERN_NONE			0x0
636
-# define DP_TEST_PHY_PATTERN_D10_2_NO_SCRAMBLING	0x1
637
-# define DP_TEST_PHY_PATTERN_SYMBOL_ERR_MEASUREMENT_CNT 0x2
638
-# define DP_TEST_PHY_PATTERN_PRBS7			0x3
639
-# define DP_TEST_PHY_PATTERN_80_BIT_CUSTOM_PATTERN	0x4
640
-# define DP_TEST_PHY_PATTERN_CP2520_PATTERN_1		0x5
641
-# define DP_TEST_PHY_PATTERN_CP2520_PATTERN_2		0x6
642
-# define DP_TEST_PHY_PATTERN_CP2520_PATTERN_3		0x7
724
+#define DP_PHY_TEST_PATTERN                 0x248
725
+# define DP_PHY_TEST_PATTERN_SEL_MASK       0x7
726
+# define DP_PHY_TEST_PATTERN_NONE           0x0
727
+# define DP_PHY_TEST_PATTERN_D10_2          0x1
728
+# define DP_PHY_TEST_PATTERN_ERROR_COUNT    0x2
729
+# define DP_PHY_TEST_PATTERN_PRBS7          0x3
730
+# define DP_PHY_TEST_PATTERN_80BIT_CUSTOM   0x4
731
+# define DP_PHY_TEST_PATTERN_CP2520         0x5
732
+
733
+#define DP_TEST_HBR2_SCRAMBLER_RESET        0x24A
643734 #define DP_TEST_80BIT_CUSTOM_PATTERN_7_0    0x250
644735 #define	DP_TEST_80BIT_CUSTOM_PATTERN_15_8   0x251
645736 #define	DP_TEST_80BIT_CUSTOM_PATTERN_23_16  0x252
....@@ -660,6 +751,16 @@
660751 
661752 #define DP_TEST_SINK			    0x270
662753 # define DP_TEST_SINK_START		    (1 << 0)
754
+#define DP_TEST_AUDIO_MODE		    0x271
755
+#define DP_TEST_AUDIO_PATTERN_TYPE	    0x272
756
+#define DP_TEST_AUDIO_PERIOD_CH1	    0x273
757
+#define DP_TEST_AUDIO_PERIOD_CH2	    0x274
758
+#define DP_TEST_AUDIO_PERIOD_CH3	    0x275
759
+#define DP_TEST_AUDIO_PERIOD_CH4	    0x276
760
+#define DP_TEST_AUDIO_PERIOD_CH5	    0x277
761
+#define DP_TEST_AUDIO_PERIOD_CH6	    0x278
762
+#define DP_TEST_AUDIO_PERIOD_CH7	    0x279
763
+#define DP_TEST_AUDIO_PERIOD_CH8	    0x27A
663764 
664765 #define DP_FEC_STATUS			    0x280    /* 1.4 */
665766 # define DP_FEC_DECODE_EN_DETECTED	    (1 << 0)
....@@ -697,6 +798,8 @@
697798 # define DP_EDP_12			    0x01
698799 # define DP_EDP_13			    0x02
699800 # define DP_EDP_14			    0x03
801
+# define DP_EDP_14a                         0x04    /* eDP 1.4a */
802
+# define DP_EDP_14b                         0x05    /* eDP 1.4b */
700803 
701804 #define DP_EDP_GENERAL_CAP_1		    0x701
702805 # define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP		(1 << 0)
....@@ -900,6 +1003,16 @@
9001003 #define DP_CEC_TX_MESSAGE_BUFFER               0x3020
9011004 #define DP_CEC_MESSAGE_BUFFER_LENGTH             0x10
9021005 
1006
+#define DP_PROTOCOL_CONVERTER_CONTROL_0		0x3050 /* DP 1.3 */
1007
+# define DP_HDMI_DVI_OUTPUT_CONFIG		(1 << 0) /* DP 1.3 */
1008
+#define DP_PROTOCOL_CONVERTER_CONTROL_1		0x3051 /* DP 1.3 */
1009
+# define DP_CONVERSION_TO_YCBCR420_ENABLE	(1 << 0) /* DP 1.3 */
1010
+# define DP_HDMI_EDID_PROCESSING_DISABLE	(1 << 1) /* DP 1.4 */
1011
+# define DP_HDMI_AUTONOMOUS_SCRAMBLING_DISABLE	(1 << 2) /* DP 1.4 */
1012
+# define DP_HDMI_FORCE_SCRAMBLING		(1 << 3) /* DP 1.4 */
1013
+#define DP_PROTOCOL_CONVERTER_CONTROL_2		0x3052 /* DP 1.3 */
1014
+# define DP_CONVERSION_TO_YCBCR422_ENABLE	(1 << 0) /* DP 1.3 */
1015
+
9031016 #define DP_AUX_HDCP_BKSV		0x68000
9041017 #define DP_AUX_HDCP_RI_PRIME		0x68005
9051018 #define DP_AUX_HDCP_AKSV		0x68007
....@@ -917,6 +1030,89 @@
9171030 #define DP_AUX_HDCP_KSV_FIFO		0x6802C
9181031 #define DP_AUX_HDCP_AINFO		0x6803B
9191032 
1033
+/* DP HDCP2.2 parameter offsets in DPCD address space */
1034
+#define DP_HDCP_2_2_REG_RTX_OFFSET		0x69000
1035
+#define DP_HDCP_2_2_REG_TXCAPS_OFFSET		0x69008
1036
+#define DP_HDCP_2_2_REG_CERT_RX_OFFSET		0x6900B
1037
+#define DP_HDCP_2_2_REG_RRX_OFFSET		0x69215
1038
+#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET		0x6921D
1039
+#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET		0x69220
1040
+#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET	0x692A0
1041
+#define DP_HDCP_2_2_REG_M_OFFSET		0x692B0
1042
+#define DP_HDCP_2_2_REG_HPRIME_OFFSET		0x692C0
1043
+#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET	0x692E0
1044
+#define DP_HDCP_2_2_REG_RN_OFFSET		0x692F0
1045
+#define DP_HDCP_2_2_REG_LPRIME_OFFSET		0x692F8
1046
+#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET		0x69318
1047
+#define	DP_HDCP_2_2_REG_RIV_OFFSET		0x69328
1048
+#define DP_HDCP_2_2_REG_RXINFO_OFFSET		0x69330
1049
+#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET	0x69332
1050
+#define DP_HDCP_2_2_REG_VPRIME_OFFSET		0x69335
1051
+#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET	0x69345
1052
+#define DP_HDCP_2_2_REG_V_OFFSET		0x693E0
1053
+#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET	0x693F0
1054
+#define DP_HDCP_2_2_REG_K_OFFSET		0x693F3
1055
+#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET	0x693F5
1056
+#define DP_HDCP_2_2_REG_MPRIME_OFFSET		0x69473
1057
+#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET		0x69493
1058
+#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET	0x69494
1059
+#define DP_HDCP_2_2_REG_DBG_OFFSET		0x69518
1060
+
1061
+/* Link Training (LT)-tunable PHY Repeaters */
1062
+#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */
1063
+#define DP_MAX_LINK_RATE_PHY_REPEATER			    0xf0001 /* 1.4a */
1064
+#define DP_PHY_REPEATER_CNT				    0xf0002 /* 1.3 */
1065
+#define DP_PHY_REPEATER_MODE				    0xf0003 /* 1.3 */
1066
+#define DP_MAX_LANE_COUNT_PHY_REPEATER			    0xf0004 /* 1.4a */
1067
+#define DP_Repeater_FEC_CAPABILITY			    0xf0004 /* 1.4 */
1068
+#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT		    0xf0005 /* 1.4a */
1069
+#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1		    0xf0010 /* 1.3 */
1070
+#define DP_TRAINING_LANE0_SET_PHY_REPEATER1		    0xf0011 /* 1.3 */
1071
+#define DP_TRAINING_LANE1_SET_PHY_REPEATER1		    0xf0012 /* 1.3 */
1072
+#define DP_TRAINING_LANE2_SET_PHY_REPEATER1		    0xf0013 /* 1.3 */
1073
+#define DP_TRAINING_LANE3_SET_PHY_REPEATER1		    0xf0014 /* 1.3 */
1074
+#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1	    0xf0020 /* 1.4a */
1075
+#define DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1		    0xf0021 /* 1.4a */
1076
+#define DP_LANE0_1_STATUS_PHY_REPEATER1			    0xf0030 /* 1.3 */
1077
+#define DP_LANE2_3_STATUS_PHY_REPEATER1			    0xf0031 /* 1.3 */
1078
+#define DP_LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER1	    0xf0032 /* 1.3 */
1079
+#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1		    0xf0033 /* 1.3 */
1080
+#define DP_ADJUST_REQUEST_LANE2_3_PHY_REPEATER1		    0xf0034 /* 1.3 */
1081
+#define DP_SYMBOL_ERROR_COUNT_LANE0_PHY_REPEATER1	    0xf0035 /* 1.3 */
1082
+#define DP_SYMBOL_ERROR_COUNT_LANE1_PHY_REPEATER1	    0xf0037 /* 1.3 */
1083
+#define DP_SYMBOL_ERROR_COUNT_LANE2_PHY_REPEATER1	    0xf0039 /* 1.3 */
1084
+#define DP_SYMBOL_ERROR_COUNT_LANE3_PHY_REPEATER1	    0xf003b /* 1.3 */
1085
+#define DP_FEC_STATUS_PHY_REPEATER1			    0xf0290 /* 1.4 */
1086
+#define DP_FEC_ERROR_COUNT_PHY_REPEATER1                    0xf0291 /* 1.4 */
1087
+#define DP_FEC_CAPABILITY_PHY_REPEATER1                     0xf0294 /* 1.4a */
1088
+
1089
+/* Repeater modes */
1090
+#define DP_PHY_REPEATER_MODE_TRANSPARENT		    0x55    /* 1.3 */
1091
+#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT		    0xaa    /* 1.3 */
1092
+
1093
+/* DP HDCP message start offsets in DPCD address space */
1094
+#define DP_HDCP_2_2_AKE_INIT_OFFSET		DP_HDCP_2_2_REG_RTX_OFFSET
1095
+#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET	DP_HDCP_2_2_REG_CERT_RX_OFFSET
1096
+#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET	DP_HDCP_2_2_REG_EKPUB_KM_OFFSET
1097
+#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET	DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET
1098
+#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET	DP_HDCP_2_2_REG_HPRIME_OFFSET
1099
+#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \
1100
+						DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET
1101
+#define DP_HDCP_2_2_LC_INIT_OFFSET		DP_HDCP_2_2_REG_RN_OFFSET
1102
+#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET	DP_HDCP_2_2_REG_LPRIME_OFFSET
1103
+#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET		DP_HDCP_2_2_REG_EDKEY_KS_OFFSET
1104
+#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET	DP_HDCP_2_2_REG_RXINFO_OFFSET
1105
+#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET		DP_HDCP_2_2_REG_V_OFFSET
1106
+#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET	DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET
1107
+#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET	DP_HDCP_2_2_REG_MPRIME_OFFSET
1108
+
1109
+#define HDCP_2_2_DP_RXSTATUS_LEN		1
1110
+#define HDCP_2_2_DP_RXSTATUS_READY(x)		((x) & BIT(0))
1111
+#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x)		((x) & BIT(1))
1112
+#define HDCP_2_2_DP_RXSTATUS_PAIRING(x)		((x) & BIT(2))
1113
+#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x)	((x) & BIT(3))
1114
+#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x)	((x) & BIT(4))
1115
+
9201116 /* DP 1.2 Sideband message defines */
9211117 /* peer device type - DP 1.2a Table 2-92 */
9221118 #define DP_PEER_DEVICE_NONE		0x0
....@@ -926,6 +1122,7 @@
9261122 #define DP_PEER_DEVICE_DP_LEGACY_CONV	0x4
9271123 
9281124 /* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
1125
+#define DP_GET_MSG_TRANSACTION_VERSION	0x00 /* DP 1.3 */
9291126 #define DP_LINK_ADDRESS			0x01
9301127 #define DP_CONNECTION_STATUS_NOTIFY	0x02
9311128 #define DP_ENUM_PATH_RESOURCES		0x10
....@@ -941,6 +1138,13 @@
9411138 #define DP_POWER_DOWN_PHY		0x25
9421139 #define DP_SINK_EVENT_NOTIFY		0x30
9431140 #define DP_QUERY_STREAM_ENC_STATUS	0x38
1141
+#define  DP_QUERY_STREAM_ENC_STATUS_STATE_NO_EXIST	0
1142
+#define  DP_QUERY_STREAM_ENC_STATUS_STATE_INACTIVE	1
1143
+#define  DP_QUERY_STREAM_ENC_STATUS_STATE_ACTIVE	2
1144
+
1145
+/* DP 1.2 MST sideband reply types */
1146
+#define DP_SIDEBAND_REPLY_ACK		0x00
1147
+#define DP_SIDEBAND_REPLY_NAK		0x01
9441148 
9451149 /* DP 1.2 MST sideband nak reasons - table 2.84 */
9461150 #define DP_NAK_WRITE_FAILURE		0x01
....@@ -963,6 +1167,7 @@
9631167 #define DP_MST_PHYSICAL_PORT_0 0
9641168 #define DP_MST_LOGICAL_PORT_0 8
9651169 
1170
+#define DP_LINK_CONSTANT_N_VALUE 0x8000
9661171 #define DP_LINK_STATUS_SIZE	   6
9671172 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
9681173 			  int lane_count);
....@@ -972,6 +1177,8 @@
9721177 				     int lane);
9731178 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
9741179 					  int lane);
1180
+u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
1181
+					 unsigned int lane);
9751182 
9761183 #define DP_BRANCH_OUI_HEADER_SIZE	0xc
9771184 #define DP_RECEIVER_CAP_SIZE		0xf
....@@ -1015,22 +1222,168 @@
10151222 #define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES	0x1F
10161223 #define DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 0x7F
10171224 
1018
-struct edp_vsc_psr {
1225
+/**
1226
+ * struct dp_sdp - DP secondary data packet
1227
+ * @sdp_header: DP secondary data packet header
1228
+ * @db: DP secondaray data packet data blocks
1229
+ * VSC SDP Payload for PSR
1230
+ * db[0]: Stereo Interface
1231
+ * db[1]: 0 - PSR State; 1 - Update RFB; 2 - CRC Valid
1232
+ * db[2]: CRC value bits 7:0 of the R or Cr component
1233
+ * db[3]: CRC value bits 15:8 of the R or Cr component
1234
+ * db[4]: CRC value bits 7:0 of the G or Y component
1235
+ * db[5]: CRC value bits 15:8 of the G or Y component
1236
+ * db[6]: CRC value bits 7:0 of the B or Cb component
1237
+ * db[7]: CRC value bits 15:8 of the B or Cb component
1238
+ * db[8] - db[31]: Reserved
1239
+ * VSC SDP Payload for Pixel Encoding/Colorimetry Format
1240
+ * db[0] - db[15]: Reserved
1241
+ * db[16]: Pixel Encoding and Colorimetry Formats
1242
+ * db[17]: Dynamic Range and Component Bit Depth
1243
+ * db[18]: Content Type
1244
+ * db[19] - db[31]: Reserved
1245
+ */
1246
+struct dp_sdp {
10191247 	struct dp_sdp_header sdp_header;
1020
-	u8 DB0; /* Stereo Interface */
1021
-	u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
1022
-	u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
1023
-	u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
1024
-	u8 DB4; /* CRC value bits 7:0 of the G or Y component */
1025
-	u8 DB5; /* CRC value bits 15:8 of the G or Y component */
1026
-	u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
1027
-	u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
1028
-	u8 DB8_31[24]; /* Reserved */
1248
+	u8 db[32];
10291249 } __packed;
10301250 
10311251 #define EDP_VSC_PSR_STATE_ACTIVE	(1<<0)
10321252 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
10331253 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
1254
+
1255
+/**
1256
+ * enum dp_pixelformat - drm DP Pixel encoding formats
1257
+ *
1258
+ * This enum is used to indicate DP VSC SDP Pixel encoding formats.
1259
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1260
+ * DB18]
1261
+ *
1262
+ * @DP_PIXELFORMAT_RGB: RGB pixel encoding format
1263
+ * @DP_PIXELFORMAT_YUV444: YCbCr 4:4:4 pixel encoding format
1264
+ * @DP_PIXELFORMAT_YUV422: YCbCr 4:2:2 pixel encoding format
1265
+ * @DP_PIXELFORMAT_YUV420: YCbCr 4:2:0 pixel encoding format
1266
+ * @DP_PIXELFORMAT_Y_ONLY: Y Only pixel encoding format
1267
+ * @DP_PIXELFORMAT_RAW: RAW pixel encoding format
1268
+ * @DP_PIXELFORMAT_RESERVED: Reserved pixel encoding format
1269
+ */
1270
+enum dp_pixelformat {
1271
+	DP_PIXELFORMAT_RGB = 0,
1272
+	DP_PIXELFORMAT_YUV444 = 0x1,
1273
+	DP_PIXELFORMAT_YUV422 = 0x2,
1274
+	DP_PIXELFORMAT_YUV420 = 0x3,
1275
+	DP_PIXELFORMAT_Y_ONLY = 0x4,
1276
+	DP_PIXELFORMAT_RAW = 0x5,
1277
+	DP_PIXELFORMAT_RESERVED = 0x6,
1278
+};
1279
+
1280
+/**
1281
+ * enum dp_colorimetry - drm DP Colorimetry formats
1282
+ *
1283
+ * This enum is used to indicate DP VSC SDP Colorimetry formats.
1284
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1285
+ * DB18] and a name of enum member follows DRM_MODE_COLORIMETRY definition.
1286
+ *
1287
+ * @DP_COLORIMETRY_DEFAULT: sRGB (IEC 61966-2-1) or
1288
+ *                          ITU-R BT.601 colorimetry format
1289
+ * @DP_COLORIMETRY_RGB_WIDE_FIXED: RGB wide gamut fixed point colorimetry format
1290
+ * @DP_COLORIMETRY_BT709_YCC: ITU-R BT.709 colorimetry format
1291
+ * @DP_COLORIMETRY_RGB_WIDE_FLOAT: RGB wide gamut floating point
1292
+ *                                 (scRGB (IEC 61966-2-2)) colorimetry format
1293
+ * @DP_COLORIMETRY_XVYCC_601: xvYCC601 colorimetry format
1294
+ * @DP_COLORIMETRY_OPRGB: OpRGB colorimetry format
1295
+ * @DP_COLORIMETRY_XVYCC_709: xvYCC709 colorimetry format
1296
+ * @DP_COLORIMETRY_DCI_P3_RGB: DCI-P3 (SMPTE RP 431-2) colorimetry format
1297
+ * @DP_COLORIMETRY_SYCC_601: sYCC601 colorimetry format
1298
+ * @DP_COLORIMETRY_RGB_CUSTOM: RGB Custom Color Profile colorimetry format
1299
+ * @DP_COLORIMETRY_OPYCC_601: opYCC601 colorimetry format
1300
+ * @DP_COLORIMETRY_BT2020_RGB: ITU-R BT.2020 R' G' B' colorimetry format
1301
+ * @DP_COLORIMETRY_BT2020_CYCC: ITU-R BT.2020 Y'c C'bc C'rc colorimetry format
1302
+ * @DP_COLORIMETRY_BT2020_YCC: ITU-R BT.2020 Y' C'b C'r colorimetry format
1303
+ */
1304
+enum dp_colorimetry {
1305
+	DP_COLORIMETRY_DEFAULT = 0,
1306
+	DP_COLORIMETRY_RGB_WIDE_FIXED = 0x1,
1307
+	DP_COLORIMETRY_BT709_YCC = 0x1,
1308
+	DP_COLORIMETRY_RGB_WIDE_FLOAT = 0x2,
1309
+	DP_COLORIMETRY_XVYCC_601 = 0x2,
1310
+	DP_COLORIMETRY_OPRGB = 0x3,
1311
+	DP_COLORIMETRY_XVYCC_709 = 0x3,
1312
+	DP_COLORIMETRY_DCI_P3_RGB = 0x4,
1313
+	DP_COLORIMETRY_SYCC_601 = 0x4,
1314
+	DP_COLORIMETRY_RGB_CUSTOM = 0x5,
1315
+	DP_COLORIMETRY_OPYCC_601 = 0x5,
1316
+	DP_COLORIMETRY_BT2020_RGB = 0x6,
1317
+	DP_COLORIMETRY_BT2020_CYCC = 0x6,
1318
+	DP_COLORIMETRY_BT2020_YCC = 0x7,
1319
+};
1320
+
1321
+/**
1322
+ * enum dp_dynamic_range - drm DP Dynamic Range
1323
+ *
1324
+ * This enum is used to indicate DP VSC SDP Dynamic Range.
1325
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1326
+ * DB18]
1327
+ *
1328
+ * @DP_DYNAMIC_RANGE_VESA: VESA range
1329
+ * @DP_DYNAMIC_RANGE_CTA: CTA range
1330
+ */
1331
+enum dp_dynamic_range {
1332
+	DP_DYNAMIC_RANGE_VESA = 0,
1333
+	DP_DYNAMIC_RANGE_CTA = 1,
1334
+};
1335
+
1336
+/**
1337
+ * enum dp_content_type - drm DP Content Type
1338
+ *
1339
+ * This enum is used to indicate DP VSC SDP Content Types.
1340
+ * It is based on DP 1.4 spec [Table 2-117: VSC SDP Payload for DB16 through
1341
+ * DB18]
1342
+ * CTA-861-G defines content types and expected processing by a sink device
1343
+ *
1344
+ * @DP_CONTENT_TYPE_NOT_DEFINED: Not defined type
1345
+ * @DP_CONTENT_TYPE_GRAPHICS: Graphics type
1346
+ * @DP_CONTENT_TYPE_PHOTO: Photo type
1347
+ * @DP_CONTENT_TYPE_VIDEO: Video type
1348
+ * @DP_CONTENT_TYPE_GAME: Game type
1349
+ */
1350
+enum dp_content_type {
1351
+	DP_CONTENT_TYPE_NOT_DEFINED = 0x00,
1352
+	DP_CONTENT_TYPE_GRAPHICS = 0x01,
1353
+	DP_CONTENT_TYPE_PHOTO = 0x02,
1354
+	DP_CONTENT_TYPE_VIDEO = 0x03,
1355
+	DP_CONTENT_TYPE_GAME = 0x04,
1356
+};
1357
+
1358
+/**
1359
+ * struct drm_dp_vsc_sdp - drm DP VSC SDP
1360
+ *
1361
+ * This structure represents a DP VSC SDP of drm
1362
+ * It is based on DP 1.4 spec [Table 2-116: VSC SDP Header Bytes] and
1363
+ * [Table 2-117: VSC SDP Payload for DB16 through DB18]
1364
+ *
1365
+ * @sdp_type: secondary-data packet type
1366
+ * @revision: revision number
1367
+ * @length: number of valid data bytes
1368
+ * @pixelformat: pixel encoding format
1369
+ * @colorimetry: colorimetry format
1370
+ * @bpc: bit per color
1371
+ * @dynamic_range: dynamic range information
1372
+ * @content_type: CTA-861-G defines content types and expected processing by a sink device
1373
+ */
1374
+struct drm_dp_vsc_sdp {
1375
+	unsigned char sdp_type;
1376
+	unsigned char revision;
1377
+	unsigned char length;
1378
+	enum dp_pixelformat pixelformat;
1379
+	enum dp_colorimetry colorimetry;
1380
+	int bpc;
1381
+	enum dp_dynamic_range dynamic_range;
1382
+	enum dp_content_type content_type;
1383
+};
1384
+
1385
+void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
1386
+			const struct drm_dp_vsc_sdp *vsc);
10341387 
10351388 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]);
10361389 
....@@ -1051,6 +1404,13 @@
10511404 {
10521405 	return dpcd[DP_DPCD_REV] >= 0x11 &&
10531406 		(dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP);
1407
+}
1408
+
1409
+static inline bool
1410
+drm_dp_fast_training_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1411
+{
1412
+	return dpcd[DP_DPCD_REV] >= 0x11 &&
1413
+		(dpcd[DP_MAX_DOWNSPREAD] & DP_NO_AUX_HANDSHAKE_LINK_TRAINING);
10541414 }
10551415 
10561416 static inline bool
....@@ -1111,6 +1471,34 @@
11111471 		DP_DSC_SLICE_WIDTH_MULTIPLIER;
11121472 }
11131473 
1474
+/* Forward Error Correction Support on DP 1.4 */
1475
+static inline bool
1476
+drm_dp_sink_supports_fec(const u8 fec_capable)
1477
+{
1478
+	return fec_capable & DP_FEC_CAPABLE;
1479
+}
1480
+
1481
+static inline bool
1482
+drm_dp_channel_coding_supported(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1483
+{
1484
+	return dpcd[DP_MAIN_LINK_CHANNEL_CODING] & DP_CAP_ANSI_8B10B;
1485
+}
1486
+
1487
+static inline bool
1488
+drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1489
+{
1490
+	return dpcd[DP_EDP_CONFIGURATION_CAP] &
1491
+			DP_ALTERNATE_SCRAMBLER_RESET_CAP;
1492
+}
1493
+
1494
+/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
1495
+static inline bool
1496
+drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1497
+{
1498
+	return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
1499
+		DP_MSA_TIMING_PAR_IGNORED;
1500
+}
1501
+
11141502 /*
11151503  * DisplayPort AUX channel
11161504  */
....@@ -1133,20 +1521,19 @@
11331521 
11341522 struct cec_adapter;
11351523 struct edid;
1524
+struct drm_connector;
11361525 
11371526 /**
11381527  * struct drm_dp_aux_cec - DisplayPort CEC-Tunneling-over-AUX
11391528  * @lock: mutex protecting this struct
11401529  * @adap: the CEC adapter for CEC-Tunneling-over-AUX support.
1141
- * @name: name of the CEC adapter
1142
- * @parent: parent device of the CEC adapter
1530
+ * @connector: the connector this CEC adapter is associated with
11431531  * @unregister_work: unregister the CEC adapter
11441532  */
11451533 struct drm_dp_aux_cec {
11461534 	struct mutex lock;
11471535 	struct cec_adapter *adap;
1148
-	const char *name;
1149
-	struct device *parent;
1536
+	struct drm_connector *connector;
11501537 	struct delayed_work unregister_work;
11511538 };
11521539 
....@@ -1196,7 +1583,6 @@
11961583 	struct device *dev;
11971584 	struct drm_crtc *crtc;
11981585 	struct mutex hw_mutex;
1199
-	struct mutex i2c_mutex;
12001586 	struct work_struct crc_work;
12011587 	u8 crc_count;
12021588 	ssize_t (*transfer)(struct drm_dp_aux *aux,
....@@ -1213,6 +1599,10 @@
12131599 	 * @cec: struct containing fields used for CEC-Tunneling-over-AUX.
12141600 	 */
12151601 	struct drm_dp_aux_cec cec;
1602
+	/**
1603
+	 * @is_remote: Is this AUX CH actually using sideband messaging.
1604
+	 */
1605
+	bool is_remote;
12161606 };
12171607 
12181608 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
....@@ -1250,33 +1640,62 @@
12501640 	return drm_dp_dpcd_write(aux, offset, &value, 1);
12511641 }
12521642 
1643
+int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
1644
+			  u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1645
+
12531646 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
12541647 				 u8 status[DP_LINK_STATUS_SIZE]);
12551648 
1256
-/*
1257
- * DisplayPort link
1258
- */
1259
-#define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0)
1649
+bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
1650
+				    u8 real_edid_checksum);
12601651 
1261
-struct drm_dp_link {
1262
-	unsigned char revision;
1263
-	unsigned int rate;
1264
-	unsigned int num_lanes;
1265
-	unsigned long capabilities;
1266
-};
1267
-
1268
-int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
1269
-int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
1270
-int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
1271
-int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
1272
-int drm_dp_downstream_max_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1273
-				const u8 port_cap[4]);
1652
+int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
1653
+				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1654
+				u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]);
1655
+bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1656
+			       const u8 port_cap[4], u8 type);
1657
+bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1658
+			       const u8 port_cap[4],
1659
+			       const struct edid *edid);
1660
+int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1661
+				   const u8 port_cap[4]);
1662
+int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1663
+				     const u8 port_cap[4],
1664
+				     const struct edid *edid);
1665
+int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1666
+				     const u8 port_cap[4],
1667
+				     const struct edid *edid);
12741668 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1275
-			      const u8 port_cap[4]);
1669
+			      const u8 port_cap[4],
1670
+			      const struct edid *edid);
1671
+bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1672
+				       const u8 port_cap[4]);
1673
+bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1674
+					     const u8 port_cap[4]);
1675
+struct drm_display_mode *drm_dp_downstream_mode(struct drm_device *dev,
1676
+						const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1677
+						const u8 port_cap[4]);
12761678 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]);
1277
-void drm_dp_downstream_debug(struct seq_file *m, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1278
-			     const u8 port_cap[4], struct drm_dp_aux *aux);
1679
+void drm_dp_downstream_debug(struct seq_file *m,
1680
+			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1681
+			     const u8 port_cap[4],
1682
+			     const struct edid *edid,
1683
+			     struct drm_dp_aux *aux);
1684
+enum drm_mode_subconnector
1685
+drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1686
+			 const u8 port_cap[4]);
1687
+void drm_dp_set_subconnector_property(struct drm_connector *connector,
1688
+				      enum drm_connector_status status,
1689
+				      const u8 *dpcd,
1690
+				      const u8 port_cap[4]);
12791691 
1692
+struct drm_dp_desc;
1693
+bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1694
+				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1695
+				const struct drm_dp_desc *desc);
1696
+int drm_dp_read_sink_count(struct drm_dp_aux *aux);
1697
+
1698
+void drm_dp_remote_aux_init(struct drm_dp_aux *aux);
12801699 void drm_dp_aux_init(struct drm_dp_aux *aux);
12811700 int drm_dp_aux_register(struct drm_dp_aux *aux);
12821701 void drm_dp_aux_unregister(struct drm_dp_aux *aux);
....@@ -1304,41 +1723,85 @@
13041723 
13051724 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
13061725 		     bool is_branch);
1726
+u32 drm_dp_get_edid_quirks(const struct edid *edid);
13071727 
13081728 /**
13091729  * enum drm_dp_quirk - Display Port sink/branch device specific quirks
13101730  *
13111731  * Display Port sink and branch devices in the wild have a variety of bugs, try
13121732  * to collect them here. The quirks are shared, but it's up to the drivers to
1313
- * implement workarounds for them.
1733
+ * implement workarounds for them. Note that because some devices have
1734
+ * unreliable OUIDs, the EDID of sinks should also be checked for quirks using
1735
+ * drm_dp_get_edid_quirks().
13141736  */
13151737 enum drm_dp_quirk {
13161738 	/**
1317
-	 * @DP_DPCD_QUIRK_LIMITED_M_N:
1739
+	 * @DP_DPCD_QUIRK_CONSTANT_N:
13181740 	 *
13191741 	 * The device requires main link attributes Mvid and Nvid to be limited
1320
-	 * to 16 bits.
1742
+	 * to 16 bits. So will give a constant value (0x8000) for compatability.
13211743 	 */
1322
-	DP_DPCD_QUIRK_LIMITED_M_N,
1744
+	DP_DPCD_QUIRK_CONSTANT_N,
1745
+	/**
1746
+	 * @DP_DPCD_QUIRK_NO_PSR:
1747
+	 *
1748
+	 * The device does not support PSR even if reports that it supports or
1749
+	 * driver still need to implement proper handling for such device.
1750
+	 */
1751
+	DP_DPCD_QUIRK_NO_PSR,
1752
+	/**
1753
+	 * @DP_DPCD_QUIRK_NO_SINK_COUNT:
1754
+	 *
1755
+	 * The device does not set SINK_COUNT to a non-zero value.
1756
+	 * The driver should ignore SINK_COUNT during detection. Note that
1757
+	 * drm_dp_read_sink_count_cap() automatically checks for this quirk.
1758
+	 */
1759
+	DP_DPCD_QUIRK_NO_SINK_COUNT,
1760
+	/**
1761
+	 * @DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD:
1762
+	 *
1763
+	 * The device supports MST DSC despite not supporting Virtual DPCD.
1764
+	 * The DSC caps can be read from the physical aux instead.
1765
+	 */
1766
+	DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD,
1767
+	/**
1768
+	 * @DP_QUIRK_FORCE_DPCD_BACKLIGHT:
1769
+	 *
1770
+	 * The device is telling the truth when it says that it uses DPCD
1771
+	 * backlight controls, even if the system's firmware disagrees. This
1772
+	 * quirk should be checked against both the ident and panel EDID.
1773
+	 * When present, the driver should honor the DPCD backlight
1774
+	 * capabilities advertised.
1775
+	 */
1776
+	DP_QUIRK_FORCE_DPCD_BACKLIGHT,
1777
+	/**
1778
+	 * @DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS:
1779
+	 *
1780
+	 * The device supports a link rate of 3.24 Gbps (multiplier 0xc) despite
1781
+	 * the DP_MAX_LINK_RATE register reporting a lower max multiplier.
1782
+	 */
1783
+	DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS,
13231784 };
13241785 
13251786 /**
13261787  * drm_dp_has_quirk() - does the DP device have a specific quirk
1327
- * @desc: Device decriptor filled by drm_dp_read_desc()
1788
+ * @desc: Device descriptor filled by drm_dp_read_desc()
1789
+ * @edid_quirks: Optional quirk bitmask filled by drm_dp_get_edid_quirks()
13281790  * @quirk: Quirk to query for
13291791  *
13301792  * Return true if DP device identified by @desc has @quirk.
13311793  */
13321794 static inline bool
1333
-drm_dp_has_quirk(const struct drm_dp_desc *desc, enum drm_dp_quirk quirk)
1795
+drm_dp_has_quirk(const struct drm_dp_desc *desc, u32 edid_quirks,
1796
+		 enum drm_dp_quirk quirk)
13341797 {
1335
-	return desc->quirks & BIT(quirk);
1798
+	return (desc->quirks | edid_quirks) & BIT(quirk);
13361799 }
13371800 
13381801 #ifdef CONFIG_DRM_DP_CEC
13391802 void drm_dp_cec_irq(struct drm_dp_aux *aux);
1340
-void drm_dp_cec_register_connector(struct drm_dp_aux *aux, const char *name,
1341
-				   struct device *parent);
1803
+void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1804
+				   struct drm_connector *connector);
13421805 void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux);
13431806 void drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid);
13441807 void drm_dp_cec_unset_edid(struct drm_dp_aux *aux);
....@@ -1347,9 +1810,9 @@
13471810 {
13481811 }
13491812 
1350
-static inline void drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1351
-						 const char *name,
1352
-						 struct device *parent)
1813
+static inline void
1814
+drm_dp_cec_register_connector(struct drm_dp_aux *aux,
1815
+			      struct drm_connector *connector)
13531816 {
13541817 }
13551818 
....@@ -1368,4 +1831,26 @@
13681831 
13691832 #endif
13701833 
1834
+/**
1835
+ * struct drm_dp_phy_test_params - DP Phy Compliance parameters
1836
+ * @link_rate: Requested Link rate from DPCD 0x219
1837
+ * @num_lanes: Number of lanes requested by sing through DPCD 0x220
1838
+ * @phy_pattern: DP Phy test pattern from DPCD 0x248
1839
+ * @hbr2_reset: DP HBR2_COMPLIANCE_SCRAMBLER_RESET from DCPD 0x24A and 0x24B
1840
+ * @custom80: DP Test_80BIT_CUSTOM_PATTERN from DPCDs 0x250 through 0x259
1841
+ * @enhanced_frame_cap: flag for enhanced frame capability.
1842
+ */
1843
+struct drm_dp_phy_test_params {
1844
+	int link_rate;
1845
+	u8 num_lanes;
1846
+	u8 phy_pattern;
1847
+	u8 hbr2_reset[2];
1848
+	u8 custom80[10];
1849
+	bool enhanced_frame_cap;
1850
+};
1851
+
1852
+int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
1853
+				struct drm_dp_phy_test_params *data);
1854
+int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
1855
+				struct drm_dp_phy_test_params *data, u8 dp_rev);
13711856 #endif /* _DRM_DP_HELPER_H_ */