add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/drivers/pinctrl/tegra/pinctrl-tegra.c
..
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * Driver for the NVIDIA Tegra pinmux
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  *
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@@ -7,15 +8,6 @@
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  * Copyright (C) 2010 Google, Inc.
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  * Copyright (C) 2010 NVIDIA Corporation
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  * Copyright (C) 2009-2011 ST-Ericsson AB
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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- * more details.
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  */
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12
 
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 #include <linux/err.h>
..
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@@ -283,18 +275,64 @@
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 	return 0;
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 }
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277
 
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+static int tegra_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
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+					     struct pinctrl_gpio_range *range,
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+					     unsigned int offset)
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+{
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+	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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+	const struct tegra_pingroup *group;
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+	u32 value;
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+
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+	if (!pmx->soc->sfsel_in_mux)
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+		return 0;
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+
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+	group = &pmx->soc->groups[offset];
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+
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+	if (group->mux_reg < 0 || group->sfsel_bit < 0)
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+		return -EINVAL;
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+
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+	value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
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+	value &= ~BIT(group->sfsel_bit);
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+	pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
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+
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+	return 0;
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+}
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+
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+static void tegra_pinctrl_gpio_disable_free(struct pinctrl_dev *pctldev,
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+					    struct pinctrl_gpio_range *range,
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+					    unsigned int offset)
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+{
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+	struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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+	const struct tegra_pingroup *group;
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+	u32 value;
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+
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+	if (!pmx->soc->sfsel_in_mux)
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+		return;
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+
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+	group = &pmx->soc->groups[offset];
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+
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+	if (group->mux_reg < 0 || group->sfsel_bit < 0)
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+		return;
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+
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+	value = pmx_readl(pmx, group->mux_bank, group->mux_reg);
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+	value |= BIT(group->sfsel_bit);
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+	pmx_writel(pmx, value, group->mux_bank, group->mux_reg);
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+}
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+
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 static const struct pinmux_ops tegra_pinmux_ops = {
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 	.get_functions_count = tegra_pinctrl_get_funcs_count,
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 	.get_function_name = tegra_pinctrl_get_func_name,
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 	.get_function_groups = tegra_pinctrl_get_func_groups,
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 	.set_mux = tegra_pinctrl_set_mux,
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+	.gpio_request_enable = tegra_pinctrl_gpio_request_enable,
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+	.gpio_disable_free = tegra_pinctrl_gpio_disable_free,
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 };
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 static int tegra_pinconf_reg(struct tegra_pmx *pmx,
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 			     const struct tegra_pingroup *g,
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 			     enum tegra_pinconf_param param,
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 			     bool report_err,
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-			     s8 *bank, s16 *reg, s8 *bit, s8 *width)
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+			     s8 *bank, s32 *reg, s8 *bit, s8 *width)
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 {
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 	switch (param) {
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 	case TEGRA_PINCONF_PARAM_PULL:
..
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@@ -453,7 +491,7 @@
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 	const struct tegra_pingroup *g;
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 	int ret;
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 	s8 bank, bit, width;
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-	s16 reg;
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+	s32 reg;
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 	u32 val, mask;
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 	g = &pmx->soc->groups[group];
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@@ -482,7 +520,7 @@
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 	const struct tegra_pingroup *g;
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 	int ret, i;
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 	s8 bank, bit, width;
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-	s16 reg;
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+	s32 reg;
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 	u32 val, mask;
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 	g = &pmx->soc->groups[group];
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@@ -550,7 +588,7 @@
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 	const struct tegra_pingroup *g;
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 	int i, ret;
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 	s8 bank, bit, width;
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-	s16 reg;
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+	s32 reg;
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 	u32 val;
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 	g = &pmx->soc->groups[group];
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@@ -623,20 +661,86 @@
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 	for (i = 0; i < pmx->soc->ngroups; ++i) {
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 		g = &pmx->soc->groups[i];
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-		if (g->parked_bit >= 0) {
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-			val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
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-			val &= ~(1 << g->parked_bit);
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-			pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
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+		if (g->parked_bitmask > 0) {
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+			unsigned int bank, reg;
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+
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+			if (g->mux_reg != -1) {
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+				bank = g->mux_bank;
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+				reg = g->mux_reg;
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+			} else {
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+				bank = g->drv_bank;
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+				reg = g->drv_reg;
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+			}
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+
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+			val = pmx_readl(pmx, bank, reg);
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+			val &= ~g->parked_bitmask;
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+			pmx_writel(pmx, val, bank, reg);
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 		}
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 	}
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 }
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-static bool gpio_node_has_range(const char *compatible)
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+static size_t tegra_pinctrl_get_bank_size(struct device *dev,
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+					  unsigned int bank_id)
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+{
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+	struct platform_device *pdev = to_platform_device(dev);
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+	struct resource *res;
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+
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+	res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
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+
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+	return resource_size(res) / 4;
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+}
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+
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+static int tegra_pinctrl_suspend(struct device *dev)
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+{
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+	struct tegra_pmx *pmx = dev_get_drvdata(dev);
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+	u32 *backup_regs = pmx->backup_regs;
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+	u32 __iomem *regs;
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+	size_t bank_size;
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+	unsigned int i, k;
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+
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+	for (i = 0; i < pmx->nbanks; i++) {
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+		bank_size = tegra_pinctrl_get_bank_size(dev, i);
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+		regs = pmx->regs[i];
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+		for (k = 0; k < bank_size; k++)
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+			*backup_regs++ = readl_relaxed(regs++);
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+	}
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+
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+	return pinctrl_force_sleep(pmx->pctl);
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+}
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+
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+static int tegra_pinctrl_resume(struct device *dev)
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+{
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+	struct tegra_pmx *pmx = dev_get_drvdata(dev);
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+	u32 *backup_regs = pmx->backup_regs;
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+	u32 __iomem *regs;
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+	size_t bank_size;
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+	unsigned int i, k;
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+
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+	for (i = 0; i < pmx->nbanks; i++) {
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+		bank_size = tegra_pinctrl_get_bank_size(dev, i);
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+		regs = pmx->regs[i];
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+		for (k = 0; k < bank_size; k++)
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+			writel_relaxed(*backup_regs++, regs++);
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+	}
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+
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+	/* flush all the prior writes */
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+	readl_relaxed(pmx->regs[0]);
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+	/* wait for pinctrl register read to complete */
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+	rmb();
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+	return 0;
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+}
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+
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+const struct dev_pm_ops tegra_pinctrl_pm = {
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+	.suspend_noirq = &tegra_pinctrl_suspend,
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+	.resume_noirq = &tegra_pinctrl_resume
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+};
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+
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+static bool tegra_pinctrl_gpio_node_has_range(struct tegra_pmx *pmx)
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 {
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 	struct device_node *np;
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 	bool has_prop = false;
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742
 
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-	np = of_find_compatible_node(NULL, NULL, compatible);
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+	np = of_find_compatible_node(NULL, NULL, pmx->soc->gpio_compatible);
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 	if (!np)
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 		return has_prop;
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746
 
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@@ -655,6 +759,7 @@
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 	int i;
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 	const char **group_pins;
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 	int fn, gn, gfn;
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+	unsigned long backup_regs_size = 0;
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 	pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
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 	if (!pmx)
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@@ -707,6 +812,7 @@
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 		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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 		if (!res)
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 			break;
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+		backup_regs_size += resource_size(res);
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 	}
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 	pmx->nbanks = i;
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818
 
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@@ -715,9 +821,13 @@
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 	if (!pmx->regs)
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 		return -ENOMEM;
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823
 
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+	pmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,
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+					GFP_KERNEL);
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+	if (!pmx->backup_regs)
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+		return -ENOMEM;
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+
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 	for (i = 0; i < pmx->nbanks; i++) {
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-		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
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-		pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
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+		pmx->regs[i] = devm_platform_ioremap_resource(pdev, i);
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 		if (IS_ERR(pmx->regs[i]))
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 			return PTR_ERR(pmx->regs[i]);
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 	}
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@@ -730,7 +840,7 @@
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 	tegra_pinctrl_clear_parked_bits(pmx);
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842
 
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-	if (!gpio_node_has_range(pmx->soc->gpio_compatible))
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+	if (pmx->soc->ngpios > 0 && !tegra_pinctrl_gpio_node_has_range(pmx))
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 		pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
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 	platform_set_drvdata(pdev, pmx);
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@@ -739,4 +849,3 @@
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849
 
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 	return 0;
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 }
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-EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);