add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/drivers/pinctrl/qcom/pinctrl-msm.h
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@@ -1,14 +1,6 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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 /*
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  * Copyright (c) 2013, Sony Mobile Communications AB.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 and
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- * only version 2 as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope that it will be useful,
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- * but WITHOUT ANY WARRANTY; without even the implied warranty of
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- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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- * GNU General Public License for more details.
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  */
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 #ifndef __PINCTRL_MSM_H__
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 #define __PINCTRL_MSM_H__
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@@ -46,6 +38,7 @@
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  * @mux_bit:              Offset in @ctl_reg for the pinmux function selection.
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  * @pull_bit:             Offset in @ctl_reg for the bias configuration.
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  * @drv_bit:              Offset in @ctl_reg for the drive strength configuration.
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+ * @od_bit:               Offset in @ctl_reg for controlling open drain.
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  * @oe_bit:               Offset in @ctl_reg for controlling output enable.
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  * @in_bit:               Offset in @io_reg for the input bit value.
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  * @out_bit:              Offset in @io_reg for the output bit value.
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@@ -76,11 +69,14 @@
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 	u32 intr_status_reg;
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 	u32 intr_target_reg;
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+	unsigned int tile:2;
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+
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 	unsigned mux_bit:5;
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 	unsigned pull_bit:5;
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 	unsigned drv_bit:5;
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+	unsigned od_bit:5;
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 	unsigned oe_bit:5;
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 	unsigned in_bit:5;
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 	unsigned out_bit:5;
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@@ -98,6 +94,16 @@
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 };
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 /**
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+ * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
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+ * @gpio:          The GPIOs that are wakeup capable
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+ * @wakeirq:       The interrupt at the always-on interrupt controller
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+ */
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+struct msm_gpio_wakeirq_map {
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+	unsigned int gpio;
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+	unsigned int wakeirq;
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+};
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+
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+/**
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  * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
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  * @pins:	    An array describing all pins the pin controller affects.
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  * @npins:	    The number of entries in @pins.
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@@ -107,6 +113,12 @@
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  * @ngroups:	    The numbmer of entries in @groups.
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  * @ngpio:	    The number of pingroups the driver should expose as GPIOs.
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  * @pull_no_keeper: The SoC does not support keeper bias.
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+ * @wakeirq_map:    The map of wakeup capable GPIOs and the pin at PDC/MPM
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+ * @nwakeirq_map:   The number of entries in @wakeirq_map
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+ * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need
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+ *                            to be aware that their parent can't handle dual
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+ *                            edge interrupts.
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+ * @gpio_func: Which function number is GPIO (usually 0).
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  */
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 struct msm_pinctrl_soc_data {
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 	const struct pinctrl_pin_desc *pins;
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@@ -117,8 +129,17 @@
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 	unsigned ngroups;
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 	unsigned ngpios;
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 	bool pull_no_keeper;
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+	const char *const *tiles;
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+	unsigned int ntiles;
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+	const int *reserved_gpios;
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+	const struct msm_gpio_wakeirq_map *wakeirq_map;
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+	unsigned int nwakeirq_map;
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+	bool wakeirq_dual_edge_errata;
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+	unsigned int gpio_func;
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 };
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+extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
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+
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 int msm_pinctrl_probe(struct platform_device *pdev,
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 		      const struct msm_pinctrl_soc_data *soc_data);
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 int msm_pinctrl_remove(struct platform_device *pdev);