~hc/RK356X_SDK_RELEASE.git

..	..	@@ -295,6 +295,7 @@
295	295	MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
296	296	MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
297	297	MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
	298	+ MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC,
298	299	};
299	300
300	301	/* reg_sfd_rec_type
..	..	@@ -525,6 +526,61 @@
525	526	mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
526	527	}
527	528
	529	+/* reg_sfd_uc_tunnel_uip_msb
	530	+ * When protocol is IPv4, the most significant byte of the underlay IPv4
	531	+ * destination IP.
	532	+ * When protocol is IPv6, reserved.
	533	+ * Access: RW
	534	+ */
	535	+MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24,
	536	+ 8, MLXSW_REG_SFD_REC_LEN, 0x08, false);
	537	+
	538	+/* reg_sfd_uc_tunnel_fid
	539	+ * Filtering ID.
	540	+ * Access: Index
	541	+ */
	542	+MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
	543	+ MLXSW_REG_SFD_REC_LEN, 0x08, false);
	544	+
	545	+enum mlxsw_reg_sfd_uc_tunnel_protocol {
	546	+ MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4,
	547	+ MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6,
	548	+};
	549	+
	550	+/* reg_sfd_uc_tunnel_protocol
	551	+ * IP protocol.
	552	+ * Access: RW
	553	+ */
	554	+MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27,
	555	+ 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
	556	+
	557	+/* reg_sfd_uc_tunnel_uip_lsb
	558	+ * When protocol is IPv4, the least significant bytes of the underlay
	559	+ * IPv4 destination IP.
	560	+ * When protocol is IPv6, pointer to the underlay IPv6 destination IP
	561	+ * which is configured by RIPS.
	562	+ * Access: RW
	563	+ */
	564	+MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0,
	565	+ 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false);
	566	+
	567	+static inline void
	568	+mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index,
	569	+ enum mlxsw_reg_sfd_rec_policy policy,
	570	+ const char *mac, u16 fid,
	571	+ enum mlxsw_reg_sfd_rec_action action, u32 uip,
	572	+ enum mlxsw_reg_sfd_uc_tunnel_protocol proto)
	573	+{
	574	+ mlxsw_reg_sfd_rec_pack(payload, rec_index,
	575	+ MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac,
	576	+ action);
	577	+ mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
	578	+ mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24);
	579	+ mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip);
	580	+ mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid);
	581	+ mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto);
	582	+}
	583	+
528	584	/* SFN - Switch FDB Notification Register
529	585	* -------------------------------------------
530	586	* The switch provides notifications on newly learned FDB entries and
..	..	@@ -565,7 +621,7 @@
565	621	{
566	622	MLXSW_REG_ZERO(sfn, payload);
567	623	mlxsw_reg_sfn_swid_set(payload, 0);
568		- mlxsw_reg_sfn_end_set(payload, 1);
	624	+ mlxsw_reg_sfn_end_set(payload, 0);
569	625	mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
570	626	}
571	627
..	..	@@ -585,6 +641,10 @@
585	641	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
586	642	/* Aged-out MAC address on a LAG port. */
587	643	MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
	644	+ /* Learned unicast tunnel record. */
	645	+ MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD,
	646	+ /* Aged-out unicast tunnel record. */
	647	+ MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE,
588	648	};
589	649
590	650	/* reg_sfn_rec_type
..	..	@@ -646,6 +706,66 @@
646	706	mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
647	707	*p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
648	708	*p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
	709	+}
	710	+
	711	+/* reg_sfn_uc_tunnel_uip_msb
	712	+ * When protocol is IPv4, the most significant byte of the underlay IPv4
	713	+ * address of the remote VTEP.
	714	+ * When protocol is IPv6, reserved.
	715	+ * Access: RO
	716	+ */
	717	+MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24,
	718	+ 8, MLXSW_REG_SFN_REC_LEN, 0x08, false);
	719	+
	720	+enum mlxsw_reg_sfn_uc_tunnel_protocol {
	721	+ MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4,
	722	+ MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6,
	723	+};
	724	+
	725	+/* reg_sfn_uc_tunnel_protocol
	726	+ * IP protocol.
	727	+ * Access: RO
	728	+ */
	729	+MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27,
	730	+ 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
	731	+
	732	+/* reg_sfn_uc_tunnel_uip_lsb
	733	+ * When protocol is IPv4, the least significant bytes of the underlay
	734	+ * IPv4 address of the remote VTEP.
	735	+ * When protocol is IPv6, ipv6_id to be queried from TNIPSD.
	736	+ * Access: RO
	737	+ */
	738	+MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0,
	739	+ 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false);
	740	+
	741	+enum mlxsw_reg_sfn_tunnel_port {
	742	+ MLXSW_REG_SFN_TUNNEL_PORT_NVE,
	743	+ MLXSW_REG_SFN_TUNNEL_PORT_VPLS,
	744	+ MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0,
	745	+ MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1,
	746	+};
	747	+
	748	+/* reg_sfn_uc_tunnel_port
	749	+ * Tunnel port.
	750	+ * Reserved on Spectrum.
	751	+ * Access: RO
	752	+ */
	753	+MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4,
	754	+ MLXSW_REG_SFN_REC_LEN, 0x10, false);
	755	+
	756	+static inline void
	757	+mlxsw_reg_sfn_uc_tunnel_unpack(char payload, int rec_index, char mac,
	758	+ u16 p_fid, u32 p_uip,
	759	+ enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto)
	760	+{
	761	+ u32 uip_msb, uip_lsb;
	762	+
	763	+ mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
	764	+ *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
	765	+ uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index);
	766	+ uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index);
	767	+ *p_uip = uip_msb << 24 \| uip_lsb;
	768	+ *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index);
649	769	}
650	770
651	771	/* SPMS - Switch Port MSTP/RSTP State Register
..	..	@@ -1069,6 +1189,8 @@
1069	1189	MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1070	1190	MLXSW_REG_SFDF_FLUSH_PER_LAG,
1071	1191	MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
	1192	+ MLXSW_REG_SFDF_FLUSH_PER_NVE,
	1193	+ MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID,
1072	1194	};
1073	1195
1074	1196	/* reg_sfdf_flush_type
..	..	@@ -1079,6 +1201,10 @@
1079	1201	* 3 - All FID dynamic entries pointing to port are flushed.
1080	1202	* 4 - All dynamic entries pointing to LAG are flushed.
1081	1203	* 5 - All FID dynamic entries pointing to LAG are flushed.
	1204	+ * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
	1205	+ * flushed.
	1206	+ * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are
	1207	+ * flushed, per FID.
1082	1208	* Access: RW
1083	1209	*/
1084	1210	MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
..	..	@@ -1315,12 +1441,19 @@
1315	1441	*/
1316	1442	MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1317	1443
1318		-static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
	1444	+/* reg_slcr_seed
	1445	+ * LAG seed value. The seed is the same for all ports.
	1446	+ * Access: RW
	1447	+ */
	1448	+MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32);
	1449	+
	1450	+static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed)
1319	1451	{
1320	1452	MLXSW_REG_ZERO(slcr, payload);
1321	1453	mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1322	1454	mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1323	1455	mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
	1456	+ mlxsw_reg_slcr_seed_set(payload, seed);
1324	1457	}
1325	1458
1326	1459	/* SLCOR - Switch LAG Collector Register
..	..	@@ -2066,6 +2199,14 @@
2066	2199	*/
2067	2200	MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2068	2201
	2202	+/* reg_pagt_multi
	2203	+ * Multi-ACL
	2204	+ * 0 - This ACL is the last ACL in the multi-ACL
	2205	+ * 1 - This ACL is part of a multi-ACL
	2206	+ * Access: RW
	2207	+ */
	2208	+MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false);
	2209	+
2069	2210	/* reg_pagt_acl_id
2070	2211	* ACL identifier
2071	2212	* Access: RW
..	..	@@ -2079,12 +2220,13 @@
2079	2220	}
2080	2221
2081	2222	static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2082		- u16 acl_id)
	2223	+ u16 acl_id, bool multi)
2083	2224	{
2084	2225	u8 size = mlxsw_reg_pagt_size_get(payload);
2085	2226
2086	2227	if (index >= size)
2087	2228	mlxsw_reg_pagt_size_set(payload, index + 1);
	2229	+ mlxsw_reg_pagt_multi_set(payload, index, multi);
2088	2230	mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2089	2231	}
2090	2232
..	..	@@ -2362,6 +2504,43 @@
2362	2504	*p_a = mlxsw_reg_pefa_a_get(payload);
2363	2505	}
2364	2506
	2507	+/* PEMRBT - Policy-Engine Multicast Router Binding Table Register
	2508	+ * --------------------------------------------------------------
	2509	+ * This register is used for binding Multicast router to an ACL group
	2510	+ * that serves the MC router.
	2511	+ * This register is not supported by SwitchX/-2 and Spectrum.
	2512	+ */
	2513	+#define MLXSW_REG_PEMRBT_ID 0x3014
	2514	+#define MLXSW_REG_PEMRBT_LEN 0x14
	2515	+
	2516	+MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN);
	2517	+
	2518	+enum mlxsw_reg_pemrbt_protocol {
	2519	+ MLXSW_REG_PEMRBT_PROTO_IPV4,
	2520	+ MLXSW_REG_PEMRBT_PROTO_IPV6,
	2521	+};
	2522	+
	2523	+/* reg_pemrbt_protocol
	2524	+ * Access: Index
	2525	+ */
	2526	+MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1);
	2527	+
	2528	+/* reg_pemrbt_group_id
	2529	+ * ACL group identifier.
	2530	+ * Range 0..cap_max_acl_groups-1
	2531	+ * Access: RW
	2532	+ */
	2533	+MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16);
	2534	+
	2535	+static inline void
	2536	+mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol,
	2537	+ u16 group_id)
	2538	+{
	2539	+ MLXSW_REG_ZERO(pemrbt, payload);
	2540	+ mlxsw_reg_pemrbt_protocol_set(payload, protocol);
	2541	+ mlxsw_reg_pemrbt_group_id_set(payload, group_id);
	2542	+}
	2543	+
2365	2544	/* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2
2366	2545	* -----------------------------------------------------
2367	2546	* This register is used for accessing rules within a TCAM region.
..	..	@@ -2573,7 +2752,7 @@
2573	2752	mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank);
2574	2753	mlxsw_reg_perpt_erpt_index_set(payload, erpt_index);
2575	2754	mlxsw_reg_perpt_key_size_set(payload, key_size);
2576		- mlxsw_reg_perpt_bf_bypass_set(payload, true);
	2755	+ mlxsw_reg_perpt_bf_bypass_set(payload, false);
2577	2756	mlxsw_reg_perpt_erp_id_set(payload, erp_id);
2578	2757	mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank);
2579	2758	mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index);
..	..	@@ -2765,8 +2944,9 @@
2765	2944	u32 priority,
2766	2945	const char *tcam_region_info,
2767	2946	const char *key, u8 erp_id,
2768		- bool large_exists, u32 lkey_id,
2769		- u32 action_pointer)
	2947	+ u16 delta_start, u8 delta_mask,
	2948	+ u8 delta_value, bool large_exists,
	2949	+ u32 lkey_id, u32 action_pointer)
2770	2950	{
2771	2951	MLXSW_REG_ZERO(ptce3, payload);
2772	2952	mlxsw_reg_ptce3_v_set(payload, valid);
..	..	@@ -2775,6 +2955,9 @@
2775	2955	mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info);
2776	2956	mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key);
2777	2957	mlxsw_reg_ptce3_erp_id_set(payload, erp_id);
	2958	+ mlxsw_reg_ptce3_delta_start_set(payload, delta_start);
	2959	+ mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask);
	2960	+ mlxsw_reg_ptce3_delta_value_set(payload, delta_value);
2778	2961	mlxsw_reg_ptce3_large_exists_set(payload, large_exists);
2779	2962	mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id);
2780	2963	mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer);
..	..	@@ -2832,7 +3015,7 @@
2832	3015	mlxsw_reg_percr_region_id_set(payload, region_id);
2833	3016	mlxsw_reg_percr_atcam_ignore_prune_set(payload, false);
2834	3017	mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false);
2835		- mlxsw_reg_percr_bf_bypass_set(payload, true);
	3018	+ mlxsw_reg_percr_bf_bypass_set(payload, false);
2836	3019	}
2837	3020
2838	3021	/* PERERP - Policy-Engine Region eRP Register
..	..	@@ -2921,6 +3104,72 @@
2921	3104	mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id);
2922	3105	}
2923	3106
	3107	+/* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register
	3108	+ * ----------------------------------------------------------------
	3109	+ * This register configures the Bloom filter entries.
	3110	+ */
	3111	+#define MLXSW_REG_PEABFE_ID 0x3022
	3112	+#define MLXSW_REG_PEABFE_BASE_LEN 0x10
	3113	+#define MLXSW_REG_PEABFE_BF_REC_LEN 0x4
	3114	+#define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256
	3115	+#define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \
	3116	+ MLXSW_REG_PEABFE_BF_REC_LEN * \
	3117	+ MLXSW_REG_PEABFE_BF_REC_MAX_COUNT)
	3118	+
	3119	+MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN);
	3120	+
	3121	+/* reg_peabfe_size
	3122	+ * Number of BF entries to be updated.
	3123	+ * Range 1..256
	3124	+ * Access: Op
	3125	+ */
	3126	+MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9);
	3127	+
	3128	+/* reg_peabfe_bf_entry_state
	3129	+ * Bloom filter state
	3130	+ * 0 - Clear
	3131	+ * 1 - Set
	3132	+ * Access: RW
	3133	+ */
	3134	+MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state,
	3135	+ MLXSW_REG_PEABFE_BASE_LEN, 31, 1,
	3136	+ MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
	3137	+
	3138	+/* reg_peabfe_bf_entry_bank
	3139	+ * Bloom filter bank ID
	3140	+ * Range 0..cap_max_erp_table_banks-1
	3141	+ * Access: Index
	3142	+ */
	3143	+MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank,
	3144	+ MLXSW_REG_PEABFE_BASE_LEN, 24, 4,
	3145	+ MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
	3146	+
	3147	+/* reg_peabfe_bf_entry_index
	3148	+ * Bloom filter entry index
	3149	+ * Range 0..2^cap_max_bf_log-1
	3150	+ * Access: Index
	3151	+ */
	3152	+MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index,
	3153	+ MLXSW_REG_PEABFE_BASE_LEN, 0, 24,
	3154	+ MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false);
	3155	+
	3156	+static inline void mlxsw_reg_peabfe_pack(char *payload)
	3157	+{
	3158	+ MLXSW_REG_ZERO(peabfe, payload);
	3159	+}
	3160	+
	3161	+static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index,
	3162	+ u8 state, u8 bank, u32 bf_index)
	3163	+{
	3164	+ u8 num_rec = mlxsw_reg_peabfe_size_get(payload);
	3165	+
	3166	+ if (rec_index >= num_rec)
	3167	+ mlxsw_reg_peabfe_size_set(payload, rec_index + 1);
	3168	+ mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state);
	3169	+ mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank);
	3170	+ mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index);
	3171	+}
	3172	+
2924	3173	/* IEDR - Infrastructure Entry Delete Register
2925	3174	* ----------------------------------------------------
2926	3175	* This register is used for deleting entries from the entry tables.
..	..	@@ -2954,7 +3203,7 @@
2954	3203	* Size of entries do be deleted. The unit is 1 entry, regardless of entry type.
2955	3204	* Access: OP
2956	3205	*/
2957		-MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 11,
	3206	+MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13,
2958	3207	MLXSW_REG_IEDR_REC_LEN, 0x00, false);
2959	3208
2960	3209	/* reg_iedr_rec_index_start
..	..	@@ -3046,6 +3295,12 @@
3046	3295	* Access: Index
3047	3296	*/
3048	3297	MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
	3298	+
	3299	+/* reg_qpcr_clear_counter
	3300	+ * Clear counters.
	3301	+ * Access: OP
	3302	+ */
	3303	+MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1);
3049	3304
3050	3305	/* reg_qpcr_color_aware
3051	3306	* Is the policer aware of colors.
..	..	@@ -3144,6 +3399,26 @@
3144	3399	*/
3145	3400	MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
3146	3401
	3402	+/* reg_qpcr_violate_count
	3403	+ * Counts the number of times violate_action happened on this PID.
	3404	+ * Access: RW
	3405	+ */
	3406	+MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64);
	3407	+
	3408	+/* Packets */
	3409	+#define MLXSW_REG_QPCR_LOWEST_CIR 1
	3410	+#define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */
	3411	+#define MLXSW_REG_QPCR_LOWEST_CBS 4
	3412	+#define MLXSW_REG_QPCR_HIGHEST_CBS 24
	3413	+
	3414	+/* Bandwidth */
	3415	+#define MLXSW_REG_QPCR_LOWEST_CIR_BITS 1024 /* bps */
	3416	+#define MLXSW_REG_QPCR_HIGHEST_CIR_BITS 2000000000000ULL /* 2Tbps */
	3417	+#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP1 4
	3418	+#define MLXSW_REG_QPCR_LOWEST_CBS_BITS_SP2 4
	3419	+#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP1 25
	3420	+#define MLXSW_REG_QPCR_HIGHEST_CBS_BITS_SP2 31
	3421	+
3147	3422	static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
3148	3423	enum mlxsw_reg_qpcr_ir_units ir_units,
3149	3424	bool bytes, u32 cir, u16 cbs)
..	..	@@ -3228,10 +3503,10 @@
3228	3503	MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
3229	3504
3230	3505	enum mlxsw_reg_qeec_hr {
3231		- MLXSW_REG_QEEC_HIERARCY_PORT,
3232		- MLXSW_REG_QEEC_HIERARCY_GROUP,
3233		- MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
3234		- MLXSW_REG_QEEC_HIERARCY_TC,
	3506	+ MLXSW_REG_QEEC_HR_PORT,
	3507	+ MLXSW_REG_QEEC_HR_GROUP,
	3508	+ MLXSW_REG_QEEC_HR_SUBGROUP,
	3509	+ MLXSW_REG_QEEC_HR_TC,
3235	3510	};
3236	3511
3237	3512	/* reg_qeec_element_hierarchy
..	..	@@ -3265,6 +3540,18 @@
3265	3540	* Access: RW
3266	3541	*/
3267	3542	MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1);
	3543	+
	3544	+/* reg_qeec_ptps
	3545	+ * PTP shaper
	3546	+ * 0: regular shaper mode
	3547	+ * 1: PTP oriented shaper
	3548	+ * Allowed only for hierarchy 0
	3549	+ * Not supported for CPU port
	3550	+ * Note that ptps mode may affect the shaper rates of all hierarchies
	3551	+ * Supported only on Spectrum-1
	3552	+ * Access: RW
	3553	+ */
	3554	+MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1);
3268	3555
3269	3556	enum {
3270	3557	MLXSW_REG_QEEC_BYTES_MODE,
..	..	@@ -3302,8 +3589,8 @@
3302	3589	*/
3303	3590	MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
3304	3591
3305		-/* A large max rate will disable the max shaper. */
3306		-#define MLXSW_REG_QEEC_MAS_DIS 200000000 /* Kbps */
	3592	+/* The largest max shaper value possible to disable the shaper. */
	3593	+#define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */
3307	3594
3308	3595	/* reg_qeec_max_shaper_rate
3309	3596	* Max shaper information rate.
..	..	@@ -3311,7 +3598,7 @@
3311	3598	* When in bytes mode, value is specified in units of 1000bps.
3312	3599	* Access: RW
3313	3600	*/
3314		-MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
	3601	+MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31);
3315	3602
3316	3603	/* reg_qeec_de
3317	3604	* DWRR configuration enable. Enables configuration of the dwrr and
..	..	@@ -3341,6 +3628,21 @@
3341	3628	*/
3342	3629	MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
3343	3630
	3631	+/* reg_qeec_max_shaper_bs
	3632	+ * Max shaper burst size
	3633	+ * Burst size is 2^max_shaper_bs * 512 bits
	3634	+ * For Spectrum-1: Range is: 5..25
	3635	+ * For Spectrum-2: Range is: 11..25
	3636	+ * Reserved when ptps = 1
	3637	+ * Access: RW
	3638	+ */
	3639	+MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6);
	3640	+
	3641	+#define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25
	3642	+#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5
	3643	+#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11
	3644	+#define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 11
	3645	+
3344	3646	static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
3345	3647	enum mlxsw_reg_qeec_hr hr, u8 index,
3346	3648	u8 next_index)
..	..	@@ -3350,6 +3652,15 @@
3350	3652	mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
3351	3653	mlxsw_reg_qeec_element_index_set(payload, index);
3352	3654	mlxsw_reg_qeec_next_element_index_set(payload, next_index);
	3655	+}
	3656	+
	3657	+static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port,
	3658	+ bool ptps)
	3659	+{
	3660	+ MLXSW_REG_ZERO(qeec, payload);
	3661	+ mlxsw_reg_qeec_local_port_set(payload, local_port);
	3662	+ mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT);
	3663	+ mlxsw_reg_qeec_ptps_set(payload, ptps);
3353	3664	}
3354	3665
3355	3666	/* QRWE - QoS ReWrite Enable
..	..	@@ -3478,6 +3789,38 @@
3478	3789	mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp);
3479	3790	}
3480	3791
	3792	+/* QPDP - QoS Port DSCP to Priority Mapping Register
	3793	+ * -------------------------------------------------
	3794	+ * This register controls the port default Switch Priority and Color. The
	3795	+ * default Switch Priority and Color are used for frames where the trust state
	3796	+ * uses default values. All member ports of a LAG should be configured with the
	3797	+ * same default values.
	3798	+ */
	3799	+#define MLXSW_REG_QPDP_ID 0x4007
	3800	+#define MLXSW_REG_QPDP_LEN 0x8
	3801	+
	3802	+MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN);
	3803	+
	3804	+/* reg_qpdp_local_port
	3805	+ * Local Port. Supported for data packets from CPU port.
	3806	+ * Access: Index
	3807	+ */
	3808	+MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8);
	3809	+
	3810	+/* reg_qpdp_switch_prio
	3811	+ * Default port Switch Priority (default 0)
	3812	+ * Access: RW
	3813	+ */
	3814	+MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4);
	3815	+
	3816	+static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port,
	3817	+ u8 switch_prio)
	3818	+{
	3819	+ MLXSW_REG_ZERO(qpdp, payload);
	3820	+ mlxsw_reg_qpdp_local_port_set(payload, local_port);
	3821	+ mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio);
	3822	+}
	3823	+
3481	3824	/* QPDPM - QoS Port DSCP to Priority Mapping Register
3482	3825	* --------------------------------------------------
3483	3826	* This register controls the mapping from DSCP field to
..	..	@@ -3565,6 +3908,112 @@
3565	3908	mlxsw_reg_qtctm_mc_set(payload, mc);
3566	3909	}
3567	3910
	3911	+/* QPSC - QoS PTP Shaper Configuration Register
	3912	+ * --------------------------------------------
	3913	+ * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1.
	3914	+ * Supported only on Spectrum-1.
	3915	+ */
	3916	+#define MLXSW_REG_QPSC_ID 0x401B
	3917	+#define MLXSW_REG_QPSC_LEN 0x28
	3918	+
	3919	+MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN);
	3920	+
	3921	+enum mlxsw_reg_qpsc_port_speed {
	3922	+ MLXSW_REG_QPSC_PORT_SPEED_100M,
	3923	+ MLXSW_REG_QPSC_PORT_SPEED_1G,
	3924	+ MLXSW_REG_QPSC_PORT_SPEED_10G,
	3925	+ MLXSW_REG_QPSC_PORT_SPEED_25G,
	3926	+};
	3927	+
	3928	+/* reg_qpsc_port_speed
	3929	+ * Port speed.
	3930	+ * Access: Index
	3931	+ */
	3932	+MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4);
	3933	+
	3934	+/* reg_qpsc_shaper_time_exp
	3935	+ * The base-time-interval for updating the shapers tokens (for all hierarchies).
	3936	+ * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
	3937	+ * shaper_rate = 64bit * shaper_inc / shaper_update_rate
	3938	+ * Access: RW
	3939	+ */
	3940	+MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4);
	3941	+
	3942	+/* reg_qpsc_shaper_time_mantissa
	3943	+ * The base-time-interval for updating the shapers tokens (for all hierarchies).
	3944	+ * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec
	3945	+ * shaper_rate = 64bit * shaper_inc / shaper_update_rate
	3946	+ * Access: RW
	3947	+ */
	3948	+MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5);
	3949	+
	3950	+/* reg_qpsc_shaper_inc
	3951	+ * Number of tokens added to shaper on each update.
	3952	+ * Units of 8B.
	3953	+ * Access: RW
	3954	+ */
	3955	+MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5);
	3956	+
	3957	+/* reg_qpsc_shaper_bs
	3958	+ * Max shaper Burst size.
	3959	+ * Burst size is 2 ^ max_shaper_bs * 512 [bits]
	3960	+ * Range is: 5..25 (from 2KB..2GB)
	3961	+ * Access: RW
	3962	+ */
	3963	+MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6);
	3964	+
	3965	+/* reg_qpsc_ptsc_we
	3966	+ * Write enable to port_to_shaper_credits.
	3967	+ * Access: WO
	3968	+ */
	3969	+MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1);
	3970	+
	3971	+/* reg_qpsc_port_to_shaper_credits
	3972	+ * For split ports: range 1..57
	3973	+ * For non-split ports: range 1..112
	3974	+ * Written only when ptsc_we is set.
	3975	+ * Access: RW
	3976	+ */
	3977	+MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8);
	3978	+
	3979	+/* reg_qpsc_ing_timestamp_inc
	3980	+ * Ingress timestamp increment.
	3981	+ * 2's complement.
	3982	+ * The timestamp of MTPPTR at ingress will be incremented by this value. Global
	3983	+ * value for all ports.
	3984	+ * Same units as used by MTPPTR.
	3985	+ * Access: RW
	3986	+ */
	3987	+MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32);
	3988	+
	3989	+/* reg_qpsc_egr_timestamp_inc
	3990	+ * Egress timestamp increment.
	3991	+ * 2's complement.
	3992	+ * The timestamp of MTPPTR at egress will be incremented by this value. Global
	3993	+ * value for all ports.
	3994	+ * Same units as used by MTPPTR.
	3995	+ * Access: RW
	3996	+ */
	3997	+MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32);
	3998	+
	3999	+static inline void
	4000	+mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed,
	4001	+ u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc,
	4002	+ u8 shaper_bs, u8 port_to_shaper_credits,
	4003	+ int ing_timestamp_inc, int egr_timestamp_inc)
	4004	+{
	4005	+ MLXSW_REG_ZERO(qpsc, payload);
	4006	+ mlxsw_reg_qpsc_port_speed_set(payload, port_speed);
	4007	+ mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp);
	4008	+ mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa);
	4009	+ mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc);
	4010	+ mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs);
	4011	+ mlxsw_reg_qpsc_ptsc_we_set(payload, true);
	4012	+ mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits);
	4013	+ mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc);
	4014	+ mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc);
	4015	+}
	4016	+
3568	4017	/* PMLP - Ports Module to Local Port Register
3569	4018	* ------------------------------------------
3570	4019	* Configures the assignment of modules to local ports.
..	..	@@ -3592,6 +4041,7 @@
3592	4041	* 1 - Lane 0 is used.
3593	4042	* 2 - Lanes 0 and 1 are used.
3594	4043	* 4 - Lanes 0, 1, 2 and 3 are used.
	4044	+ * 8 - Lanes 0-7 are used.
3595	4045	* Access: RW
3596	4046	*/
3597	4047	MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
..	..	@@ -3606,14 +4056,14 @@
3606	4056	* Tx Lane. When rxtx field is cleared, this field is used for Rx as well.
3607	4057	* Access: RW
3608	4058	*/
3609		-MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
	4059	+MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false);
3610	4060
3611	4061	/* reg_pmlp_rx_lane
3612	4062	* Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is
3613	4063	* equal to Tx lane.
3614	4064	* Access: RW
3615	4065	*/
3616		-MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
	4066	+MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false);
3617	4067
3618	4068	static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
3619	4069	{
..	..	@@ -3722,15 +4172,32 @@
3722	4172	*/
3723	4173	MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
3724	4174
	4175	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0)
	4176	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1)
	4177	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3)
	4178	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4)
	4179	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5)
	4180	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6)
	4181	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7)
	4182	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8)
	4183	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9)
	4184	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
	4185	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
	4186	+#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15)
	4187	+
	4188	+/* reg_ptys_ext_eth_proto_cap
	4189	+ * Extended Ethernet port supported speeds and protocols.
	4190	+ * Access: RO
	4191	+ */
	4192	+MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32);
	4193	+
3725	4194	#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
3726	4195	#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
3727	4196	#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
3728	4197	#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
3729	4198	#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
3730		-#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
3731	4199	#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
3732	4200	#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
3733		-#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
3734	4201	#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
3735	4202	#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
3736	4203	#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
..	..	@@ -3742,9 +4209,6 @@
3742	4209	#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
3743	4210	#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
3744	4211	#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
3745		-#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
3746		-#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
3747		-#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
3748	4212	#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
3749	4213	#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
3750	4214	#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
..	..	@@ -3776,6 +4240,12 @@
3776	4240	*/
3777	4241	MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
3778	4242
	4243	+/* reg_ptys_ext_eth_proto_admin
	4244	+ * Extended speed and protocol to set port to.
	4245	+ * Access: RW
	4246	+ */
	4247	+MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32);
	4248	+
3779	4249	/* reg_ptys_eth_proto_admin
3780	4250	* Speed and protocol to set port to.
3781	4251	* Access: RW
..	..	@@ -3793,6 +4263,12 @@
3793	4263	* Access: RW
3794	4264	*/
3795	4265	MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
	4266	+
	4267	+/* reg_ptys_ext_eth_proto_oper
	4268	+ * The extended current speed and protocol configured for the port.
	4269	+ * Access: RO
	4270	+ */
	4271	+MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32);
3796	4272
3797	4273	/* reg_ptys_eth_proto_oper
3798	4274	* The current speed and protocol configured for the port.
..	..	@@ -3812,12 +4288,23 @@
3812	4288	*/
3813	4289	MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
3814	4290
3815		-/* reg_ptys_eth_proto_lp_advertise
3816		- * The protocols that were advertised by the link partner during
3817		- * autonegotiation.
	4291	+enum mlxsw_reg_ptys_connector_type {
	4292	+ MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR,
	4293	+ MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE,
	4294	+ MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP,
	4295	+ MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI,
	4296	+ MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC,
	4297	+ MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII,
	4298	+ MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE,
	4299	+ MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA,
	4300	+ MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER,
	4301	+};
	4302	+
	4303	+/* reg_ptys_connector_type
	4304	+ * Connector type indication.
3818	4305	* Access: RO
3819	4306	*/
3820		-MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32);
	4307	+MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4);
3821	4308
3822	4309	static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
3823	4310	u32 proto_admin, bool autoneg)
..	..	@@ -3829,17 +4316,46 @@
3829	4316	mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
3830	4317	}
3831	4318
	4319	+static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port,
	4320	+ u32 proto_admin, bool autoneg)
	4321	+{
	4322	+ MLXSW_REG_ZERO(ptys, payload);
	4323	+ mlxsw_reg_ptys_local_port_set(payload, local_port);
	4324	+ mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
	4325	+ mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin);
	4326	+ mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
	4327	+}
	4328	+
3832	4329	static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
3833	4330	u32 *p_eth_proto_cap,
3834		- u32 *p_eth_proto_adm,
	4331	+ u32 *p_eth_proto_admin,
3835	4332	u32 *p_eth_proto_oper)
3836	4333	{
3837	4334	if (p_eth_proto_cap)
3838		- *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
3839		- if (p_eth_proto_adm)
3840		- *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
	4335	+ *p_eth_proto_cap =
	4336	+ mlxsw_reg_ptys_eth_proto_cap_get(payload);
	4337	+ if (p_eth_proto_admin)
	4338	+ *p_eth_proto_admin =
	4339	+ mlxsw_reg_ptys_eth_proto_admin_get(payload);
3841	4340	if (p_eth_proto_oper)
3842		- *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
	4341	+ *p_eth_proto_oper =
	4342	+ mlxsw_reg_ptys_eth_proto_oper_get(payload);
	4343	+}
	4344	+
	4345	+static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload,
	4346	+ u32 *p_eth_proto_cap,
	4347	+ u32 *p_eth_proto_admin,
	4348	+ u32 *p_eth_proto_oper)
	4349	+{
	4350	+ if (p_eth_proto_cap)
	4351	+ *p_eth_proto_cap =
	4352	+ mlxsw_reg_ptys_ext_eth_proto_cap_get(payload);
	4353	+ if (p_eth_proto_admin)
	4354	+ *p_eth_proto_admin =
	4355	+ mlxsw_reg_ptys_ext_eth_proto_admin_get(payload);
	4356	+ if (p_eth_proto_oper)
	4357	+ *p_eth_proto_oper =
	4358	+ mlxsw_reg_ptys_ext_eth_proto_oper_get(payload);
3843	4359	}
3844	4360
3845	4361	static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
..	..	@@ -4162,8 +4678,11 @@
4162	4678
4163	4679	enum mlxsw_reg_ppcnt_grp {
4164	4680	MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
	4681	+ MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1,
4165	4682	MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2,
	4683	+ MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3,
4166	4684	MLXSW_REG_PPCNT_EXT_CNT = 0x5,
	4685	+ MLXSW_REG_PPCNT_DISCARD_CNT = 0x6,
4167	4686	MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
4168	4687	MLXSW_REG_PPCNT_TC_CNT = 0x11,
4169	4688	MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
..	..	@@ -4178,6 +4697,7 @@
4178	4697	* 0x2: RFC 2819 Counters
4179	4698	* 0x3: RFC 3635 Counters
4180	4699	* 0x5: Ethernet Extended Counters
	4700	+ * 0x6: Ethernet Discard Counters
4181	4701	* 0x8: Link Level Retransmission Counters
4182	4702	* 0x10: Per Priority Counters
4183	4703	* 0x11: Per Traffic Class Counters
..	..	@@ -4321,7 +4841,45 @@
4321	4841	MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
4322	4842	MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
4323	4843
	4844	+/* Ethernet RFC 2863 Counter Group */
	4845	+
	4846	+/* reg_ppcnt_if_in_discards
	4847	+ * Access: RO
	4848	+ */
	4849	+MLXSW_ITEM64(reg, ppcnt, if_in_discards,
	4850	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
	4851	+
	4852	+/* reg_ppcnt_if_out_discards
	4853	+ * Access: RO
	4854	+ */
	4855	+MLXSW_ITEM64(reg, ppcnt, if_out_discards,
	4856	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
	4857	+
	4858	+/* reg_ppcnt_if_out_errors
	4859	+ * Access: RO
	4860	+ */
	4861	+MLXSW_ITEM64(reg, ppcnt, if_out_errors,
	4862	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
	4863	+
4324	4864	/* Ethernet RFC 2819 Counter Group */
	4865	+
	4866	+/* reg_ppcnt_ether_stats_undersize_pkts
	4867	+ * Access: RO
	4868	+ */
	4869	+MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts,
	4870	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
	4871	+
	4872	+/* reg_ppcnt_ether_stats_oversize_pkts
	4873	+ * Access: RO
	4874	+ */
	4875	+MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts,
	4876	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
	4877	+
	4878	+/* reg_ppcnt_ether_stats_fragments
	4879	+ * Access: RO
	4880	+ */
	4881	+MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments,
	4882	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
4325	4883
4326	4884	/* reg_ppcnt_ether_stats_pkts64octets
4327	4885	* Access: RO
..	..	@@ -4383,6 +4941,32 @@
4383	4941	MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets,
4384	4942	MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64);
4385	4943
	4944	+/* Ethernet RFC 3635 Counter Group */
	4945	+
	4946	+/* reg_ppcnt_dot3stats_fcs_errors
	4947	+ * Access: RO
	4948	+ */
	4949	+MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors,
	4950	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
	4951	+
	4952	+/* reg_ppcnt_dot3stats_symbol_errors
	4953	+ * Access: RO
	4954	+ */
	4955	+MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors,
	4956	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
	4957	+
	4958	+/* reg_ppcnt_dot3control_in_unknown_opcodes
	4959	+ * Access: RO
	4960	+ */
	4961	+MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes,
	4962	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
	4963	+
	4964	+/* reg_ppcnt_dot3in_pause_frames
	4965	+ * Access: RO
	4966	+ */
	4967	+MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames,
	4968	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
	4969	+
4386	4970	/* Ethernet Extended Counter Group Counters */
4387	4971
4388	4972	/* reg_ppcnt_ecn_marked
..	..	@@ -4390,6 +4974,80 @@
4390	4974	*/
4391	4975	MLXSW_ITEM64(reg, ppcnt, ecn_marked,
4392	4976	MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
	4977	+
	4978	+/* Ethernet Discard Counter Group Counters */
	4979	+
	4980	+/* reg_ppcnt_ingress_general
	4981	+ * Access: RO
	4982	+ */
	4983	+MLXSW_ITEM64(reg, ppcnt, ingress_general,
	4984	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
	4985	+
	4986	+/* reg_ppcnt_ingress_policy_engine
	4987	+ * Access: RO
	4988	+ */
	4989	+MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine,
	4990	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
	4991	+
	4992	+/* reg_ppcnt_ingress_vlan_membership
	4993	+ * Access: RO
	4994	+ */
	4995	+MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership,
	4996	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
	4997	+
	4998	+/* reg_ppcnt_ingress_tag_frame_type
	4999	+ * Access: RO
	5000	+ */
	5001	+MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type,
	5002	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
	5003	+
	5004	+/* reg_ppcnt_egress_vlan_membership
	5005	+ * Access: RO
	5006	+ */
	5007	+MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership,
	5008	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
	5009	+
	5010	+/* reg_ppcnt_loopback_filter
	5011	+ * Access: RO
	5012	+ */
	5013	+MLXSW_ITEM64(reg, ppcnt, loopback_filter,
	5014	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
	5015	+
	5016	+/* reg_ppcnt_egress_general
	5017	+ * Access: RO
	5018	+ */
	5019	+MLXSW_ITEM64(reg, ppcnt, egress_general,
	5020	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
	5021	+
	5022	+/* reg_ppcnt_egress_hoq
	5023	+ * Access: RO
	5024	+ */
	5025	+MLXSW_ITEM64(reg, ppcnt, egress_hoq,
	5026	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
	5027	+
	5028	+/* reg_ppcnt_egress_policy_engine
	5029	+ * Access: RO
	5030	+ */
	5031	+MLXSW_ITEM64(reg, ppcnt, egress_policy_engine,
	5032	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
	5033	+
	5034	+/* reg_ppcnt_ingress_tx_link_down
	5035	+ * Access: RO
	5036	+ */
	5037	+MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down,
	5038	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
	5039	+
	5040	+/* reg_ppcnt_egress_stp_filter
	5041	+ * Access: RO
	5042	+ */
	5043	+MLXSW_ITEM64(reg, ppcnt, egress_stp_filter,
	5044	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
	5045	+
	5046	+/* reg_ppcnt_egress_sll
	5047	+ * Access: RO
	5048	+ */
	5049	+MLXSW_ITEM64(reg, ppcnt, egress_sll,
	5050	+ MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
4393	5051
4394	5052	/* Ethernet Per Priority Group Counters */
4395	5053
..	..	@@ -4748,6 +5406,257 @@
4748	5406	mlxsw_reg_pspa_sub_port_set(payload, 0);
4749	5407	}
4750	5408
	5409	+/* PMAOS - Ports Module Administrative and Operational Status
	5410	+ * ----------------------------------------------------------
	5411	+ * This register configures and retrieves the per module status.
	5412	+ */
	5413	+#define MLXSW_REG_PMAOS_ID 0x5012
	5414	+#define MLXSW_REG_PMAOS_LEN 0x10
	5415	+
	5416	+MLXSW_REG_DEFINE(pmaos, MLXSW_REG_PMAOS_ID, MLXSW_REG_PMAOS_LEN);
	5417	+
	5418	+/* reg_slot_index
	5419	+ * Slot index.
	5420	+ * Access: Index
	5421	+ */
	5422	+MLXSW_ITEM32(reg, pmaos, slot_index, 0x00, 24, 4);
	5423	+
	5424	+/* reg_pmaos_module
	5425	+ * Module number.
	5426	+ * Access: Index
	5427	+ */
	5428	+MLXSW_ITEM32(reg, pmaos, module, 0x00, 16, 8);
	5429	+
	5430	+/* reg_pmaos_ase
	5431	+ * Admin state update enable.
	5432	+ * If this bit is set, admin state will be updated based on admin_state field.
	5433	+ * Only relevant on Set() operations.
	5434	+ * Access: WO
	5435	+ */
	5436	+MLXSW_ITEM32(reg, pmaos, ase, 0x04, 31, 1);
	5437	+
	5438	+/* reg_pmaos_ee
	5439	+ * Event update enable.
	5440	+ * If this bit is set, event generation will be updated based on the e field.
	5441	+ * Only relevant on Set operations.
	5442	+ * Access: WO
	5443	+ */
	5444	+MLXSW_ITEM32(reg, pmaos, ee, 0x04, 30, 1);
	5445	+
	5446	+enum mlxsw_reg_pmaos_e {
	5447	+ MLXSW_REG_PMAOS_E_DO_NOT_GENERATE_EVENT,
	5448	+ MLXSW_REG_PMAOS_E_GENERATE_EVENT,
	5449	+ MLXSW_REG_PMAOS_E_GENERATE_SINGLE_EVENT,
	5450	+};
	5451	+
	5452	+/* reg_pmaos_e
	5453	+ * Event Generation on operational state change.
	5454	+ * Access: RW
	5455	+ */
	5456	+MLXSW_ITEM32(reg, pmaos, e, 0x04, 0, 2);
	5457	+
	5458	+static inline void mlxsw_reg_pmaos_pack(char *payload, u8 module,
	5459	+ enum mlxsw_reg_pmaos_e e)
	5460	+{
	5461	+ MLXSW_REG_ZERO(pmaos, payload);
	5462	+ mlxsw_reg_pmaos_module_set(payload, module);
	5463	+ mlxsw_reg_pmaos_e_set(payload, e);
	5464	+ mlxsw_reg_pmaos_ee_set(payload, true);
	5465	+}
	5466	+
	5467	+/* PPLR - Port Physical Loopback Register
	5468	+ * --------------------------------------
	5469	+ * This register allows configuration of the port's loopback mode.
	5470	+ */
	5471	+#define MLXSW_REG_PPLR_ID 0x5018
	5472	+#define MLXSW_REG_PPLR_LEN 0x8
	5473	+
	5474	+MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN);
	5475	+
	5476	+/* reg_pplr_local_port
	5477	+ * Local port number.
	5478	+ * Access: Index
	5479	+ */
	5480	+MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8);
	5481	+
	5482	+/* Phy local loopback. When set the port's egress traffic is looped back
	5483	+ * to the receiver and the port transmitter is disabled.
	5484	+ */
	5485	+#define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1)
	5486	+
	5487	+/* reg_pplr_lb_en
	5488	+ * Loopback enable.
	5489	+ * Access: RW
	5490	+ */
	5491	+MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8);
	5492	+
	5493	+static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
	5494	+ bool phy_local)
	5495	+{
	5496	+ MLXSW_REG_ZERO(pplr, payload);
	5497	+ mlxsw_reg_pplr_local_port_set(payload, local_port);
	5498	+ mlxsw_reg_pplr_lb_en_set(payload,
	5499	+ phy_local ?
	5500	+ MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
	5501	+}
	5502	+
	5503	+/* PMPE - Port Module Plug/Unplug Event Register
	5504	+ * ---------------------------------------------
	5505	+ * This register reports any operational status change of a module.
	5506	+ * A change in the module’s state will generate an event only if the change
	5507	+ * happens after arming the event mechanism. Any changes to the module state
	5508	+ * while the event mechanism is not armed will not be reported. Software can
	5509	+ * query the PMPE register for module status.
	5510	+ */
	5511	+#define MLXSW_REG_PMPE_ID 0x5024
	5512	+#define MLXSW_REG_PMPE_LEN 0x10
	5513	+
	5514	+MLXSW_REG_DEFINE(pmpe, MLXSW_REG_PMPE_ID, MLXSW_REG_PMPE_LEN);
	5515	+
	5516	+/* reg_pmpe_slot_index
	5517	+ * Slot index.
	5518	+ * Access: Index
	5519	+ */
	5520	+MLXSW_ITEM32(reg, pmpe, slot_index, 0x00, 24, 4);
	5521	+
	5522	+/* reg_pmpe_module
	5523	+ * Module number.
	5524	+ * Access: Index
	5525	+ */
	5526	+MLXSW_ITEM32(reg, pmpe, module, 0x00, 16, 8);
	5527	+
	5528	+enum mlxsw_reg_pmpe_module_status {
	5529	+ MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ENABLED = 1,
	5530	+ MLXSW_REG_PMPE_MODULE_STATUS_UNPLUGGED,
	5531	+ MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_ERROR,
	5532	+ MLXSW_REG_PMPE_MODULE_STATUS_PLUGGED_DISABLED,
	5533	+};
	5534	+
	5535	+/* reg_pmpe_module_status
	5536	+ * Module status.
	5537	+ * Access: RO
	5538	+ */
	5539	+MLXSW_ITEM32(reg, pmpe, module_status, 0x00, 0, 4);
	5540	+
	5541	+/* reg_pmpe_error_type
	5542	+ * Module error details.
	5543	+ * Access: RO
	5544	+ */
	5545	+MLXSW_ITEM32(reg, pmpe, error_type, 0x04, 8, 4);
	5546	+
	5547	+/* PDDR - Port Diagnostics Database Register
	5548	+ * -----------------------------------------
	5549	+ * The PDDR enables to read the Phy debug database
	5550	+ */
	5551	+#define MLXSW_REG_PDDR_ID 0x5031
	5552	+#define MLXSW_REG_PDDR_LEN 0x100
	5553	+
	5554	+MLXSW_REG_DEFINE(pddr, MLXSW_REG_PDDR_ID, MLXSW_REG_PDDR_LEN);
	5555	+
	5556	+/* reg_pddr_local_port
	5557	+ * Local port number.
	5558	+ * Access: Index
	5559	+ */
	5560	+MLXSW_ITEM32(reg, pddr, local_port, 0x00, 16, 8);
	5561	+
	5562	+enum mlxsw_reg_pddr_page_select {
	5563	+ MLXSW_REG_PDDR_PAGE_SELECT_TROUBLESHOOTING_INFO = 1,
	5564	+};
	5565	+
	5566	+/* reg_pddr_page_select
	5567	+ * Page select index.
	5568	+ * Access: Index
	5569	+ */
	5570	+MLXSW_ITEM32(reg, pddr, page_select, 0x04, 0, 8);
	5571	+
	5572	+enum mlxsw_reg_pddr_trblsh_group_opcode {
	5573	+ /* Monitor opcodes */
	5574	+ MLXSW_REG_PDDR_TRBLSH_GROUP_OPCODE_MONITOR,
	5575	+};
	5576	+
	5577	+/* reg_pddr_group_opcode
	5578	+ * Group selector.
	5579	+ * Access: Index
	5580	+ */
	5581	+MLXSW_ITEM32(reg, pddr, trblsh_group_opcode, 0x08, 0, 16);
	5582	+
	5583	+/* reg_pddr_status_opcode
	5584	+ * Group selector.
	5585	+ * Access: RO
	5586	+ */
	5587	+MLXSW_ITEM32(reg, pddr, trblsh_status_opcode, 0x0C, 0, 16);
	5588	+
	5589	+static inline void mlxsw_reg_pddr_pack(char *payload, u8 local_port,
	5590	+ u8 page_select)
	5591	+{
	5592	+ MLXSW_REG_ZERO(pddr, payload);
	5593	+ mlxsw_reg_pddr_local_port_set(payload, local_port);
	5594	+ mlxsw_reg_pddr_page_select_set(payload, page_select);
	5595	+}
	5596	+
	5597	+/* PMTM - Port Module Type Mapping Register
	5598	+ * ----------------------------------------
	5599	+ * The PMTM allows query or configuration of module types.
	5600	+ */
	5601	+#define MLXSW_REG_PMTM_ID 0x5067
	5602	+#define MLXSW_REG_PMTM_LEN 0x10
	5603	+
	5604	+MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);
	5605	+
	5606	+/* reg_pmtm_module
	5607	+ * Module number.
	5608	+ * Access: Index
	5609	+ */
	5610	+MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);
	5611	+
	5612	+enum mlxsw_reg_pmtm_module_type {
	5613	+ /* Backplane with 4 lanes */
	5614	+ MLXSW_REG_PMTM_MODULE_TYPE_BP_4X,
	5615	+ /* QSFP */
	5616	+ MLXSW_REG_PMTM_MODULE_TYPE_QSFP,
	5617	+ /* SFP */
	5618	+ MLXSW_REG_PMTM_MODULE_TYPE_SFP,
	5619	+ /* Backplane with single lane */
	5620	+ MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4,
	5621	+ /* Backplane with two lane */
	5622	+ MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8,
	5623	+ /* Chip2Chip4x */
	5624	+ MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10,
	5625	+ /* Chip2Chip2x */
	5626	+ MLXSW_REG_PMTM_MODULE_TYPE_C2C2X,
	5627	+ /* Chip2Chip1x */
	5628	+ MLXSW_REG_PMTM_MODULE_TYPE_C2C1X,
	5629	+ /* QSFP-DD */
	5630	+ MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14,
	5631	+ /* OSFP */
	5632	+ MLXSW_REG_PMTM_MODULE_TYPE_OSFP,
	5633	+ /* SFP-DD */
	5634	+ MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD,
	5635	+ /* DSFP */
	5636	+ MLXSW_REG_PMTM_MODULE_TYPE_DSFP,
	5637	+ /* Chip2Chip8x */
	5638	+ MLXSW_REG_PMTM_MODULE_TYPE_C2C8X,
	5639	+};
	5640	+
	5641	+/* reg_pmtm_module_type
	5642	+ * Module type.
	5643	+ * Access: RW
	5644	+ */
	5645	+MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4);
	5646	+
	5647	+static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module)
	5648	+{
	5649	+ MLXSW_REG_ZERO(pmtm, payload);
	5650	+ mlxsw_reg_pmtm_module_set(payload, module);
	5651	+}
	5652	+
	5653	+static inline void
	5654	+mlxsw_reg_pmtm_unpack(char *payload,
	5655	+ enum mlxsw_reg_pmtm_module_type *module_type)
	5656	+{
	5657	+ *module_type = mlxsw_reg_pmtm_module_type_get(payload);
	5658	+}
	5659	+
4751	5660	/* HTGT - Host Trap Group Table
4752	5661	* ----------------------------
4753	5662	* Configures the properties for forwarding to CPU.
..	..	@@ -4773,26 +5682,42 @@
4773	5682
4774	5683	enum mlxsw_reg_htgt_trap_group {
4775	5684	MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
4776		- MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
4777		- MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
	5685	+ MLXSW_REG_HTGT_TRAP_GROUP_MFDE,
	5686	+ MLXSW_REG_HTGT_TRAP_GROUP_MTWE,
	5687	+ MLXSW_REG_HTGT_TRAP_GROUP_PMPE,
4778	5688	MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
4779	5689	MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
4780	5690	MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
4781		- MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
	5691	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING,
4782	5692	MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
4783	5693	MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
4784	5694	MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
4785	5695	MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
4786		- MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
4787		- MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
	5696	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY,
4788	5697	MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
4789		- MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
	5698	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_EXTERNAL_ROUTE,
4790	5699	MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
4791	5700	MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
4792		- MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
4793	5701	MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
4794		- MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
4795		- MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
	5702	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6,
	5703	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR,
	5704	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0,
	5705	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1,
	5706	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP,
	5707	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE,
	5708	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING,
	5709	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS,
	5710	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD,
	5711	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY,
	5712	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS,
	5713	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS,
	5714	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS,
	5715	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS,
	5716	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS,
	5717	+ MLXSW_REG_HTGT_TRAP_GROUP_SP_BUFFER_DISCARDS,
	5718	+
	5719	+ __MLXSW_REG_HTGT_TRAP_GROUP_MAX,
	5720	+ MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1
4796	5721	};
4797	5722
4798	5723	/* reg_htgt_trap_group
..	..	@@ -4930,6 +5855,8 @@
4930	5855	MLXSW_REG_HPKT_ACTION_DISCARD,
4931	5856	MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
4932	5857	MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
	5858	+ MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU,
	5859	+ MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15,
4933	5860	};
4934	5861
4935	5862	/* reg_hpkt_action
..	..	@@ -4940,6 +5867,8 @@
4940	5867	* 3 - Discard.
4941	5868	* 4 - Soft discard (allow other traps to act on the packet).
4942	5869	* 5 - Trap and soft discard (allow other traps to overwrite this trap).
	5870	+ * 6 - Trap to CPU (CPU receives sole copy) and count it as error.
	5871	+ * 15 - Restore the firmware's default action.
4943	5872	* Access: RW
4944	5873	*
4945	5874	* Note: Must be set to 0 (forward) for event trap IDs, as they are already
..	..	@@ -4960,7 +5889,7 @@
4960	5889	* Note: A trap ID can only be associated with a single trap group. The device
4961	5890	* will associate the trap ID with the last trap group configured.
4962	5891	*/
4963		-MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
	5892	+MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 10);
4964	5893
4965	5894	enum {
4966	5895	MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
..	..	@@ -5283,6 +6212,8 @@
5283	6212	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
5284	6213	/* IPinIP IPv6 underlay Unicast */
5285	6214	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
	6215	+ /* IPinIP generic - used for Spectrum-2 underlay RIF */
	6216	+ MLXSW_REG_RITR_LOOPBACK_GENERIC,
5286	6217	};
5287	6218
5288	6219	/* reg_ritr_loopback_protocol
..	..	@@ -5322,6 +6253,13 @@
5322	6253	* Access: RW
5323	6254	*/
5324	6255	MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
	6256	+
	6257	+/* reg_ritr_loopback_ipip_underlay_rif
	6258	+ * Underlay ingress router interface.
	6259	+ * Reserved for Spectrum.
	6260	+ * Access: RW
	6261	+ */
	6262	+MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16);
5325	6263
5326	6264	/* reg_ritr_loopback_ipip_usip*
5327	6265	* Encapsulation Underlay source IP.
..	..	@@ -5438,11 +6376,12 @@
5438	6376	mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
5439	6377	enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5440	6378	enum mlxsw_reg_ritr_loopback_ipip_options options,
5441		- u16 uvr_id, u32 gre_key)
	6379	+ u16 uvr_id, u16 underlay_rif, u32 gre_key)
5442	6380	{
5443	6381	mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
5444	6382	mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
5445	6383	mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
	6384	+ mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif);
5446	6385	mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
5447	6386	}
5448	6387
..	..	@@ -5450,12 +6389,12 @@
5450	6389	mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
5451	6390	enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
5452	6391	enum mlxsw_reg_ritr_loopback_ipip_options options,
5453		- u16 uvr_id, u32 usip, u32 gre_key)
	6392	+ u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key)
5454	6393	{
5455	6394	mlxsw_reg_ritr_loopback_protocol_set(payload,
5456	6395	MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
5457	6396	mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
5458		- uvr_id, gre_key);
	6397	+ uvr_id, underlay_rif, gre_key);
5459	6398	mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
5460	6399	}
5461	6400
..	..	@@ -6817,6 +7756,13 @@
6817	7756	*/
6818	7757	MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
6819	7758
	7759	+/* reg_rtdp_egress_router_interface
	7760	+ * Underlay egress router interface.
	7761	+ * Valid range is from 0 to cap_max_router_interfaces - 1
	7762	+ * Access: RW
	7763	+ */
	7764	+MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16);
	7765	+
6820	7766	/* IPinIP */
6821	7767
6822	7768	/* reg_rtdp_ipip_irif
..	..	@@ -7466,6 +8412,35 @@
7466	8412	*p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
7467	8413	}
7468	8414
	8415	+/* FORE - Fan Out of Range Event Register
	8416	+ * --------------------------------------
	8417	+ * This register reports the status of the controlled fans compared to the
	8418	+ * range defined by the MFSL register.
	8419	+ */
	8420	+#define MLXSW_REG_FORE_ID 0x9007
	8421	+#define MLXSW_REG_FORE_LEN 0x0C
	8422	+
	8423	+MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN);
	8424	+
	8425	+/* fan_under_limit
	8426	+ * Fan speed is below the low limit defined in MFSL register. Each bit relates
	8427	+ * to a single tachometer and indicates the specific tachometer reading is
	8428	+ * below the threshold.
	8429	+ * Access: RO
	8430	+ */
	8431	+MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10);
	8432	+
	8433	+static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho,
	8434	+ bool *fault)
	8435	+{
	8436	+ u16 limit;
	8437	+
	8438	+ if (fault) {
	8439	+ limit = mlxsw_reg_fore_fan_under_limit_get(payload);
	8440	+ *fault = limit & BIT(tacho);
	8441	+ }
	8442	+}
	8443	+
7469	8444	/* MTCAP - Management Temperature Capabilities
7470	8445	* -------------------------------------------
7471	8446	* This register exposes the capabilities of the device and
..	..	@@ -7494,16 +8469,21 @@
7494	8469
7495	8470	MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
7496	8471
	8472	+#define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64
	8473	+#define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256
7497	8474	/* reg_mtmp_sensor_index
7498	8475	* Sensors index to access.
7499	8476	* 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially
7500	8477	* (module 0 is mapped to sensor_index 64).
7501	8478	* Access: Index
7502	8479	*/
7503		-MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
	8480	+MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12);
7504	8481
7505	8482	/* Convert to milli degrees Celsius */
7506		-#define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
	8483	+#define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \
	8484	+ ((v_) >= 0) ? ((v_) * 125) : \
	8485	+ ((s16)((GENMASK(15, 0) + (v_) + 1) \
	8486	+ * 125)); })
7507	8487
7508	8488	/* reg_mtmp_temperature
7509	8489	* Temperature reading from the sensor. Reading is in 0.125 Celsius
..	..	@@ -7538,6 +8518,13 @@
7538	8518	* 2 - Generate single event
7539	8519	* Access: RW
7540	8520	*/
	8521	+
	8522	+enum mlxsw_reg_mtmp_tee {
	8523	+ MLXSW_REG_MTMP_TEE_NO_EVENT,
	8524	+ MLXSW_REG_MTMP_TEE_GENERATE_EVENT,
	8525	+ MLXSW_REG_MTMP_TEE_GENERATE_SINGLE_EVENT,
	8526	+};
	8527	+
7541	8528	MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
7542	8529
7543	8530	#define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */
..	..	@@ -7548,6 +8535,7 @@
7548	8535	*/
7549	8536	MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
7550	8537
	8538	+#define MLXSW_REG_MTMP_HYSTERESIS_TEMP 0x28 /* 5 Celsius */
7551	8539	/* reg_mtmp_temperature_threshold_lo
7552	8540	* Low threshold for Temperature Warning Event. In 0.125 Celsius.
7553	8541	* Access: RW
..	..	@@ -7562,7 +8550,7 @@
7562	8550	*/
7563	8551	MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
7564	8552
7565		-static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
	8553	+static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index,
7566	8554	bool max_temp_enable,
7567	8555	bool max_temp_reset)
7568	8556	{
..	..	@@ -7574,11 +8562,10 @@
7574	8562	MLXSW_REG_MTMP_THRESH_HI);
7575	8563	}
7576	8564
7577		-static inline void mlxsw_reg_mtmp_unpack(char payload, unsigned int p_temp,
7578		- unsigned int *p_max_temp,
7579		- char *sensor_name)
	8565	+static inline void mlxsw_reg_mtmp_unpack(char payload, int p_temp,
	8566	+ int p_max_temp, char sensor_name)
7580	8567	{
7581		- u16 temp;
	8568	+ s16 temp;
7582	8569
7583	8570	if (p_temp) {
7584	8571	temp = mlxsw_reg_mtmp_temperature_get(payload);
..	..	@@ -7590,6 +8577,97 @@
7590	8577	}
7591	8578	if (sensor_name)
7592	8579	mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
	8580	+}
	8581	+
	8582	+/* MTWE - Management Temperature Warning Event
	8583	+ * -------------------------------------------
	8584	+ * This register is used for over temperature warning.
	8585	+ */
	8586	+#define MLXSW_REG_MTWE_ID 0x900B
	8587	+#define MLXSW_REG_MTWE_LEN 0x10
	8588	+
	8589	+MLXSW_REG_DEFINE(mtwe, MLXSW_REG_MTWE_ID, MLXSW_REG_MTWE_LEN);
	8590	+
	8591	+/* reg_mtwe_sensor_warning
	8592	+ * Bit vector indicating which of the sensor reading is above threshold.
	8593	+ * Address 00h bit31 is sensor_warning[127].
	8594	+ * Address 0Ch bit0 is sensor_warning[0].
	8595	+ * Access: RO
	8596	+ */
	8597	+MLXSW_ITEM_BIT_ARRAY(reg, mtwe, sensor_warning, 0x0, 0x10, 1);
	8598	+
	8599	+/* MTBR - Management Temperature Bulk Register
	8600	+ * -------------------------------------------
	8601	+ * This register is used for bulk temperature reading.
	8602	+ */
	8603	+#define MLXSW_REG_MTBR_ID 0x900F
	8604	+#define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */
	8605	+#define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */
	8606	+#define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */
	8607	+#define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \
	8608	+ MLXSW_REG_MTBR_REC_LEN * \
	8609	+ MLXSW_REG_MTBR_REC_MAX_COUNT)
	8610	+
	8611	+MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN);
	8612	+
	8613	+/* reg_mtbr_base_sensor_index
	8614	+ * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors,
	8615	+ * 64-127 are mapped to the SFP+/QSFP modules sequentially).
	8616	+ * Access: Index
	8617	+ */
	8618	+MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12);
	8619	+
	8620	+/* reg_mtbr_num_rec
	8621	+ * Request: Number of records to read
	8622	+ * Response: Number of records read
	8623	+ * See above description for more details.
	8624	+ * Range 1..255
	8625	+ * Access: RW
	8626	+ */
	8627	+MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8);
	8628	+
	8629	+/* reg_mtbr_rec_max_temp
	8630	+ * The highest measured temperature from the sensor.
	8631	+ * When the bit mte is cleared, the field max_temperature is reserved.
	8632	+ * Access: RO
	8633	+ */
	8634	+MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16,
	8635	+ 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false);
	8636	+
	8637	+/* reg_mtbr_rec_temp
	8638	+ * Temperature reading from the sensor. Reading is in 0..125 Celsius
	8639	+ * degrees units.
	8640	+ * Access: RO
	8641	+ */
	8642	+MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16,
	8643	+ MLXSW_REG_MTBR_REC_LEN, 0x00, false);
	8644	+
	8645	+static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index,
	8646	+ u8 num_rec)
	8647	+{
	8648	+ MLXSW_REG_ZERO(mtbr, payload);
	8649	+ mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index);
	8650	+ mlxsw_reg_mtbr_num_rec_set(payload, num_rec);
	8651	+}
	8652	+
	8653	+/* Error codes from temperatute reading */
	8654	+enum mlxsw_reg_mtbr_temp_status {
	8655	+ MLXSW_REG_MTBR_NO_CONN = 0x8000,
	8656	+ MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001,
	8657	+ MLXSW_REG_MTBR_INDEX_NA = 0x8002,
	8658	+ MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003,
	8659	+};
	8660	+
	8661	+/* Base index for reading modules temperature */
	8662	+#define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64
	8663	+
	8664	+static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind,
	8665	+ u16 p_temp, u16 p_max_temp)
	8666	+{
	8667	+ if (p_temp)
	8668	+ *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind);
	8669	+ if (p_max_temp)
	8670	+ *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind);
7593	8671	}
7594	8672
7595	8673	/* MCIA - Management Cable Info Access
..	..	@@ -7646,13 +8724,53 @@
7646	8724	*/
7647	8725	MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
7648	8726
7649		-#define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48
	8727	+#define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256
	8728	+#define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128
	8729	+#define MLXSW_REG_MCIA_EEPROM_SIZE 48
	8730	+#define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50
	8731	+#define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51
	8732	+#define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0
	8733	+#define MLXSW_REG_MCIA_TH_ITEM_SIZE 2
	8734	+#define MLXSW_REG_MCIA_TH_PAGE_NUM 3
	8735	+#define MLXSW_REG_MCIA_TH_PAGE_CMIS_NUM 2
	8736	+#define MLXSW_REG_MCIA_PAGE0_LO 0
	8737	+#define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80
	8738	+#define MLXSW_REG_MCIA_EEPROM_CMIS_FLAT_MEMORY BIT(7)
	8739	+
	8740	+enum mlxsw_reg_mcia_eeprom_module_info_rev_id {
	8741	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00,
	8742	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01,
	8743	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03,
	8744	+};
	8745	+
	8746	+enum mlxsw_reg_mcia_eeprom_module_info_id {
	8747	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03,
	8748	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C,
	8749	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D,
	8750	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11,
	8751	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18,
	8752	+};
	8753	+
	8754	+enum mlxsw_reg_mcia_eeprom_module_info {
	8755	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID,
	8756	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID,
	8757	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_TYPE_ID,
	8758	+ MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE,
	8759	+};
7650	8760
7651	8761	/* reg_mcia_eeprom
7652	8762	* Bytes to read/write.
7653	8763	* Access: RW
7654	8764	*/
7655		-MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
	8765	+MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE);
	8766	+
	8767	+/* This is used to access the optional upper pages (1-3) in the QSFP+
	8768	+ * memory map. Page 1 is available on offset 256 through 383, page 2 -
	8769	+ * on offset 384 through 511, page 3 - on offset 512 through 639.
	8770	+ */
	8771	+#define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \
	8772	+ MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \
	8773	+ MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1)
7656	8774
7657	8775	static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
7658	8776	u8 page_number, u16 device_addr,
..	..	@@ -7682,6 +8800,13 @@
7682	8800	* Access: Index
7683	8801	*/
7684	8802	MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
	8803	+
	8804	+/* reg_mpat_session_id
	8805	+ * Mirror Session ID.
	8806	+ * Used for MIRROR_SESSION<i> trap.
	8807	+ * Access: RW
	8808	+ */
	8809	+MLXSW_ITEM32(reg, mpat, session_id, 0x00, 24, 4);
7685	8810
7686	8811	/* reg_mpat_system_port
7687	8812	* A unique port identifier for the final destination of the packet.
..	..	@@ -7739,6 +8864,18 @@
7739	8864	* Access: RW
7740	8865	*/
7741	8866	MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
	8867	+
	8868	+/* reg_mpat_pide
	8869	+ * Policer enable.
	8870	+ * Access: RW
	8871	+ */
	8872	+MLXSW_ITEM32(reg, mpat, pide, 0x0C, 15, 1);
	8873	+
	8874	+/* reg_mpat_pid
	8875	+ * Policer ID.
	8876	+ * Access: RW
	8877	+ */
	8878	+MLXSW_ITEM32(reg, mpat, pid, 0x0C, 0, 14);
7742	8879
7743	8880	/* Remote SPAN - Ethernet VLAN
7744	8881	* - - - - - - - - - - - - - -
..	..	@@ -7878,7 +9015,7 @@
7878	9015	* properties.
7879	9016	*/
7880	9017	#define MLXSW_REG_MPAR_ID 0x901B
7881		-#define MLXSW_REG_MPAR_LEN 0x08
	9018	+#define MLXSW_REG_MPAR_LEN 0x0C
7882	9019
7883	9020	MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
7884	9021
..	..	@@ -7921,6 +9058,60 @@
7921	9058	mlxsw_reg_mpar_enable_set(payload, enable);
7922	9059	mlxsw_reg_mpar_i_e_set(payload, i_e);
7923	9060	mlxsw_reg_mpar_pa_id_set(payload, pa_id);
	9061	+}
	9062	+
	9063	+/* MGIR - Management General Information Register
	9064	+ * ----------------------------------------------
	9065	+ * MGIR register allows software to query the hardware and firmware general
	9066	+ * information.
	9067	+ */
	9068	+#define MLXSW_REG_MGIR_ID 0x9020
	9069	+#define MLXSW_REG_MGIR_LEN 0x9C
	9070	+
	9071	+MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN);
	9072	+
	9073	+/* reg_mgir_hw_info_device_hw_revision
	9074	+ * Access: RO
	9075	+ */
	9076	+MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16);
	9077	+
	9078	+#define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16
	9079	+
	9080	+/* reg_mgir_fw_info_psid
	9081	+ * PSID (ASCII string).
	9082	+ * Access: RO
	9083	+ */
	9084	+MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE);
	9085	+
	9086	+/* reg_mgir_fw_info_extended_major
	9087	+ * Access: RO
	9088	+ */
	9089	+MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32);
	9090	+
	9091	+/* reg_mgir_fw_info_extended_minor
	9092	+ * Access: RO
	9093	+ */
	9094	+MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32);
	9095	+
	9096	+/* reg_mgir_fw_info_extended_sub_minor
	9097	+ * Access: RO
	9098	+ */
	9099	+MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32);
	9100	+
	9101	+static inline void mlxsw_reg_mgir_pack(char *payload)
	9102	+{
	9103	+ MLXSW_REG_ZERO(mgir, payload);
	9104	+}
	9105	+
	9106	+static inline void
	9107	+mlxsw_reg_mgir_unpack(char payload, u32 hw_rev, char *fw_info_psid,
	9108	+ u32 fw_major, u32 fw_minor, u32 *fw_sub_minor)
	9109	+{
	9110	+ *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload);
	9111	+ mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid);
	9112	+ *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload);
	9113	+ *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload);
	9114	+ *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload);
7924	9115	}
7925	9116
7926	9117	/* MRSR - Management Reset and Shutdown Register
..	..	@@ -7986,6 +9177,107 @@
7986	9177	mlxsw_reg_mlcr_local_port_set(payload, local_port);
7987	9178	mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
7988	9179	MLXSW_REG_MLCR_DURATION_MAX : 0);
	9180	+}
	9181	+
	9182	+/* MTPPS - Management Pulse Per Second Register
	9183	+ * --------------------------------------------
	9184	+ * This register provides the device PPS capabilities, configure the PPS in and
	9185	+ * out modules and holds the PPS in time stamp.
	9186	+ */
	9187	+#define MLXSW_REG_MTPPS_ID 0x9053
	9188	+#define MLXSW_REG_MTPPS_LEN 0x3C
	9189	+
	9190	+MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN);
	9191	+
	9192	+/* reg_mtpps_enable
	9193	+ * Enables the PPS functionality the specific pin.
	9194	+ * A boolean variable.
	9195	+ * Access: RW
	9196	+ */
	9197	+MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1);
	9198	+
	9199	+enum mlxsw_reg_mtpps_pin_mode {
	9200	+ MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2,
	9201	+};
	9202	+
	9203	+/* reg_mtpps_pin_mode
	9204	+ * Pin mode to be used. The mode must comply with the supported modes of the
	9205	+ * requested pin.
	9206	+ * Access: RW
	9207	+ */
	9208	+MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4);
	9209	+
	9210	+#define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7
	9211	+
	9212	+/* reg_mtpps_pin
	9213	+ * Pin to be configured or queried out of the supported pins.
	9214	+ * Access: Index
	9215	+ */
	9216	+MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8);
	9217	+
	9218	+/* reg_mtpps_time_stamp
	9219	+ * When pin_mode = pps_in, the latched device time when it was triggered from
	9220	+ * the external GPIO pin.
	9221	+ * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target
	9222	+ * time to generate next output signal.
	9223	+ * Time is in units of device clock.
	9224	+ * Access: RW
	9225	+ */
	9226	+MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64);
	9227	+
	9228	+static inline void
	9229	+mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp)
	9230	+{
	9231	+ MLXSW_REG_ZERO(mtpps, payload);
	9232	+ mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN);
	9233	+ mlxsw_reg_mtpps_pin_mode_set(payload,
	9234	+ MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN);
	9235	+ mlxsw_reg_mtpps_enable_set(payload, true);
	9236	+ mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp);
	9237	+}
	9238	+
	9239	+/* MTUTC - Management UTC Register
	9240	+ * -------------------------------
	9241	+ * Configures the HW UTC counter.
	9242	+ */
	9243	+#define MLXSW_REG_MTUTC_ID 0x9055
	9244	+#define MLXSW_REG_MTUTC_LEN 0x1C
	9245	+
	9246	+MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN);
	9247	+
	9248	+enum mlxsw_reg_mtutc_operation {
	9249	+ MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0,
	9250	+ MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3,
	9251	+};
	9252	+
	9253	+/* reg_mtutc_operation
	9254	+ * Operation.
	9255	+ * Access: OP
	9256	+ */
	9257	+MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4);
	9258	+
	9259	+/* reg_mtutc_freq_adjustment
	9260	+ * Frequency adjustment: Every PPS the HW frequency will be
	9261	+ * adjusted by this value. Units of HW clock, where HW counts
	9262	+ * 10^9 HW clocks for 1 HW second.
	9263	+ * Access: RW
	9264	+ */
	9265	+MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32);
	9266	+
	9267	+/* reg_mtutc_utc_sec
	9268	+ * UTC seconds.
	9269	+ * Access: WO
	9270	+ */
	9271	+MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32);
	9272	+
	9273	+static inline void
	9274	+mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper,
	9275	+ u32 freq_adj, u32 utc_sec)
	9276	+{
	9277	+ MLXSW_REG_ZERO(mtutc, payload);
	9278	+ mlxsw_reg_mtutc_operation_set(payload, oper);
	9279	+ mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj);
	9280	+ mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec);
7989	9281	}
7990	9282
7991	9283	/* MCQI - Management Component Query Information
..	..	@@ -8299,6 +9591,983 @@
8299	9591	mlxsw_reg_mgpc_opcode_set(payload, opcode);
8300	9592	}
8301	9593
	9594	+/* MPRS - Monitoring Parsing State Register
	9595	+ * ----------------------------------------
	9596	+ * The MPRS register is used for setting up the parsing for hash,
	9597	+ * policy-engine and routing.
	9598	+ */
	9599	+#define MLXSW_REG_MPRS_ID 0x9083
	9600	+#define MLXSW_REG_MPRS_LEN 0x14
	9601	+
	9602	+MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN);
	9603	+
	9604	+/* reg_mprs_parsing_depth
	9605	+ * Minimum parsing depth.
	9606	+ * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL
	9607	+ * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2.
	9608	+ * Access: RW
	9609	+ */
	9610	+MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16);
	9611	+
	9612	+/* reg_mprs_parsing_en
	9613	+ * Parsing enable.
	9614	+ * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and
	9615	+ * NVGRE. Default is enabled. Reserved when SwitchX-2.
	9616	+ * Access: RW
	9617	+ */
	9618	+MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16);
	9619	+
	9620	+/* reg_mprs_vxlan_udp_dport
	9621	+ * VxLAN UDP destination port.
	9622	+ * Used for identifying VxLAN packets and for dport field in
	9623	+ * encapsulation. Default is 4789.
	9624	+ * Access: RW
	9625	+ */
	9626	+MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16);
	9627	+
	9628	+static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth,
	9629	+ u16 vxlan_udp_dport)
	9630	+{
	9631	+ MLXSW_REG_ZERO(mprs, payload);
	9632	+ mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth);
	9633	+ mlxsw_reg_mprs_parsing_en_set(payload, true);
	9634	+ mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport);
	9635	+}
	9636	+
	9637	+/* MOGCR - Monitoring Global Configuration Register
	9638	+ * ------------------------------------------------
	9639	+ */
	9640	+#define MLXSW_REG_MOGCR_ID 0x9086
	9641	+#define MLXSW_REG_MOGCR_LEN 0x20
	9642	+
	9643	+MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN);
	9644	+
	9645	+/* reg_mogcr_ptp_iftc
	9646	+ * PTP Ingress FIFO Trap Clear
	9647	+ * The PTP_ING_FIFO trap provides MTPPTR with clr according
	9648	+ * to this value. Default 0.
	9649	+ * Reserved when IB switches and when SwitchX/-2, Spectrum-2
	9650	+ * Access: RW
	9651	+ */
	9652	+MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1);
	9653	+
	9654	+/* reg_mogcr_ptp_eftc
	9655	+ * PTP Egress FIFO Trap Clear
	9656	+ * The PTP_EGR_FIFO trap provides MTPPTR with clr according
	9657	+ * to this value. Default 0.
	9658	+ * Reserved when IB switches and when SwitchX/-2, Spectrum-2
	9659	+ * Access: RW
	9660	+ */
	9661	+MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1);
	9662	+
	9663	+/* reg_mogcr_mirroring_pid_base
	9664	+ * Base policer id for mirroring policers.
	9665	+ * Must have an even value (e.g. 1000, not 1001).
	9666	+ * Reserved when SwitchX/-2, Switch-IB/2, Spectrum-1 and Quantum.
	9667	+ * Access: RW
	9668	+ */
	9669	+MLXSW_ITEM32(reg, mogcr, mirroring_pid_base, 0x0C, 0, 14);
	9670	+
	9671	+/* MPAGR - Monitoring Port Analyzer Global Register
	9672	+ * ------------------------------------------------
	9673	+ * This register is used for global port analyzer configurations.
	9674	+ * Note: This register is not supported by current FW versions for Spectrum-1.
	9675	+ */
	9676	+#define MLXSW_REG_MPAGR_ID 0x9089
	9677	+#define MLXSW_REG_MPAGR_LEN 0x0C
	9678	+
	9679	+MLXSW_REG_DEFINE(mpagr, MLXSW_REG_MPAGR_ID, MLXSW_REG_MPAGR_LEN);
	9680	+
	9681	+enum mlxsw_reg_mpagr_trigger {
	9682	+ MLXSW_REG_MPAGR_TRIGGER_EGRESS,
	9683	+ MLXSW_REG_MPAGR_TRIGGER_INGRESS,
	9684	+ MLXSW_REG_MPAGR_TRIGGER_INGRESS_WRED,
	9685	+ MLXSW_REG_MPAGR_TRIGGER_INGRESS_SHARED_BUFFER,
	9686	+ MLXSW_REG_MPAGR_TRIGGER_INGRESS_ING_CONG,
	9687	+ MLXSW_REG_MPAGR_TRIGGER_INGRESS_EGR_CONG,
	9688	+ MLXSW_REG_MPAGR_TRIGGER_EGRESS_ECN,
	9689	+ MLXSW_REG_MPAGR_TRIGGER_EGRESS_HIGH_LATENCY,
	9690	+};
	9691	+
	9692	+/* reg_mpagr_trigger
	9693	+ * Mirror trigger.
	9694	+ * Access: Index
	9695	+ */
	9696	+MLXSW_ITEM32(reg, mpagr, trigger, 0x00, 0, 4);
	9697	+
	9698	+/* reg_mpagr_pa_id
	9699	+ * Port analyzer ID.
	9700	+ * Access: RW
	9701	+ */
	9702	+MLXSW_ITEM32(reg, mpagr, pa_id, 0x04, 0, 4);
	9703	+
	9704	+/* reg_mpagr_probability_rate
	9705	+ * Sampling rate.
	9706	+ * Valid values are: 1 to 3.5*10^9
	9707	+ * Value of 1 means "sample all". Default is 1.
	9708	+ * Access: RW
	9709	+ */
	9710	+MLXSW_ITEM32(reg, mpagr, probability_rate, 0x08, 0, 32);
	9711	+
	9712	+static inline void mlxsw_reg_mpagr_pack(char *payload,
	9713	+ enum mlxsw_reg_mpagr_trigger trigger,
	9714	+ u8 pa_id, u32 probability_rate)
	9715	+{
	9716	+ MLXSW_REG_ZERO(mpagr, payload);
	9717	+ mlxsw_reg_mpagr_trigger_set(payload, trigger);
	9718	+ mlxsw_reg_mpagr_pa_id_set(payload, pa_id);
	9719	+ mlxsw_reg_mpagr_probability_rate_set(payload, probability_rate);
	9720	+}
	9721	+
	9722	+/* MOMTE - Monitoring Mirror Trigger Enable Register
	9723	+ * -------------------------------------------------
	9724	+ * This register is used to configure the mirror enable for different mirror
	9725	+ * reasons.
	9726	+ */
	9727	+#define MLXSW_REG_MOMTE_ID 0x908D
	9728	+#define MLXSW_REG_MOMTE_LEN 0x10
	9729	+
	9730	+MLXSW_REG_DEFINE(momte, MLXSW_REG_MOMTE_ID, MLXSW_REG_MOMTE_LEN);
	9731	+
	9732	+/* reg_momte_local_port
	9733	+ * Local port number.
	9734	+ * Access: Index
	9735	+ */
	9736	+MLXSW_ITEM32(reg, momte, local_port, 0x00, 16, 8);
	9737	+
	9738	+enum mlxsw_reg_momte_type {
	9739	+ MLXSW_REG_MOMTE_TYPE_WRED = 0x20,
	9740	+ MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS = 0x31,
	9741	+ MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_TCLASS_DESCRIPTORS = 0x32,
	9742	+ MLXSW_REG_MOMTE_TYPE_SHARED_BUFFER_EGRESS_PORT = 0x33,
	9743	+ MLXSW_REG_MOMTE_TYPE_ING_CONG = 0x40,
	9744	+ MLXSW_REG_MOMTE_TYPE_EGR_CONG = 0x50,
	9745	+ MLXSW_REG_MOMTE_TYPE_ECN = 0x60,
	9746	+ MLXSW_REG_MOMTE_TYPE_HIGH_LATENCY = 0x70,
	9747	+};
	9748	+
	9749	+/* reg_momte_type
	9750	+ * Type of mirroring.
	9751	+ * Access: Index
	9752	+ */
	9753	+MLXSW_ITEM32(reg, momte, type, 0x04, 0, 8);
	9754	+
	9755	+/* reg_momte_tclass_en
	9756	+ * TClass/PG mirror enable. Each bit represents corresponding tclass.
	9757	+ * 0: disable (default)
	9758	+ * 1: enable
	9759	+ * Access: RW
	9760	+ */
	9761	+MLXSW_ITEM_BIT_ARRAY(reg, momte, tclass_en, 0x08, 0x08, 1);
	9762	+
	9763	+static inline void mlxsw_reg_momte_pack(char *payload, u8 local_port,
	9764	+ enum mlxsw_reg_momte_type type)
	9765	+{
	9766	+ MLXSW_REG_ZERO(momte, payload);
	9767	+ mlxsw_reg_momte_local_port_set(payload, local_port);
	9768	+ mlxsw_reg_momte_type_set(payload, type);
	9769	+}
	9770	+
	9771	+/* MTPPPC - Time Precision Packet Port Configuration
	9772	+ * -------------------------------------------------
	9773	+ * This register serves for configuration of which PTP messages should be
	9774	+ * timestamped. This is a global configuration, despite the register name.
	9775	+ *
	9776	+ * Reserved when Spectrum-2.
	9777	+ */
	9778	+#define MLXSW_REG_MTPPPC_ID 0x9090
	9779	+#define MLXSW_REG_MTPPPC_LEN 0x28
	9780	+
	9781	+MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN);
	9782	+
	9783	+/* reg_mtpppc_ing_timestamp_message_type
	9784	+ * Bitwise vector of PTP message types to timestamp at ingress.
	9785	+ * MessageType field as defined by IEEE 1588
	9786	+ * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
	9787	+ * Default all 0
	9788	+ * Access: RW
	9789	+ */
	9790	+MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16);
	9791	+
	9792	+/* reg_mtpppc_egr_timestamp_message_type
	9793	+ * Bitwise vector of PTP message types to timestamp at egress.
	9794	+ * MessageType field as defined by IEEE 1588
	9795	+ * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req)
	9796	+ * Default all 0
	9797	+ * Access: RW
	9798	+ */
	9799	+MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16);
	9800	+
	9801	+static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr)
	9802	+{
	9803	+ MLXSW_REG_ZERO(mtpppc, payload);
	9804	+ mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing);
	9805	+ mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr);
	9806	+}
	9807	+
	9808	+/* MTPPTR - Time Precision Packet Timestamping Reading
	9809	+ * ---------------------------------------------------
	9810	+ * The MTPPTR is used for reading the per port PTP timestamp FIFO.
	9811	+ * There is a trap for packets which are latched to the timestamp FIFO, thus the
	9812	+ * SW knows which FIFO to read. Note that packets enter the FIFO before been
	9813	+ * trapped. The sequence number is used to synchronize the timestamp FIFO
	9814	+ * entries and the trapped packets.
	9815	+ * Reserved when Spectrum-2.
	9816	+ */
	9817	+
	9818	+#define MLXSW_REG_MTPPTR_ID 0x9091
	9819	+#define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */
	9820	+#define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */
	9821	+#define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4
	9822	+#define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \
	9823	+ MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT)
	9824	+
	9825	+MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN);
	9826	+
	9827	+/* reg_mtpptr_local_port
	9828	+ * Not supported for CPU port.
	9829	+ * Access: Index
	9830	+ */
	9831	+MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8);
	9832	+
	9833	+enum mlxsw_reg_mtpptr_dir {
	9834	+ MLXSW_REG_MTPPTR_DIR_INGRESS,
	9835	+ MLXSW_REG_MTPPTR_DIR_EGRESS,
	9836	+};
	9837	+
	9838	+/* reg_mtpptr_dir
	9839	+ * Direction.
	9840	+ * Access: Index
	9841	+ */
	9842	+MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1);
	9843	+
	9844	+/* reg_mtpptr_clr
	9845	+ * Clear the records.
	9846	+ * Access: OP
	9847	+ */
	9848	+MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1);
	9849	+
	9850	+/* reg_mtpptr_num_rec
	9851	+ * Number of valid records in the response
	9852	+ * Range 0.. cap_ptp_timestamp_fifo
	9853	+ * Access: RO
	9854	+ */
	9855	+MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4);
	9856	+
	9857	+/* reg_mtpptr_rec_message_type
	9858	+ * MessageType field as defined by IEEE 1588 Each bit corresponds to a value
	9859	+ * (e.g. Bit0: Sync, Bit1: Delay_Req)
	9860	+ * Access: RO
	9861	+ */
	9862	+MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type,
	9863	+ MLXSW_REG_MTPPTR_BASE_LEN, 8, 4,
	9864	+ MLXSW_REG_MTPPTR_REC_LEN, 0, false);
	9865	+
	9866	+/* reg_mtpptr_rec_domain_number
	9867	+ * DomainNumber field as defined by IEEE 1588
	9868	+ * Access: RO
	9869	+ */
	9870	+MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number,
	9871	+ MLXSW_REG_MTPPTR_BASE_LEN, 0, 8,
	9872	+ MLXSW_REG_MTPPTR_REC_LEN, 0, false);
	9873	+
	9874	+/* reg_mtpptr_rec_sequence_id
	9875	+ * SequenceId field as defined by IEEE 1588
	9876	+ * Access: RO
	9877	+ */
	9878	+MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id,
	9879	+ MLXSW_REG_MTPPTR_BASE_LEN, 0, 16,
	9880	+ MLXSW_REG_MTPPTR_REC_LEN, 0x4, false);
	9881	+
	9882	+/* reg_mtpptr_rec_timestamp_high
	9883	+ * Timestamp of when the PTP packet has passed through the port Units of PLL
	9884	+ * clock time.
	9885	+ * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec.
	9886	+ * Access: RO
	9887	+ */
	9888	+MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high,
	9889	+ MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
	9890	+ MLXSW_REG_MTPPTR_REC_LEN, 0x8, false);
	9891	+
	9892	+/* reg_mtpptr_rec_timestamp_low
	9893	+ * See rec_timestamp_high.
	9894	+ * Access: RO
	9895	+ */
	9896	+MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low,
	9897	+ MLXSW_REG_MTPPTR_BASE_LEN, 0, 32,
	9898	+ MLXSW_REG_MTPPTR_REC_LEN, 0xC, false);
	9899	+
	9900	+static inline void mlxsw_reg_mtpptr_unpack(const char *payload,
	9901	+ unsigned int rec,
	9902	+ u8 *p_message_type,
	9903	+ u8 *p_domain_number,
	9904	+ u16 *p_sequence_id,
	9905	+ u64 *p_timestamp)
	9906	+{
	9907	+ u32 timestamp_high, timestamp_low;
	9908	+
	9909	+ *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec);
	9910	+ *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec);
	9911	+ *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec);
	9912	+ timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec);
	9913	+ timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec);
	9914	+ *p_timestamp = (u64)timestamp_high << 32 \| timestamp_low;
	9915	+}
	9916	+
	9917	+/* MTPTPT - Monitoring Precision Time Protocol Trap Register
	9918	+ * ---------------------------------------------------------
	9919	+ * This register is used for configuring under which trap to deliver PTP
	9920	+ * packets depending on type of the packet.
	9921	+ */
	9922	+#define MLXSW_REG_MTPTPT_ID 0x9092
	9923	+#define MLXSW_REG_MTPTPT_LEN 0x08
	9924	+
	9925	+MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN);
	9926	+
	9927	+enum mlxsw_reg_mtptpt_trap_id {
	9928	+ MLXSW_REG_MTPTPT_TRAP_ID_PTP0,
	9929	+ MLXSW_REG_MTPTPT_TRAP_ID_PTP1,
	9930	+};
	9931	+
	9932	+/* reg_mtptpt_trap_id
	9933	+ * Trap id.
	9934	+ * Access: Index
	9935	+ */
	9936	+MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4);
	9937	+
	9938	+/* reg_mtptpt_message_type
	9939	+ * Bitwise vector of PTP message types to trap. This is a necessary but
	9940	+ * non-sufficient condition since need to enable also per port. See MTPPPC.
	9941	+ * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g.
	9942	+ * Bit0: Sync, Bit1: Delay_Req)
	9943	+ */
	9944	+MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16);
	9945	+
	9946	+static inline void mlxsw_reg_mtptptp_pack(char *payload,
	9947	+ enum mlxsw_reg_mtptpt_trap_id trap_id,
	9948	+ u16 message_type)
	9949	+{
	9950	+ MLXSW_REG_ZERO(mtptpt, payload);
	9951	+ mlxsw_reg_mtptpt_trap_id_set(payload, trap_id);
	9952	+ mlxsw_reg_mtptpt_message_type_set(payload, message_type);
	9953	+}
	9954	+
	9955	+/* MFGD - Monitoring FW General Debug Register
	9956	+ * -------------------------------------------
	9957	+ */
	9958	+#define MLXSW_REG_MFGD_ID 0x90F0
	9959	+#define MLXSW_REG_MFGD_LEN 0x0C
	9960	+
	9961	+MLXSW_REG_DEFINE(mfgd, MLXSW_REG_MFGD_ID, MLXSW_REG_MFGD_LEN);
	9962	+
	9963	+/* reg_mfgd_fw_fatal_event_mode
	9964	+ * 0 - don't check FW fatal (default)
	9965	+ * 1 - check FW fatal - enable MFDE trap
	9966	+ * Access: RW
	9967	+ */
	9968	+MLXSW_ITEM32(reg, mfgd, fatal_event_mode, 0x00, 9, 2);
	9969	+
	9970	+/* reg_mfgd_trigger_test
	9971	+ * Access: WO
	9972	+ */
	9973	+MLXSW_ITEM32(reg, mfgd, trigger_test, 0x00, 11, 1);
	9974	+
	9975	+/* MGPIR - Management General Peripheral Information Register
	9976	+ * ----------------------------------------------------------
	9977	+ * MGPIR register allows software to query the hardware and
	9978	+ * firmware general information of peripheral entities.
	9979	+ */
	9980	+#define MLXSW_REG_MGPIR_ID 0x9100
	9981	+#define MLXSW_REG_MGPIR_LEN 0xA0
	9982	+
	9983	+MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN);
	9984	+
	9985	+enum mlxsw_reg_mgpir_device_type {
	9986	+ MLXSW_REG_MGPIR_DEVICE_TYPE_NONE,
	9987	+ MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE,
	9988	+};
	9989	+
	9990	+/* device_type
	9991	+ * Access: RO
	9992	+ */
	9993	+MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4);
	9994	+
	9995	+/* devices_per_flash
	9996	+ * Number of devices of device_type per flash (can be shared by few devices).
	9997	+ * Access: RO
	9998	+ */
	9999	+MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8);
	10000	+
	10001	+/* num_of_devices
	10002	+ * Number of devices of device_type.
	10003	+ * Access: RO
	10004	+ */
	10005	+MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8);
	10006	+
	10007	+/* num_of_modules
	10008	+ * Number of modules.
	10009	+ * Access: RO
	10010	+ */
	10011	+MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8);
	10012	+
	10013	+static inline void mlxsw_reg_mgpir_pack(char *payload)
	10014	+{
	10015	+ MLXSW_REG_ZERO(mgpir, payload);
	10016	+}
	10017	+
	10018	+static inline void
	10019	+mlxsw_reg_mgpir_unpack(char payload, u8 num_of_devices,
	10020	+ enum mlxsw_reg_mgpir_device_type *device_type,
	10021	+ u8 devices_per_flash, u8 num_of_modules)
	10022	+{
	10023	+ if (num_of_devices)
	10024	+ *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload);
	10025	+ if (device_type)
	10026	+ *device_type = mlxsw_reg_mgpir_device_type_get(payload);
	10027	+ if (devices_per_flash)
	10028	+ *devices_per_flash =
	10029	+ mlxsw_reg_mgpir_devices_per_flash_get(payload);
	10030	+ if (num_of_modules)
	10031	+ *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload);
	10032	+}
	10033	+
	10034	+/* MFDE - Monitoring FW Debug Register
	10035	+ * -----------------------------------
	10036	+ */
	10037	+#define MLXSW_REG_MFDE_ID 0x9200
	10038	+#define MLXSW_REG_MFDE_LEN 0x18
	10039	+
	10040	+MLXSW_REG_DEFINE(mfde, MLXSW_REG_MFDE_ID, MLXSW_REG_MFDE_LEN);
	10041	+
	10042	+/* reg_mfde_irisc_id
	10043	+ * Which irisc triggered the event
	10044	+ * Access: RO
	10045	+ */
	10046	+MLXSW_ITEM32(reg, mfde, irisc_id, 0x00, 8, 4);
	10047	+
	10048	+enum mlxsw_reg_mfde_event_id {
	10049	+ MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO = 1,
	10050	+ /* KVD insertion machine stopped */
	10051	+ MLXSW_REG_MFDE_EVENT_ID_KVD_IM_STOP,
	10052	+};
	10053	+
	10054	+/* reg_mfde_event_id
	10055	+ * Access: RO
	10056	+ */
	10057	+MLXSW_ITEM32(reg, mfde, event_id, 0x00, 0, 8);
	10058	+
	10059	+enum mlxsw_reg_mfde_method {
	10060	+ MLXSW_REG_MFDE_METHOD_QUERY,
	10061	+ MLXSW_REG_MFDE_METHOD_WRITE,
	10062	+};
	10063	+
	10064	+/* reg_mfde_method
	10065	+ * Access: RO
	10066	+ */
	10067	+MLXSW_ITEM32(reg, mfde, method, 0x04, 29, 1);
	10068	+
	10069	+/* reg_mfde_long_process
	10070	+ * Indicates if the command is in long_process mode.
	10071	+ * Access: RO
	10072	+ */
	10073	+MLXSW_ITEM32(reg, mfde, long_process, 0x04, 28, 1);
	10074	+
	10075	+enum mlxsw_reg_mfde_command_type {
	10076	+ MLXSW_REG_MFDE_COMMAND_TYPE_MAD,
	10077	+ MLXSW_REG_MFDE_COMMAND_TYPE_EMAD,
	10078	+ MLXSW_REG_MFDE_COMMAND_TYPE_CMDIF,
	10079	+};
	10080	+
	10081	+/* reg_mfde_command_type
	10082	+ * Access: RO
	10083	+ */
	10084	+MLXSW_ITEM32(reg, mfde, command_type, 0x04, 24, 2);
	10085	+
	10086	+/* reg_mfde_reg_attr_id
	10087	+ * EMAD - register id, MAD - attibute id
	10088	+ * Access: RO
	10089	+ */
	10090	+MLXSW_ITEM32(reg, mfde, reg_attr_id, 0x04, 0, 16);
	10091	+
	10092	+/* reg_mfde_log_address
	10093	+ * crspace address accessed, which resulted in timeout.
	10094	+ * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO
	10095	+ * Access: RO
	10096	+ */
	10097	+MLXSW_ITEM32(reg, mfde, log_address, 0x10, 0, 32);
	10098	+
	10099	+/* reg_mfde_log_id
	10100	+ * Which irisc triggered the timeout.
	10101	+ * Valid in case event_id == MLXSW_REG_MFDE_EVENT_ID_CRSPACE_TO
	10102	+ * Access: RO
	10103	+ */
	10104	+MLXSW_ITEM32(reg, mfde, log_id, 0x14, 0, 4);
	10105	+
	10106	+/* reg_mfde_pipes_mask
	10107	+ * Bit per kvh pipe.
	10108	+ * Access: RO
	10109	+ */
	10110	+MLXSW_ITEM32(reg, mfde, pipes_mask, 0x10, 0, 16);
	10111	+
	10112	+/* TNGCR - Tunneling NVE General Configuration Register
	10113	+ * ----------------------------------------------------
	10114	+ * The TNGCR register is used for setting up the NVE Tunneling configuration.
	10115	+ */
	10116	+#define MLXSW_REG_TNGCR_ID 0xA001
	10117	+#define MLXSW_REG_TNGCR_LEN 0x44
	10118	+
	10119	+MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN);
	10120	+
	10121	+enum mlxsw_reg_tngcr_type {
	10122	+ MLXSW_REG_TNGCR_TYPE_VXLAN,
	10123	+ MLXSW_REG_TNGCR_TYPE_VXLAN_GPE,
	10124	+ MLXSW_REG_TNGCR_TYPE_GENEVE,
	10125	+ MLXSW_REG_TNGCR_TYPE_NVGRE,
	10126	+};
	10127	+
	10128	+/* reg_tngcr_type
	10129	+ * Tunnel type for encapsulation and decapsulation. The types are mutually
	10130	+ * exclusive.
	10131	+ * Note: For Spectrum the NVE parsing must be enabled in MPRS.
	10132	+ * Access: RW
	10133	+ */
	10134	+MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4);
	10135	+
	10136	+/* reg_tngcr_nve_valid
	10137	+ * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation.
	10138	+ * Access: RW
	10139	+ */
	10140	+MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1);
	10141	+
	10142	+/* reg_tngcr_nve_ttl_uc
	10143	+ * The TTL for NVE tunnel encapsulation underlay unicast packets.
	10144	+ * Access: RW
	10145	+ */
	10146	+MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8);
	10147	+
	10148	+/* reg_tngcr_nve_ttl_mc
	10149	+ * The TTL for NVE tunnel encapsulation underlay multicast packets.
	10150	+ * Access: RW
	10151	+ */
	10152	+MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8);
	10153	+
	10154	+enum {
	10155	+ /* Do not copy flow label. Calculate flow label using nve_flh. */
	10156	+ MLXSW_REG_TNGCR_FL_NO_COPY,
	10157	+ /* Copy flow label from inner packet if packet is IPv6 and
	10158	+ * encapsulation is by IPv6. Otherwise, calculate flow label using
	10159	+ * nve_flh.
	10160	+ */
	10161	+ MLXSW_REG_TNGCR_FL_COPY,
	10162	+};
	10163	+
	10164	+/* reg_tngcr_nve_flc
	10165	+ * For NVE tunnel encapsulation: Flow label copy from inner packet.
	10166	+ * Access: RW
	10167	+ */
	10168	+MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1);
	10169	+
	10170	+enum {
	10171	+ /* Flow label is static. In Spectrum this means '0'. Spectrum-2
	10172	+ * uses {nve_fl_prefix, nve_fl_suffix}.
	10173	+ */
	10174	+ MLXSW_REG_TNGCR_FL_NO_HASH,
	10175	+ /* 8 LSBs of the flow label are calculated from ECMP hash of the
	10176	+ * inner packet. 12 MSBs are configured by nve_fl_prefix.
	10177	+ */
	10178	+ MLXSW_REG_TNGCR_FL_HASH,
	10179	+};
	10180	+
	10181	+/* reg_tngcr_nve_flh
	10182	+ * NVE flow label hash.
	10183	+ * Access: RW
	10184	+ */
	10185	+MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1);
	10186	+
	10187	+/* reg_tngcr_nve_fl_prefix
	10188	+ * NVE flow label prefix. Constant 12 MSBs of the flow label.
	10189	+ * Access: RW
	10190	+ */
	10191	+MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12);
	10192	+
	10193	+/* reg_tngcr_nve_fl_suffix
	10194	+ * NVE flow label suffix. Constant 8 LSBs of the flow label.
	10195	+ * Reserved when nve_flh=1 and for Spectrum.
	10196	+ * Access: RW
	10197	+ */
	10198	+MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8);
	10199	+
	10200	+enum {
	10201	+ /* Source UDP port is fixed (default '0') */
	10202	+ MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH,
	10203	+ /* Source UDP port is calculated based on hash */
	10204	+ MLXSW_REG_TNGCR_UDP_SPORT_HASH,
	10205	+};
	10206	+
	10207	+/* reg_tngcr_nve_udp_sport_type
	10208	+ * NVE UDP source port type.
	10209	+ * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2).
	10210	+ * When the source UDP port is calculated based on hash, then the 8 LSBs
	10211	+ * are calculated from hash the 8 MSBs are configured by
	10212	+ * nve_udp_sport_prefix.
	10213	+ * Access: RW
	10214	+ */
	10215	+MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1);
	10216	+
	10217	+/* reg_tngcr_nve_udp_sport_prefix
	10218	+ * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port.
	10219	+ * Reserved when NVE type is NVGRE.
	10220	+ * Access: RW
	10221	+ */
	10222	+MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8);
	10223	+
	10224	+/* reg_tngcr_nve_group_size_mc
	10225	+ * The amount of sequential linked lists of MC entries. The first linked
	10226	+ * list is configured by SFD.underlay_mc_ptr.
	10227	+ * Valid values: 1, 2, 4, 8, 16, 32, 64
	10228	+ * The linked list are configured by TNUMT.
	10229	+ * The hash is set by LAG hash.
	10230	+ * Access: RW
	10231	+ */
	10232	+MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8);
	10233	+
	10234	+/* reg_tngcr_nve_group_size_flood
	10235	+ * The amount of sequential linked lists of flooding entries. The first
	10236	+ * linked list is configured by SFMR.nve_tunnel_flood_ptr
	10237	+ * Valid values: 1, 2, 4, 8, 16, 32, 64
	10238	+ * The linked list are configured by TNUMT.
	10239	+ * The hash is set by LAG hash.
	10240	+ * Access: RW
	10241	+ */
	10242	+MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8);
	10243	+
	10244	+/* reg_tngcr_learn_enable
	10245	+ * During decapsulation, whether to learn from NVE port.
	10246	+ * Reserved when Spectrum-2. See TNPC.
	10247	+ * Access: RW
	10248	+ */
	10249	+MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1);
	10250	+
	10251	+/* reg_tngcr_underlay_virtual_router
	10252	+ * Underlay virtual router.
	10253	+ * Reserved when Spectrum-2.
	10254	+ * Access: RW
	10255	+ */
	10256	+MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16);
	10257	+
	10258	+/* reg_tngcr_underlay_rif
	10259	+ * Underlay ingress router interface. RIF type should be loopback generic.
	10260	+ * Reserved when Spectrum.
	10261	+ * Access: RW
	10262	+ */
	10263	+MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16);
	10264	+
	10265	+/* reg_tngcr_usipv4
	10266	+ * Underlay source IPv4 address of the NVE.
	10267	+ * Access: RW
	10268	+ */
	10269	+MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32);
	10270	+
	10271	+/* reg_tngcr_usipv6
	10272	+ * Underlay source IPv6 address of the NVE. For Spectrum, must not be
	10273	+ * modified under traffic of NVE tunneling encapsulation.
	10274	+ * Access: RW
	10275	+ */
	10276	+MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16);
	10277	+
	10278	+static inline void mlxsw_reg_tngcr_pack(char *payload,
	10279	+ enum mlxsw_reg_tngcr_type type,
	10280	+ bool valid, u8 ttl)
	10281	+{
	10282	+ MLXSW_REG_ZERO(tngcr, payload);
	10283	+ mlxsw_reg_tngcr_type_set(payload, type);
	10284	+ mlxsw_reg_tngcr_nve_valid_set(payload, valid);
	10285	+ mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl);
	10286	+ mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl);
	10287	+ mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY);
	10288	+ mlxsw_reg_tngcr_nve_flh_set(payload, 0);
	10289	+ mlxsw_reg_tngcr_nve_udp_sport_type_set(payload,
	10290	+ MLXSW_REG_TNGCR_UDP_SPORT_HASH);
	10291	+ mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0);
	10292	+ mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1);
	10293	+ mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1);
	10294	+}
	10295	+
	10296	+/* TNUMT - Tunneling NVE Underlay Multicast Table Register
	10297	+ * -------------------------------------------------------
	10298	+ * The TNUMT register is for building the underlay MC table. It is used
	10299	+ * for MC, flooding and BC traffic into the NVE tunnel.
	10300	+ */
	10301	+#define MLXSW_REG_TNUMT_ID 0xA003
	10302	+#define MLXSW_REG_TNUMT_LEN 0x20
	10303	+
	10304	+MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN);
	10305	+
	10306	+enum mlxsw_reg_tnumt_record_type {
	10307	+ MLXSW_REG_TNUMT_RECORD_TYPE_IPV4,
	10308	+ MLXSW_REG_TNUMT_RECORD_TYPE_IPV6,
	10309	+ MLXSW_REG_TNUMT_RECORD_TYPE_LABEL,
	10310	+};
	10311	+
	10312	+/* reg_tnumt_record_type
	10313	+ * Record type.
	10314	+ * Access: RW
	10315	+ */
	10316	+MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4);
	10317	+
	10318	+enum mlxsw_reg_tnumt_tunnel_port {
	10319	+ MLXSW_REG_TNUMT_TUNNEL_PORT_NVE,
	10320	+ MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS,
	10321	+ MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0,
	10322	+ MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1,
	10323	+};
	10324	+
	10325	+/* reg_tnumt_tunnel_port
	10326	+ * Tunnel port.
	10327	+ * Access: RW
	10328	+ */
	10329	+MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4);
	10330	+
	10331	+/* reg_tnumt_underlay_mc_ptr
	10332	+ * Index to the underlay multicast table.
	10333	+ * For Spectrum the index is to the KVD linear.
	10334	+ * Access: Index
	10335	+ */
	10336	+MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24);
	10337	+
	10338	+/* reg_tnumt_vnext
	10339	+ * The next_underlay_mc_ptr is valid.
	10340	+ * Access: RW
	10341	+ */
	10342	+MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1);
	10343	+
	10344	+/* reg_tnumt_next_underlay_mc_ptr
	10345	+ * The next index to the underlay multicast table.
	10346	+ * Access: RW
	10347	+ */
	10348	+MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24);
	10349	+
	10350	+/* reg_tnumt_record_size
	10351	+ * Number of IP addresses in the record.
	10352	+ * Range is 1..cap_max_nve_mc_entries_ipv{4,6}
	10353	+ * Access: RW
	10354	+ */
	10355	+MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3);
	10356	+
	10357	+/* reg_tnumt_udip
	10358	+ * The underlay IPv4 addresses. udip[i] is reserved if i >= size
	10359	+ * Access: RW
	10360	+ */
	10361	+MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false);
	10362	+
	10363	+/* reg_tnumt_udip_ptr
	10364	+ * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if
	10365	+ * i >= size. The IPv6 addresses are configured by RIPS.
	10366	+ * Access: RW
	10367	+ */
	10368	+MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false);
	10369	+
	10370	+static inline void mlxsw_reg_tnumt_pack(char *payload,
	10371	+ enum mlxsw_reg_tnumt_record_type type,
	10372	+ enum mlxsw_reg_tnumt_tunnel_port tport,
	10373	+ u32 underlay_mc_ptr, bool vnext,
	10374	+ u32 next_underlay_mc_ptr,
	10375	+ u8 record_size)
	10376	+{
	10377	+ MLXSW_REG_ZERO(tnumt, payload);
	10378	+ mlxsw_reg_tnumt_record_type_set(payload, type);
	10379	+ mlxsw_reg_tnumt_tunnel_port_set(payload, tport);
	10380	+ mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr);
	10381	+ mlxsw_reg_tnumt_vnext_set(payload, vnext);
	10382	+ mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr);
	10383	+ mlxsw_reg_tnumt_record_size_set(payload, record_size);
	10384	+}
	10385	+
	10386	+/* TNQCR - Tunneling NVE QoS Configuration Register
	10387	+ * ------------------------------------------------
	10388	+ * The TNQCR register configures how QoS is set in encapsulation into the
	10389	+ * underlay network.
	10390	+ */
	10391	+#define MLXSW_REG_TNQCR_ID 0xA010
	10392	+#define MLXSW_REG_TNQCR_LEN 0x0C
	10393	+
	10394	+MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN);
	10395	+
	10396	+/* reg_tnqcr_enc_set_dscp
	10397	+ * For encapsulation: How to set DSCP field:
	10398	+ * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay
	10399	+ * (outer) IP header. If there is no IP header, use TNQDR.dscp
	10400	+ * 1 - Set the DSCP field as TNQDR.dscp
	10401	+ * Access: RW
	10402	+ */
	10403	+MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1);
	10404	+
	10405	+static inline void mlxsw_reg_tnqcr_pack(char *payload)
	10406	+{
	10407	+ MLXSW_REG_ZERO(tnqcr, payload);
	10408	+ mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0);
	10409	+}
	10410	+
	10411	+/* TNQDR - Tunneling NVE QoS Default Register
	10412	+ * ------------------------------------------
	10413	+ * The TNQDR register configures the default QoS settings for NVE
	10414	+ * encapsulation.
	10415	+ */
	10416	+#define MLXSW_REG_TNQDR_ID 0xA011
	10417	+#define MLXSW_REG_TNQDR_LEN 0x08
	10418	+
	10419	+MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN);
	10420	+
	10421	+/* reg_tnqdr_local_port
	10422	+ * Local port number (receive port). CPU port is supported.
	10423	+ * Access: Index
	10424	+ */
	10425	+MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8);
	10426	+
	10427	+/* reg_tnqdr_dscp
	10428	+ * For encapsulation, the default DSCP.
	10429	+ * Access: RW
	10430	+ */
	10431	+MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6);
	10432	+
	10433	+static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port)
	10434	+{
	10435	+ MLXSW_REG_ZERO(tnqdr, payload);
	10436	+ mlxsw_reg_tnqdr_local_port_set(payload, local_port);
	10437	+ mlxsw_reg_tnqdr_dscp_set(payload, 0);
	10438	+}
	10439	+
	10440	+/* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register
	10441	+ * --------------------------------------------------------
	10442	+ * The TNEEM register maps ECN of the IP header at the ingress to the
	10443	+ * encapsulation to the ECN of the underlay network.
	10444	+ */
	10445	+#define MLXSW_REG_TNEEM_ID 0xA012
	10446	+#define MLXSW_REG_TNEEM_LEN 0x0C
	10447	+
	10448	+MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN);
	10449	+
	10450	+/* reg_tneem_overlay_ecn
	10451	+ * ECN of the IP header in the overlay network.
	10452	+ * Access: Index
	10453	+ */
	10454	+MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2);
	10455	+
	10456	+/* reg_tneem_underlay_ecn
	10457	+ * ECN of the IP header in the underlay network.
	10458	+ * Access: RW
	10459	+ */
	10460	+MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2);
	10461	+
	10462	+static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn,
	10463	+ u8 underlay_ecn)
	10464	+{
	10465	+ MLXSW_REG_ZERO(tneem, payload);
	10466	+ mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn);
	10467	+ mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn);
	10468	+}
	10469	+
	10470	+/* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register
	10471	+ * --------------------------------------------------------
	10472	+ * The TNDEM register configures the actions that are done in the
	10473	+ * decapsulation.
	10474	+ */
	10475	+#define MLXSW_REG_TNDEM_ID 0xA013
	10476	+#define MLXSW_REG_TNDEM_LEN 0x0C
	10477	+
	10478	+MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN);
	10479	+
	10480	+/* reg_tndem_underlay_ecn
	10481	+ * ECN field of the IP header in the underlay network.
	10482	+ * Access: Index
	10483	+ */
	10484	+MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2);
	10485	+
	10486	+/* reg_tndem_overlay_ecn
	10487	+ * ECN field of the IP header in the overlay network.
	10488	+ * Access: Index
	10489	+ */
	10490	+MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2);
	10491	+
	10492	+/* reg_tndem_eip_ecn
	10493	+ * Egress IP ECN. ECN field of the IP header of the packet which goes out
	10494	+ * from the decapsulation.
	10495	+ * Access: RW
	10496	+ */
	10497	+MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2);
	10498	+
	10499	+/* reg_tndem_trap_en
	10500	+ * Trap enable:
	10501	+ * 0 - No trap due to decap ECN
	10502	+ * 1 - Trap enable with trap_id
	10503	+ * Access: RW
	10504	+ */
	10505	+MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4);
	10506	+
	10507	+/* reg_tndem_trap_id
	10508	+ * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
	10509	+ * Reserved when trap_en is '0'.
	10510	+ * Access: RW
	10511	+ */
	10512	+MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9);
	10513	+
	10514	+static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn,
	10515	+ u8 overlay_ecn, u8 ecn, bool trap_en,
	10516	+ u16 trap_id)
	10517	+{
	10518	+ MLXSW_REG_ZERO(tndem, payload);
	10519	+ mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn);
	10520	+ mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn);
	10521	+ mlxsw_reg_tndem_eip_ecn_set(payload, ecn);
	10522	+ mlxsw_reg_tndem_trap_en_set(payload, trap_en);
	10523	+ mlxsw_reg_tndem_trap_id_set(payload, trap_id);
	10524	+}
	10525	+
	10526	+/* TNPC - Tunnel Port Configuration Register
	10527	+ * -----------------------------------------
	10528	+ * The TNPC register is used for tunnel port configuration.
	10529	+ * Reserved when Spectrum.
	10530	+ */
	10531	+#define MLXSW_REG_TNPC_ID 0xA020
	10532	+#define MLXSW_REG_TNPC_LEN 0x18
	10533	+
	10534	+MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN);
	10535	+
	10536	+enum mlxsw_reg_tnpc_tunnel_port {
	10537	+ MLXSW_REG_TNPC_TUNNEL_PORT_NVE,
	10538	+ MLXSW_REG_TNPC_TUNNEL_PORT_VPLS,
	10539	+ MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0,
	10540	+ MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1,
	10541	+};
	10542	+
	10543	+/* reg_tnpc_tunnel_port
	10544	+ * Tunnel port.
	10545	+ * Access: Index
	10546	+ */
	10547	+MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4);
	10548	+
	10549	+/* reg_tnpc_learn_enable_v6
	10550	+ * During IPv6 underlay decapsulation, whether to learn from tunnel port.
	10551	+ * Access: RW
	10552	+ */
	10553	+MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1);
	10554	+
	10555	+/* reg_tnpc_learn_enable_v4
	10556	+ * During IPv4 underlay decapsulation, whether to learn from tunnel port.
	10557	+ * Access: RW
	10558	+ */
	10559	+MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1);
	10560	+
	10561	+static inline void mlxsw_reg_tnpc_pack(char *payload,
	10562	+ enum mlxsw_reg_tnpc_tunnel_port tport,
	10563	+ bool learn_enable)
	10564	+{
	10565	+ MLXSW_REG_ZERO(tnpc, payload);
	10566	+ mlxsw_reg_tnpc_tunnel_port_set(payload, tport);
	10567	+ mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable);
	10568	+ mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable);
	10569	+}
	10570	+
8302	10571	/* TIGCR - Tunneling IPinIP General Configuration Register
8303	10572	* -------------------------------------------------------
8304	10573	* The TIGCR register is used for setting up the IPinIP Tunnel configuration.
..	..	@@ -8329,6 +10598,92 @@
8329	10598	mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
8330	10599	}
8331	10600
	10601	+/* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register
	10602	+ * -----------------------------------------------------------
	10603	+ * The TIEEM register maps ECN of the IP header at the ingress to the
	10604	+ * encapsulation to the ECN of the underlay network.
	10605	+ */
	10606	+#define MLXSW_REG_TIEEM_ID 0xA812
	10607	+#define MLXSW_REG_TIEEM_LEN 0x0C
	10608	+
	10609	+MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN);
	10610	+
	10611	+/* reg_tieem_overlay_ecn
	10612	+ * ECN of the IP header in the overlay network.
	10613	+ * Access: Index
	10614	+ */
	10615	+MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2);
	10616	+
	10617	+/* reg_tineem_underlay_ecn
	10618	+ * ECN of the IP header in the underlay network.
	10619	+ * Access: RW
	10620	+ */
	10621	+MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2);
	10622	+
	10623	+static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn,
	10624	+ u8 underlay_ecn)
	10625	+{
	10626	+ MLXSW_REG_ZERO(tieem, payload);
	10627	+ mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn);
	10628	+ mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn);
	10629	+}
	10630	+
	10631	+/* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register
	10632	+ * -----------------------------------------------------------
	10633	+ * The TIDEM register configures the actions that are done in the
	10634	+ * decapsulation.
	10635	+ */
	10636	+#define MLXSW_REG_TIDEM_ID 0xA813
	10637	+#define MLXSW_REG_TIDEM_LEN 0x0C
	10638	+
	10639	+MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN);
	10640	+
	10641	+/* reg_tidem_underlay_ecn
	10642	+ * ECN field of the IP header in the underlay network.
	10643	+ * Access: Index
	10644	+ */
	10645	+MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2);
	10646	+
	10647	+/* reg_tidem_overlay_ecn
	10648	+ * ECN field of the IP header in the overlay network.
	10649	+ * Access: Index
	10650	+ */
	10651	+MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2);
	10652	+
	10653	+/* reg_tidem_eip_ecn
	10654	+ * Egress IP ECN. ECN field of the IP header of the packet which goes out
	10655	+ * from the decapsulation.
	10656	+ * Access: RW
	10657	+ */
	10658	+MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2);
	10659	+
	10660	+/* reg_tidem_trap_en
	10661	+ * Trap enable:
	10662	+ * 0 - No trap due to decap ECN
	10663	+ * 1 - Trap enable with trap_id
	10664	+ * Access: RW
	10665	+ */
	10666	+MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4);
	10667	+
	10668	+/* reg_tidem_trap_id
	10669	+ * Trap ID. Either DECAP_ECN0 or DECAP_ECN1.
	10670	+ * Reserved when trap_en is '0'.
	10671	+ * Access: RW
	10672	+ */
	10673	+MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9);
	10674	+
	10675	+static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn,
	10676	+ u8 overlay_ecn, u8 eip_ecn,
	10677	+ bool trap_en, u16 trap_id)
	10678	+{
	10679	+ MLXSW_REG_ZERO(tidem, payload);
	10680	+ mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn);
	10681	+ mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn);
	10682	+ mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn);
	10683	+ mlxsw_reg_tidem_trap_en_set(payload, trap_en);
	10684	+ mlxsw_reg_tidem_trap_id_set(payload, trap_id);
	10685	+}
	10686	+
8332	10687	/* SBPR - Shared Buffer Pools Register
8333	10688	* -----------------------------------
8334	10689	* The SBPR configures and retrieves the shared buffer pools and configuration.
..	..	@@ -8356,8 +10711,15 @@
8356	10711	*/
8357	10712	MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
8358	10713
	10714	+/* reg_sbpr_infi_size
	10715	+ * Size is infinite.
	10716	+ * Access: RW
	10717	+ */
	10718	+MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1);
	10719	+
8359	10720	/* reg_sbpr_size
8360	10721	* Pool size in buffer cells.
	10722	+ * Reserved when infi_size = 1.
8361	10723	* Access: RW
8362	10724	*/
8363	10725	MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
..	..	@@ -8375,13 +10737,15 @@
8375	10737
8376	10738	static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
8377	10739	enum mlxsw_reg_sbxx_dir dir,
8378		- enum mlxsw_reg_sbpr_mode mode, u32 size)
	10740	+ enum mlxsw_reg_sbpr_mode mode, u32 size,
	10741	+ bool infi_size)
8379	10742	{
8380	10743	MLXSW_REG_ZERO(sbpr, payload);
8381	10744	mlxsw_reg_sbpr_pool_set(payload, pool);
8382	10745	mlxsw_reg_sbpr_dir_set(payload, dir);
8383	10746	mlxsw_reg_sbpr_mode_set(payload, mode);
8384	10747	mlxsw_reg_sbpr_size_set(payload, size);
	10748	+ mlxsw_reg_sbpr_infi_size_set(payload, infi_size);
8385	10749	}
8386	10750
8387	10751	/* SBCM - Shared Buffer Class Management Register
..	..	@@ -8429,6 +10793,12 @@
8429	10793	#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
8430	10794	#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
8431	10795
	10796	+/* reg_sbcm_infi_max
	10797	+ * Max buffer is infinite.
	10798	+ * Access: RW
	10799	+ */
	10800	+MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1);
	10801	+
8432	10802	/* reg_sbcm_max_buff
8433	10803	* When the pool associated to the port-pg/tclass is configured to
8434	10804	* static, Maximum buffer size for the limiter configured in cells.
..	..	@@ -8438,6 +10808,7 @@
8438	10808	* 0: 0
8439	10809	* i: (1/128)*2^(i-1), for i=1..14
8440	10810	* 0xFF: Infinity
	10811	+ * Reserved when infi_max = 1.
8441	10812	* Access: RW
8442	10813	*/
8443	10814	MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
..	..	@@ -8450,7 +10821,8 @@
8450	10821
8451	10822	static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
8452	10823	enum mlxsw_reg_sbxx_dir dir,
8453		- u32 min_buff, u32 max_buff, u8 pool)
	10824	+ u32 min_buff, u32 max_buff,
	10825	+ bool infi_max, u8 pool)
8454	10826	{
8455	10827	MLXSW_REG_ZERO(sbcm, payload);
8456	10828	mlxsw_reg_sbcm_local_port_set(payload, local_port);
..	..	@@ -8458,6 +10830,7 @@
8458	10830	mlxsw_reg_sbcm_dir_set(payload, dir);
8459	10831	mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
8460	10832	mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
	10833	+ mlxsw_reg_sbcm_infi_max_set(payload, infi_max);
8461	10834	mlxsw_reg_sbcm_pool_set(payload, pool);
8462	10835	}
8463	10836
..	..	@@ -8768,8 +11141,10 @@
8768	11141	MLXSW_REG(ppbs),
8769	11142	MLXSW_REG(prcr),
8770	11143	MLXSW_REG(pefa),
	11144	+ MLXSW_REG(pemrbt),
8771	11145	MLXSW_REG(ptce2),
8772	11146	MLXSW_REG(perpt),
	11147	+ MLXSW_REG(peabfe),
8773	11148	MLXSW_REG(perar),
8774	11149	MLXSW_REG(ptce3),
8775	11150	MLXSW_REG(percr),
..	..	@@ -8781,8 +11156,10 @@
8781	11156	MLXSW_REG(qeec),
8782	11157	MLXSW_REG(qrwe),
8783	11158	MLXSW_REG(qpdsm),
	11159	+ MLXSW_REG(qpdp),
8784	11160	MLXSW_REG(qpdpm),
8785	11161	MLXSW_REG(qtctm),
	11162	+ MLXSW_REG(qpsc),
8786	11163	MLXSW_REG(pmlp),
8787	11164	MLXSW_REG(pmtu),
8788	11165	MLXSW_REG(ptys),
..	..	@@ -8794,6 +11171,11 @@
8794	11171	MLXSW_REG(pptb),
8795	11172	MLXSW_REG(pbmc),
8796	11173	MLXSW_REG(pspa),
	11174	+ MLXSW_REG(pmaos),
	11175	+ MLXSW_REG(pplr),
	11176	+ MLXSW_REG(pmpe),
	11177	+ MLXSW_REG(pddr),
	11178	+ MLXSW_REG(pmtm),
8797	11179	MLXSW_REG(htgt),
8798	11180	MLXSW_REG(hpkt),
8799	11181	MLXSW_REG(rgcr),
..	..	@@ -8818,19 +11200,44 @@
8818	11200	MLXSW_REG(mfsc),
8819	11201	MLXSW_REG(mfsm),
8820	11202	MLXSW_REG(mfsl),
	11203	+ MLXSW_REG(fore),
8821	11204	MLXSW_REG(mtcap),
8822	11205	MLXSW_REG(mtmp),
	11206	+ MLXSW_REG(mtwe),
	11207	+ MLXSW_REG(mtbr),
8823	11208	MLXSW_REG(mcia),
8824	11209	MLXSW_REG(mpat),
8825	11210	MLXSW_REG(mpar),
	11211	+ MLXSW_REG(mgir),
8826	11212	MLXSW_REG(mrsr),
8827	11213	MLXSW_REG(mlcr),
	11214	+ MLXSW_REG(mtpps),
	11215	+ MLXSW_REG(mtutc),
8828	11216	MLXSW_REG(mpsc),
8829	11217	MLXSW_REG(mcqi),
8830	11218	MLXSW_REG(mcc),
8831	11219	MLXSW_REG(mcda),
8832	11220	MLXSW_REG(mgpc),
	11221	+ MLXSW_REG(mprs),
	11222	+ MLXSW_REG(mogcr),
	11223	+ MLXSW_REG(mpagr),
	11224	+ MLXSW_REG(momte),
	11225	+ MLXSW_REG(mtpppc),
	11226	+ MLXSW_REG(mtpptr),
	11227	+ MLXSW_REG(mtptpt),
	11228	+ MLXSW_REG(mfgd),
	11229	+ MLXSW_REG(mgpir),
	11230	+ MLXSW_REG(mfde),
	11231	+ MLXSW_REG(tngcr),
	11232	+ MLXSW_REG(tnumt),
	11233	+ MLXSW_REG(tnqcr),
	11234	+ MLXSW_REG(tnqdr),
	11235	+ MLXSW_REG(tneem),
	11236	+ MLXSW_REG(tndem),
	11237	+ MLXSW_REG(tnpc),
8833	11238	MLXSW_REG(tigcr),
	11239	+ MLXSW_REG(tieem),
	11240	+ MLXSW_REG(tidem),
8834	11241	MLXSW_REG(sbpr),
8835	11242	MLXSW_REG(sbcm),
8836	11243	MLXSW_REG(sbpm),