add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/drivers/net/ethernet/mellanox/mlxsw/pci_hw.h
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@@ -25,10 +25,8 @@
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 #define MLXSW_PCI_CIR_CTRL_STATUS_SHIFT		24
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 #define MLXSW_PCI_CIR_TIMEOUT_MSECS		1000
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-#define MLXSW_PCI_SW_RESET			0xF0010
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-#define MLXSW_PCI_SW_RESET_RST_BIT		BIT(0)
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-#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS	20000
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-#define MLXSW_PCI_SW_RESET_WAIT_MSECS		100
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+#define MLXSW_PCI_SW_RESET_TIMEOUT_MSECS	900000
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+#define MLXSW_PCI_SW_RESET_WAIT_MSECS		400
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 #define MLXSW_PCI_FW_READY			0xA1844
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 #define MLXSW_PCI_FW_READY_MASK			0xFFFF
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 #define MLXSW_PCI_FW_READY_MAGIC		0x5E
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@@ -43,10 +41,18 @@
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 #define MLXSW_PCI_DOORBELL(offset, type_offset, num)	\
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 	((offset) + (type_offset) + (num) * 4)
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+#define MLXSW_PCI_FREE_RUNNING_CLOCK_H(offset)	(offset)
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+#define MLXSW_PCI_FREE_RUNNING_CLOCK_L(offset)	((offset) + 4)
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+
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 #define MLXSW_PCI_CQS_MAX	96
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 #define MLXSW_PCI_EQS_COUNT	2
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 #define MLXSW_PCI_EQ_ASYNC_NUM	0
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 #define MLXSW_PCI_EQ_COMP_NUM	1
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+
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+#define MLXSW_PCI_SDQS_MIN	2 /* EMAD and control traffic */
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+#define MLXSW_PCI_SDQ_EMAD_INDEX	0
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+#define MLXSW_PCI_SDQ_EMAD_TC	0
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+#define MLXSW_PCI_SDQ_CTL_TC	3
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 #define MLXSW_PCI_AQ_PAGES	8
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 #define MLXSW_PCI_AQ_SIZE	(MLXSW_PCI_PAGE_SIZE * MLXSW_PCI_AQ_PAGES)
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@@ -170,7 +176,7 @@
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 /* pci_cqe_trap_id
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  * Trap ID that captured the packet.
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  */
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-MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 9);
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+MLXSW_ITEM32(pci, cqe, trap_id, 0x08, 0, 10);
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 /* pci_cqe_crc
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  * Length include CRC. Indicates the length field includes
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@@ -202,6 +208,16 @@
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 MLXSW_ITEM32(pci, cqe12, dqn, 0x0C, 1, 6);
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 mlxsw_pci_cqe_item_helpers(dqn, 0, 12, 12);
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+/* pci_cqe_user_def_val_orig_pkt_len
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+ * When trap_id is an ACL: User defined value from policy engine action.
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+ */
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+MLXSW_ITEM32(pci, cqe2, user_def_val_orig_pkt_len, 0x14, 0, 20);
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+
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+/* pci_cqe_mirror_reason
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+ * Mirror reason.
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+ */
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+MLXSW_ITEM32(pci, cqe2, mirror_reason, 0x18, 24, 8);
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+
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 /* pci_cqe_owner
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  * Ownership bit.
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  */
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@@ -222,7 +238,7 @@
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 MLXSW_ITEM32(pci, eqe, event_sub_type, 0x0C, 16, 8);
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 /* pci_eqe_cqn
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- * Completion Queue that triggeret this EQE.
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+ * Completion Queue that triggered this EQE.
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  */
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 MLXSW_ITEM32(pci, eqe, cqn, 0x0C, 8, 7);
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