add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/drivers/net/ethernet/mellanox/mlxsw/cmd.h
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@@ -317,6 +317,18 @@
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  */
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 MLXSW_ITEM32(cmd_mbox, query_fw, doorbell_page_bar, 0x48, 30, 2);
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+/* cmd_mbox_query_fw_free_running_clock_offset
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+ * The offset of the free running clock page
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+ */
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+MLXSW_ITEM64(cmd_mbox, query_fw, free_running_clock_offset, 0x50, 0, 64);
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+
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+/* cmd_mbox_query_fw_fr_rn_clk_bar
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+ * PCI base address register (BAR) of the free running clock page
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+ * 0: BAR 0
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+ * 1: 64 bit BAR
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+ */
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+MLXSW_ITEM32(cmd_mbox, query_fw, fr_rn_clk_bar, 0x58, 30, 2);
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+
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 /* QUERY_BOARDINFO - Query Board Information
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  * -----------------------------------------
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  * OpMod == 0 (N/A), INMmod == 0 (N/A)
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@@ -893,6 +905,18 @@
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  */
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 MLXSW_ITEM32(cmd_mbox, sw2hw_dq, cq, 0x00, 24, 8);
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+enum mlxsw_cmd_mbox_sw2hw_dq_sdq_lp {
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+	MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_WQE,
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+	MLXSW_CMD_MBOX_SW2HW_DQ_SDQ_LP_IGNORE_WQE,
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+};
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+
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+/* cmd_mbox_sw2hw_dq_sdq_lp
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+ * SDQ local Processing
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+ * 0: local processing by wqe.lp
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+ * 1: local processing (ignoring wqe.lp)
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+ */
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+MLXSW_ITEM32(cmd_mbox, sw2hw_dq, sdq_lp, 0x00, 23, 1);
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+
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 /* cmd_mbox_sw2hw_dq_sdq_tclass
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  * SDQ: CPU Egress TClass
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  * RDQ: Reserved