add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/drivers/net/ethernet/mellanox/mlx5/core/en_common.c
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@@ -36,12 +36,11 @@
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  * Global resources are common to all the netdevices crated on the same nic.
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  */
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-int mlx5e_create_tir(struct mlx5_core_dev *mdev,
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-		     struct mlx5e_tir *tir, u32 *in, int inlen)
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+int mlx5e_create_tir(struct mlx5_core_dev *mdev, struct mlx5e_tir *tir, u32 *in)
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 {
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 	int err;
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-	err = mlx5_core_create_tir(mdev, in, inlen, &tir->tirn);
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+	err = mlx5_core_create_tir(mdev, in, &tir->tirn);
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 	if (err)
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 		return err;
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46
 
..
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@@ -61,6 +60,16 @@
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 	mutex_unlock(&mdev->mlx5e_res.td.list_lock);
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 }
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+void mlx5e_mkey_set_relaxed_ordering(struct mlx5_core_dev *mdev, void *mkc)
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+{
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+	bool ro_pci_enable = pcie_relaxed_ordering_enabled(mdev->pdev);
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+	bool ro_write = MLX5_CAP_GEN(mdev, relaxed_ordering_write);
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+	bool ro_read = MLX5_CAP_GEN(mdev, relaxed_ordering_read);
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+
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+	MLX5_SET(mkc, mkc, relaxed_ordering_read, ro_pci_enable && ro_read);
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+	MLX5_SET(mkc, mkc, relaxed_ordering_write, ro_pci_enable && ro_write);
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+}
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+
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 static int mlx5e_create_mkey(struct mlx5_core_dev *mdev, u32 pdn,
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 			     struct mlx5_core_mkey *mkey)
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 {
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@@ -77,7 +86,7 @@
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 	MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
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 	MLX5_SET(mkc, mkc, lw, 1);
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 	MLX5_SET(mkc, mkc, lr, 1);
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-
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+	mlx5e_mkey_set_relaxed_ordering(mdev, mkc);
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 	MLX5_SET(mkc, mkc, pd, pdn);
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 	MLX5_SET(mkc, mkc, length64, 1);
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 	MLX5_SET(mkc, mkc, qpn, 0xffffff);
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@@ -142,10 +151,12 @@
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 	memset(res, 0, sizeof(*res));
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 }
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-int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb)
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+int mlx5e_refresh_tirs(struct mlx5e_priv *priv, bool enable_uc_lb,
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+		       bool enable_mc_lb)
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 {
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 	struct mlx5_core_dev *mdev = priv->mdev;
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 	struct mlx5e_tir *tir;
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+	u8 lb_flags = 0;
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 	int err  = 0;
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 	u32 tirn = 0;
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 	int inlen;
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@@ -159,15 +170,20 @@
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 	}
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 	if (enable_uc_lb)
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-		MLX5_SET(modify_tir_in, in, ctx.self_lb_block,
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-			 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_);
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+		lb_flags = MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST;
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+
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+	if (enable_mc_lb)
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+		lb_flags |= MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST;
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+
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+	if (lb_flags)
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+		MLX5_SET(modify_tir_in, in, ctx.self_lb_block, lb_flags);
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 	MLX5_SET(modify_tir_in, in, bitmask.self_lb_en, 1);
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182
 
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 	mutex_lock(&mdev->mlx5e_res.td.list_lock);
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 	list_for_each_entry(tir, &mdev->mlx5e_res.td.tirs_list, list) {
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 		tirn = tir->tirn;
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-		err = mlx5_core_modify_tir(mdev, tirn, in, inlen);
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+		err = mlx5_core_modify_tir(mdev, tirn, in);
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 		if (err)
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 			goto out;
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 	}
..
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@@ -179,16 +195,4 @@
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 	mutex_unlock(&mdev->mlx5e_res.td.list_lock);
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 	return err;
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-}
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-
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-u8 mlx5e_params_calculate_tx_min_inline(struct mlx5_core_dev *mdev)
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-{
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-	u8 min_inline_mode;
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-
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-	mlx5_query_min_inline(mdev, &min_inline_mode);
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-	if (min_inline_mode == MLX5_INLINE_MODE_NONE &&
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-	    !MLX5_CAP_ETH(mdev, wqe_vlan_insert))
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-		min_inline_mode = MLX5_INLINE_MODE_L2;
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-
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-	return min_inline_mode;
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 }