~hc/RK356X_SDK_RELEASE.git

..	..	@@ -1,12 +1,16 @@
1		-// SPDX-License-Identifier: GPL-2.0+
	1	+/* SPDX-License-Identifier: GPL-2.0+ */
2	2	// Copyright (c) 2016-2017 Hisilicon Limited.
3	3
4	4	#ifndef __HCLGE_CMD_H
5	5	#define __HCLGE_CMD_H
6	6	#include <linux/types.h>
7	7	#include <linux/io.h>
	8	+#include <linux/etherdevice.h>
	9	+#include "hnae3.h"
8	10
9	11	#define HCLGE_CMDQ_TX_TIMEOUT 30000
	12	+#define HCLGE_CMDQ_CLEAR_WAIT_TIME 200
	13	+#define HCLGE_DESC_DATA_LEN 6
10	14
11	15	struct hclge_dev;
12	16	struct hclge_desc {
..	..	@@ -18,7 +22,7 @@
18	22	__le16 flag;
19	23	__le16 retval;
20	24	__le16 rsv;
21		- __le32 data[6];
	25	+ __le32 data[HCLGE_DESC_DATA_LEN];
22	26	};
23	27
24	28	struct hclge_cmq_ring {
..	..	@@ -41,6 +45,14 @@
41	45	HCLGE_CMD_NO_AUTH = 1,
42	46	HCLGE_CMD_NOT_SUPPORTED = 2,
43	47	HCLGE_CMD_QUEUE_FULL = 3,
	48	+ HCLGE_CMD_NEXT_ERR = 4,
	49	+ HCLGE_CMD_UNEXE_ERR = 5,
	50	+ HCLGE_CMD_PARA_ERR = 6,
	51	+ HCLGE_CMD_RESULT_ERR = 7,
	52	+ HCLGE_CMD_TIMEOUT = 8,
	53	+ HCLGE_CMD_HILINK_ERR = 9,
	54	+ HCLGE_CMD_QUEUE_ILLEGAL = 10,
	55	+ HCLGE_CMD_INVALID = 11,
44	56	};
45	57
46	58	enum hclge_cmd_status {
..	..	@@ -53,6 +65,7 @@
53	65	struct hclge_misc_vector {
54	66	u8 __iomem *addr;
55	67	int vector_irq;
	68	+ char name[HNAE3_INT_NAME_LEN];
56	69	};
57	70
58	71	struct hclge_cmq {
..	..	@@ -78,23 +91,45 @@
78	91	HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
79	92	HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
80	93	HCLGE_OPC_GET_CFG_PARAM = 0x0025,
	94	+ HCLGE_OPC_PF_RST_DONE = 0x0026,
	95	+ HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
81	96
82	97	HCLGE_OPC_STATS_64_BIT = 0x0030,
83	98	HCLGE_OPC_STATS_32_BIT = 0x0031,
84	99	HCLGE_OPC_STATS_MAC = 0x0032,
	100	+ HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
	101	+ HCLGE_OPC_STATS_MAC_ALL = 0x0034,
85	102
86	103	HCLGE_OPC_QUERY_REG_NUM = 0x0040,
87	104	HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
88	105	HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
	106	+ HCLGE_OPC_DFX_BD_NUM = 0x0043,
	107	+ HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
	108	+ HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
	109	+ HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
	110	+ HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
	111	+ HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
	112	+ HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
	113	+ HCLGE_OPC_DFX_NCSI_REG = 0x004A,
	114	+ HCLGE_OPC_DFX_RTC_REG = 0x004B,
	115	+ HCLGE_OPC_DFX_PPP_REG = 0x004C,
	116	+ HCLGE_OPC_DFX_RCB_REG = 0x004D,
	117	+ HCLGE_OPC_DFX_TQP_REG = 0x004E,
	118	+ HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
	119	+
	120	+ HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,
89	121
90	122	/* MAC command */
91	123	HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
92	124	HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
93		- HCLGE_OPC_QUERY_AN_RESULT = 0x0306,
94	125	HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
95	126	HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
96	127	HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
	128	+ HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
	129	+ HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
	130	+ HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
97	131	HCLGE_OPC_SERDES_LOOPBACK = 0x0315,
	132	+ HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
98	133
99	134	/* PFC/Pause commands */
100	135	HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
..	..	@@ -126,6 +161,16 @@
126	161	HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
127	162	HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
128	163	HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
	164	+ HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
	165	+ HCLGE_OPC_QSET_DFX_STS = 0x0844,
	166	+ HCLGE_OPC_PRI_DFX_STS = 0x0845,
	167	+ HCLGE_OPC_PG_DFX_STS = 0x0846,
	168	+ HCLGE_OPC_PORT_DFX_STS = 0x0847,
	169	+ HCLGE_OPC_SCH_NQ_CNT = 0x0848,
	170	+ HCLGE_OPC_SCH_RQ_CNT = 0x0849,
	171	+ HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
	172	+ HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
	173	+ HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
129	174
130	175	/* Packet buffer allocate commands */
131	176	HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
..	..	@@ -141,17 +186,22 @@
141	186	/* TQP commands */
142	187	HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
143	188	HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
144		- HCLGE_OPC_QUERY_TX_STATUS = 0x0B03,
	189	+ HCLGE_OPC_QUERY_TX_STATS = 0x0B03,
	190	+ HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
145	191	HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
146	192	HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
147		- HCLGE_OPC_QUERY_RX_STATUS = 0x0B13,
	193	+ HCLGE_OPC_QUERY_RX_STATS = 0x0B13,
148	194	HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
149	195	HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
150	196	HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
151	197	HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
152	198
	199	+ /* PPU commands */
	200	+ HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
	201	+
153	202	/* TSO command */
154	203	HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
	204	+ HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
155	205
156	206	/* RSS commands */
157	207	HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
..	..	@@ -175,20 +225,24 @@
175	225	HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
176	226	HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
177	227	HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
	228	+ HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
178	229	HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
179	230	HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
180		- HCLGE_OPC_MAC_VLAN_MASK_SET = 0x1012,
181	231
182		- /* Multicast linear table commands */
183		- HCLGE_OPC_MTA_MAC_MODE_CFG = 0x1020,
184		- HCLGE_OPC_MTA_MAC_FUNC_CFG = 0x1021,
185		- HCLGE_OPC_MTA_TBL_ITEM_CFG = 0x1022,
186		- HCLGE_OPC_MTA_TBL_ITEM_QUERY = 0x1023,
	232	+ /* MAC VLAN commands */
	233	+ HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
187	234
188	235	/* VLAN commands */
189	236	HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
190	237	HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
191	238	HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
	239	+
	240	+ /* Flow Director commands */
	241	+ HCLGE_OPC_FD_MODE_CTRL = 0x1200,
	242	+ HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
	243	+ HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
	244	+ HCLGE_OPC_FD_TCAM_OP = 0x1203,
	245	+ HCLGE_OPC_FD_AD_OP = 0x1204,
192	246
193	247	/* MDIO command */
194	248	HCLGE_OPC_MDIO_CONFIG = 0x1900,
..	..	@@ -196,7 +250,7 @@
196	250	/* QCN commands */
197	251	HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
198	252	HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
199		- HCLGE_OPC_QCN_SHAPPING_IR_CFG = 0x1A03,
	253	+ HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,
200	254	HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
201	255	HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
202	256	HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
..	..	@@ -208,6 +262,50 @@
208	262
209	263	/* Led command */
210	264	HCLGE_OPC_LED_STATUS_CFG = 0xB000,
	265	+
	266	+ /* clear hardware resource command */
	267	+ HCLGE_OPC_CLEAR_HW_RESOURCE = 0x700B,
	268	+
	269	+ /* NCL config command */
	270	+ HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
	271	+
	272	+ /* M7 stats command */
	273	+ HCLGE_OPC_M7_STATS_BD = 0x7012,
	274	+ HCLGE_OPC_M7_STATS_INFO = 0x7013,
	275	+ HCLGE_OPC_M7_COMPAT_CFG = 0x701A,
	276	+
	277	+ /* SFP command */
	278	+ HCLGE_OPC_GET_SFP_EEPROM = 0x7100,
	279	+ HCLGE_OPC_GET_SFP_EXIST = 0x7101,
	280	+ HCLGE_OPC_GET_SFP_INFO = 0x7104,
	281	+
	282	+ /* Error INT commands */
	283	+ HCLGE_MAC_COMMON_INT_EN = 0x030E,
	284	+ HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
	285	+ HCLGE_SSU_ECC_INT_CMD = 0x0989,
	286	+ HCLGE_SSU_COMMON_INT_CMD = 0x098C,
	287	+ HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
	288	+ HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
	289	+ HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
	290	+ HCLGE_COMMON_ECC_INT_CFG = 0x1505,
	291	+ HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
	292	+ HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
	293	+ HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
	294	+ HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
	295	+ HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
	296	+ HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
	297	+ HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
	298	+ HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
	299	+ HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
	300	+ HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
	301	+ HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
	302	+ HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
	303	+ HCLGE_IGU_COMMON_INT_EN = 0x1806,
	304	+ HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
	305	+ HCLGE_PPP_CMD0_INT_CMD = 0x2100,
	306	+ HCLGE_PPP_CMD1_INT_CMD = 0x2101,
	307	+ HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
	308	+ HCLGE_NCSI_INT_EN = 0x2401,
211	309	};
212	310
213	311	#define HCLGE_TQP_REG_OFFSET 0x80000
..	..	@@ -255,23 +353,40 @@
255	353	u8 rsv;
256	354	};
257	355
258		-#define HCLGE_TC_NUM 8
	356	+#define HCLGE_MAX_TC_NUM 8
259	357	#define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
260	358	#define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
261	359	struct hclge_tx_buff_alloc_cmd {
262		- __le16 tx_pkt_buff[HCLGE_TC_NUM];
	360	+ __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
263	361	u8 tx_buff_rsv[8];
264	362	};
265	363
266	364	struct hclge_rx_priv_buff_cmd {
267		- __le16 buf_num[HCLGE_TC_NUM];
	365	+ __le16 buf_num[HCLGE_MAX_TC_NUM];
268	366	__le16 shared_buf;
269	367	u8 rsv[6];
270	368	};
271	369
	370	+enum HCLGE_CAP_BITS {
	371	+ HCLGE_CAP_UDP_GSO_B,
	372	+ HCLGE_CAP_QB_B,
	373	+ HCLGE_CAP_FD_FORWARD_TC_B,
	374	+ HCLGE_CAP_PTP_B,
	375	+ HCLGE_CAP_INT_QL_B,
	376	+ HCLGE_CAP_SIMPLE_BD_B,
	377	+ HCLGE_CAP_TX_PUSH_B,
	378	+ HCLGE_CAP_PHY_IMP_B,
	379	+ HCLGE_CAP_TQP_TXRX_INDEP_B,
	380	+ HCLGE_CAP_HW_PAD_B,
	381	+ HCLGE_CAP_STASH_B,
	382	+};
	383	+
	384	+#define HCLGE_QUERY_CAP_LENGTH 3
272	385	struct hclge_query_version_cmd {
273	386	__le32 firmware;
274		- __le32 firmware_rsv[5];
	387	+ __le32 hardware;
	388	+ __le32 rsv;
	389	+ __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
275	390	};
276	391
277	392	#define HCLGE_RX_PRIV_EN_B 15
..	..	@@ -310,7 +425,6 @@
310	425	u32 enable; /* Enable TC private buffer or not */
311	426	};
312	427
313		-#define HCLGE_MAX_TC_NUM 8
314	428	struct hclge_shared_buf {
315	429	struct hclge_waterline self;
316	430	struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
..	..	@@ -343,8 +457,10 @@
343	457	#define HCLGE_PF_MAC_NUM_MASK 0x3
344	458	#define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
345	459	#define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
	460	+#define HCLGE_VF_RST_STATUS_CMD 4
	461	+
346	462	struct hclge_func_status_cmd {
347		- __le32 vf_rst_state[4];
	463	+ __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
348	464	u8 pf_state;
349	465	u8 mac_id;
350	466	u8 rsv1;
..	..	@@ -365,7 +481,9 @@
365	481	#define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
366	482	__le16 pf_intr_vector_number;
367	483	__le16 pf_own_fun_number;
368		- __le32 rsv[3];
	484	+ __le16 tx_buf_size;
	485	+ __le16 dv_buf_size;
	486	+ __le32 rsv[2];
369	487	};
370	488
371	489	#define HCLGE_CFG_OFFSET_S 0
..	..	@@ -395,11 +513,17 @@
395	513	#define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
396	514	#define HCLGE_CFG_SPEED_ABILITY_S 0
397	515	#define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
	516	+#define HCLGE_CFG_SPEED_ABILITY_EXT_S 10
	517	+#define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10)
	518	+#define HCLGE_CFG_UMV_TBL_SPACE_S 16
	519	+#define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
	520	+
	521	+#define HCLGE_CFG_CMD_CNT 4
398	522
399	523	struct hclge_cfg_param_cmd {
400	524	__le32 offset;
401	525	__le32 rsv;
402		- __le32 param[4];
	526	+ __le32 param[HCLGE_CFG_CMD_CNT];
403	527	};
404	528
405	529	#define HCLGE_MAC_MODE 0x0
..	..	@@ -503,6 +627,12 @@
503	627	u8 rsv[20];
504	628	};
505	629
	630	+struct hclge_pf_rst_sync_cmd {
	631	+#define HCLGE_PF_RST_ALL_VF_RDY_B 0
	632	+ u8 all_vf_ready;
	633	+ u8 rsv[23];
	634	+};
	635	+
506	636	#define HCLGE_CFG_SPEED_S 0
507	637	#define HCLGE_CFG_SPEED_M GENMASK(5, 0)
508	638
..	..	@@ -515,20 +645,6 @@
515	645	#define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
516	646	u8 mac_change_fec_en;
517	647	u8 rsv[22];
518		-};
519		-
520		-#define HCLGE_QUERY_SPEED_S 3
521		-#define HCLGE_QUERY_AN_B 0
522		-#define HCLGE_QUERY_DUPLEX_B 2
523		-
524		-#define HCLGE_QUERY_SPEED_M GENMASK(4, 0)
525		-#define HCLGE_QUERY_AN_M BIT(HCLGE_QUERY_AN_B)
526		-#define HCLGE_QUERY_DUPLEX_M BIT(HCLGE_QUERY_DUPLEX_B)
527		-
528		-struct hclge_query_an_speed_dup_cmd {
529		- u8 an_syn_dup_speed;
530		- u8 pause;
531		- u8 rsv[23];
532	648	};
533	649
534	650	#define HCLGE_RING_ID_MASK GENMASK(9, 0)
..	..	@@ -547,6 +663,32 @@
547	663	u8 rsv[20];
548	664	};
549	665
	666	+struct hclge_sfp_info_cmd {
	667	+ __le32 speed;
	668	+ u8 query_type; /* 0: sfp speed, 1: active speed */
	669	+ u8 active_fec;
	670	+ u8 autoneg; /* autoneg state */
	671	+ u8 autoneg_ability; /* whether support autoneg */
	672	+ __le32 speed_ability; /* speed ability for current media */
	673	+ __le32 module_type;
	674	+ u8 rsv[8];
	675	+};
	676	+
	677	+#define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
	678	+#define HCLGE_MAC_CFG_FEC_MODE_S 1
	679	+#define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
	680	+#define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
	681	+#define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1
	682	+
	683	+#define HCLGE_MAC_FEC_OFF 0
	684	+#define HCLGE_MAC_FEC_BASER 1
	685	+#define HCLGE_MAC_FEC_RS 2
	686	+struct hclge_config_fec_cmd {
	687	+ u8 fec_mode;
	688	+ u8 default_config;
	689	+ u8 rsv[22];
	690	+};
	691	+
550	692	#define HCLGE_MAC_UPLINK_PORT 0x100
551	693
552	694	struct hclge_config_max_frm_size_cmd {
..	..	@@ -560,6 +702,11 @@
560	702	HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */
561	703	HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
562	704	HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
	705	+};
	706	+
	707	+enum hclge_mac_vlan_add_resp_code {
	708	+ HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
	709	+ HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
563	710	};
564	711
565	712	#define HCLGE_MAC_VLAN_BIT0_EN_B 0
..	..	@@ -584,26 +731,23 @@
584	731	u8 rsv2[6];
585	732	};
586	733
587		-#define HCLGE_VLAN_MASK_EN_B 0
588		-struct hclge_mac_vlan_mask_entry_cmd {
589		- u8 rsv0[2];
590		- u8 vlan_mask;
591		- u8 rsv1;
592		- u8 mac_mask[6];
593		- u8 rsv2[14];
	734	+#define HCLGE_UMV_SPC_ALC_B 0
	735	+struct hclge_umv_spc_alc_cmd {
	736	+ u8 allocate;
	737	+ u8 rsv1[3];
	738	+ __le32 space_size;
	739	+ u8 rsv2[16];
594	740	};
595	741
596	742	#define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
597	743	#define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
598	744	#define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
599		-#define HCLGE_MAC_ETHERTYPE_LLDP 0x88cc
600	745
601	746	struct hclge_mac_mgr_tbl_entry_cmd {
602	747	u8 flags;
603	748	u8 resp_code;
604	749	__le16 vlan_tag;
605		- __le32 mac_addr_hi32;
606		- __le16 mac_addr_lo16;
	750	+ u8 mac_addr[ETH_ALEN];
607	751	__le16 rsv1;
608	752	__le16 ethter_type;
609	753	__le16 egress_port;
..	..	@@ -615,67 +759,27 @@
615	759	u8 rsv3[2];
616	760	};
617	761
618		-#define HCLGE_CFG_MTA_MAC_SEL_S 0
619		-#define HCLGE_CFG_MTA_MAC_SEL_M GENMASK(1, 0)
620		-#define HCLGE_CFG_MTA_MAC_EN_B 7
621		-struct hclge_mta_filter_mode_cmd {
622		- u8 dmac_sel_en; /* Use lowest 2 bit as sel_mode, bit 7 as enable */
623		- u8 rsv[23];
624		-};
625		-
626		-#define HCLGE_CFG_FUNC_MTA_ACCEPT_B 0
627		-struct hclge_cfg_func_mta_filter_cmd {
628		- u8 accept; /* Only used lowest 1 bit */
629		- u8 function_id;
630		- u8 rsv[22];
631		-};
632		-
633		-#define HCLGE_CFG_MTA_ITEM_ACCEPT_B 0
634		-#define HCLGE_CFG_MTA_ITEM_IDX_S 0
635		-#define HCLGE_CFG_MTA_ITEM_IDX_M GENMASK(11, 0)
636		-struct hclge_cfg_func_mta_item_cmd {
637		- __le16 item_idx; /* Only used lowest 12 bit */
638		- u8 accept; /* Only used lowest 1 bit */
639		- u8 rsv[21];
640		-};
641		-
642		-struct hclge_mac_vlan_add_cmd {
643		- __le16 flags;
644		- __le16 mac_addr_hi16;
645		- __le32 mac_addr_lo32;
646		- __le32 mac_addr_msk_hi32;
647		- __le16 mac_addr_msk_lo16;
648		- __le16 vlan_tag;
649		- __le16 ingress_port;
650		- __le16 egress_port;
651		- u8 rsv[4];
652		-};
653		-
654		-#define HNS3_MAC_VLAN_CFG_FLAG_BIT 0
655		-struct hclge_mac_vlan_remove_cmd {
656		- __le16 flags;
657		- __le16 mac_addr_hi16;
658		- __le32 mac_addr_lo32;
659		- __le32 mac_addr_msk_hi32;
660		- __le16 mac_addr_msk_lo16;
661		- __le16 vlan_tag;
662		- __le16 ingress_port;
663		- __le16 egress_port;
664		- u8 rsv[4];
665		-};
666		-
667	762	struct hclge_vlan_filter_ctrl_cmd {
668	763	u8 vlan_type;
669	764	u8 vlan_fe;
670		- u8 rsv[22];
	765	+ u8 rsv1[2];
	766	+ u8 vf_id;
	767	+ u8 rsv2[19];
671	768	};
	769	+
	770	+#define HCLGE_VLAN_ID_OFFSET_STEP 160
	771	+#define HCLGE_VLAN_BYTE_SIZE 8
	772	+#define HCLGE_VLAN_OFFSET_BITMAP \
	773	+ (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
672	774
673	775	struct hclge_vlan_filter_pf_cfg_cmd {
674	776	u8 vlan_offset;
675	777	u8 vlan_cfg;
676	778	u8 rsv[2];
677		- u8 vlan_offset_bitmap[20];
	779	+ u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
678	780	};
	781	+
	782	+#define HCLGE_MAX_VF_BYTES 16
679	783
680	784	struct hclge_vlan_filter_vf_cfg_cmd {
681	785	__le16 vlan_id;
..	..	@@ -683,7 +787,32 @@
683	787	u8 rsv;
684	788	u8 vlan_cfg;
685	789	u8 rsv1[3];
686		- u8 vf_bitmap[16];
	790	+ u8 vf_bitmap[HCLGE_MAX_VF_BYTES];
	791	+};
	792	+
	793	+#define HCLGE_SWITCH_ANTI_SPOOF_B 0U
	794	+#define HCLGE_SWITCH_ALW_LPBK_B 1U
	795	+#define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U
	796	+#define HCLGE_SWITCH_ALW_DST_OVRD_B 3U
	797	+#define HCLGE_SWITCH_NO_MASK 0x0
	798	+#define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE
	799	+#define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD
	800	+#define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB
	801	+#define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7
	802	+
	803	+struct hclge_mac_vlan_switch_cmd {
	804	+ u8 roce_sel;
	805	+ u8 rsv1[3];
	806	+ __le32 func_id;
	807	+ u8 switch_param;
	808	+ u8 rsv2[3];
	809	+ u8 param_mask;
	810	+ u8 rsv3[11];
	811	+};
	812	+
	813	+enum hclge_mac_vlan_cfg_sel {
	814	+ HCLGE_MAC_VLAN_NIC_SEL = 0,
	815	+ HCLGE_MAC_VLAN_ROCE_SEL,
687	816	};
688	817
689	818	#define HCLGE_ACCEPT_TAG1_B 0
..	..	@@ -693,6 +822,7 @@
693	822	#define HCLGE_CFG_NIC_ROCE_SEL_B 4
694	823	#define HCLGE_ACCEPT_TAG2_B 5
695	824	#define HCLGE_ACCEPT_UNTAG2_B 6
	825	+#define HCLGE_VF_NUM_PER_BYTE 8
696	826
697	827	struct hclge_vport_vtag_tx_cfg_cmd {
698	828	u8 vport_vlan_cfg;
..	..	@@ -700,7 +830,7 @@
700	830	u8 rsv1[2];
701	831	__le16 def_vlan_tag1;
702	832	__le16 def_vlan_tag2;
703		- u8 vf_bitmap[8];
	833	+ u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
704	834	u8 rsv2[8];
705	835	};
706	836
..	..	@@ -712,7 +842,7 @@
712	842	u8 vport_vlan_cfg;
713	843	u8 vf_offset;
714	844	u8 rsv1[6];
715		- u8 vf_bitmap[8];
	845	+ u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
716	846	u8 rsv2[8];
717	847	};
718	848
..	..	@@ -746,6 +876,24 @@
746	876	u8 rsv[14];
747	877	};
748	878
	879	+#pragma pack(1)
	880	+struct hclge_mac_ethertype_idx_rd_cmd {
	881	+ u8 flags;
	882	+ u8 resp_code;
	883	+ __le16 vlan_tag;
	884	+ u8 mac_addr[ETH_ALEN];
	885	+ __le16 index;
	886	+ __le16 ethter_type;
	887	+ __le16 egress_port;
	888	+ __le16 egress_queue;
	889	+ __le16 rev0;
	890	+ u8 i_port_bitmap;
	891	+ u8 i_port_direction;
	892	+ u8 rev1[2];
	893	+};
	894	+
	895	+#pragma pack()
	896	+
749	897	#define HCLGE_TSO_MSS_MIN_S 0
750	898	#define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
751	899
..	..	@@ -756,6 +904,12 @@
756	904	__le16 tso_mss_min;
757	905	__le16 tso_mss_max;
758	906	u8 rsv[20];
	907	+};
	908	+
	909	+#define HCLGE_GRO_EN_B 0
	910	+struct hclge_cfg_gro_status_cmd {
	911	+ u8 gro_en;
	912	+ u8 rsv[23];
759	913	};
760	914
761	915	#define HCLGE_TSO_MSS_MIN 256
..	..	@@ -777,7 +931,15 @@
777	931	u8 rsv[22];
778	932	};
779	933
	934	+#define HCLGE_PF_RESET_DONE_BIT BIT(0)
	935	+
	936	+struct hclge_pf_rst_done_cmd {
	937	+ u8 pf_rst_done;
	938	+ u8 rsv[23];
	939	+};
	940	+
780	941	#define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
	942	+#define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
781	943	#define HCLGE_CMD_SERDES_DONE_B BIT(0)
782	944	#define HCLGE_CMD_SERDES_SUCCESS_B BIT(1)
783	945	struct hclge_serdes_lb_cmd {
..	..	@@ -791,6 +953,7 @@
791	953	#define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
792	954	#define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
793	955	#define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
	956	+#define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
794	957
795	958	#define HCLGE_TYPE_CRQ 0
796	959	#define HCLGE_TYPE_CSQ 1
..	..	@@ -804,8 +967,11 @@
804	967	#define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
805	968	#define HCLGE_NIC_CRQ_TAIL_REG 0x27024
806	969	#define HCLGE_NIC_CRQ_HEAD_REG 0x27028
807		-#define HCLGE_NIC_CMQ_EN_B 16
808		-#define HCLGE_NIC_CMQ_ENABLE BIT(HCLGE_NIC_CMQ_EN_B)
	970	+
	971	+/* this bit indicates that the driver is ready for hardware reset */
	972	+#define HCLGE_NIC_SW_RST_RDY_B 16
	973	+#define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B)
	974	+
809	975	#define HCLGE_NIC_CMQ_DESC_NUM 1024
810	976	#define HCLGE_NIC_CMQ_DESC_NUM_S 3
811	977
..	..	@@ -816,6 +982,129 @@
816	982	u8 rsv1[3];
817	983	u8 locate_led_config;
818	984	u8 rsv2[20];
	985	+};
	986	+
	987	+struct hclge_get_fd_mode_cmd {
	988	+ u8 mode;
	989	+ u8 enable;
	990	+ u8 rsv[22];
	991	+};
	992	+
	993	+struct hclge_get_fd_allocation_cmd {
	994	+ __le32 stage1_entry_num;
	995	+ __le32 stage2_entry_num;
	996	+ __le16 stage1_counter_num;
	997	+ __le16 stage2_counter_num;
	998	+ u8 rsv[12];
	999	+};
	1000	+
	1001	+struct hclge_set_fd_key_config_cmd {
	1002	+ u8 stage;
	1003	+ u8 key_select;
	1004	+ u8 inner_sipv6_word_en;
	1005	+ u8 inner_dipv6_word_en;
	1006	+ u8 outer_sipv6_word_en;
	1007	+ u8 outer_dipv6_word_en;
	1008	+ u8 rsv1[2];
	1009	+ __le32 tuple_mask;
	1010	+ __le32 meta_data_mask;
	1011	+ u8 rsv2[8];
	1012	+};
	1013	+
	1014	+#define HCLGE_FD_EPORT_SW_EN_B 0
	1015	+struct hclge_fd_tcam_config_1_cmd {
	1016	+ u8 stage;
	1017	+ u8 xy_sel;
	1018	+ u8 port_info;
	1019	+ u8 rsv1[1];
	1020	+ __le32 index;
	1021	+ u8 entry_vld;
	1022	+ u8 rsv2[7];
	1023	+ u8 tcam_data[8];
	1024	+};
	1025	+
	1026	+struct hclge_fd_tcam_config_2_cmd {
	1027	+ u8 tcam_data[24];
	1028	+};
	1029	+
	1030	+struct hclge_fd_tcam_config_3_cmd {
	1031	+ u8 tcam_data[20];
	1032	+ u8 rsv[4];
	1033	+};
	1034	+
	1035	+#define HCLGE_FD_AD_DROP_B 0
	1036	+#define HCLGE_FD_AD_DIRECT_QID_B 1
	1037	+#define HCLGE_FD_AD_QID_S 2
	1038	+#define HCLGE_FD_AD_QID_M GENMASK(11, 2)
	1039	+#define HCLGE_FD_AD_USE_COUNTER_B 12
	1040	+#define HCLGE_FD_AD_COUNTER_NUM_S 13
	1041	+#define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
	1042	+#define HCLGE_FD_AD_NXT_STEP_B 20
	1043	+#define HCLGE_FD_AD_NXT_KEY_S 21
	1044	+#define HCLGE_FD_AD_NXT_KEY_M GENMASK(25, 21)
	1045	+#define HCLGE_FD_AD_WR_RULE_ID_B 0
	1046	+#define HCLGE_FD_AD_RULE_ID_S 1
	1047	+#define HCLGE_FD_AD_RULE_ID_M GENMASK(12, 1)
	1048	+
	1049	+struct hclge_fd_ad_config_cmd {
	1050	+ u8 stage;
	1051	+ u8 rsv1[3];
	1052	+ __le32 index;
	1053	+ __le64 ad_data;
	1054	+ u8 rsv2[8];
	1055	+};
	1056	+
	1057	+struct hclge_get_m7_bd_cmd {
	1058	+ __le32 bd_num;
	1059	+ u8 rsv[20];
	1060	+};
	1061	+
	1062	+struct hclge_query_ppu_pf_other_int_dfx_cmd {
	1063	+ __le16 over_8bd_no_fe_qid;
	1064	+ __le16 over_8bd_no_fe_vf_id;
	1065	+ __le16 tso_mss_cmp_min_err_qid;
	1066	+ __le16 tso_mss_cmp_min_err_vf_id;
	1067	+ __le16 tso_mss_cmp_max_err_qid;
	1068	+ __le16 tso_mss_cmp_max_err_vf_id;
	1069	+ __le16 tx_rd_fbd_poison_qid;
	1070	+ __le16 tx_rd_fbd_poison_vf_id;
	1071	+ __le16 rx_rd_fbd_poison_qid;
	1072	+ __le16 rx_rd_fbd_poison_vf_id;
	1073	+ u8 rsv[4];
	1074	+};
	1075	+
	1076	+#define HCLGE_LINK_EVENT_REPORT_EN_B 0
	1077	+#define HCLGE_NCSI_ERROR_REPORT_EN_B 1
	1078	+struct hclge_firmware_compat_cmd {
	1079	+ __le32 compat;
	1080	+ u8 rsv[20];
	1081	+};
	1082	+
	1083	+#define HCLGE_SFP_INFO_CMD_NUM 6
	1084	+#define HCLGE_SFP_INFO_BD0_LEN 20
	1085	+#define HCLGE_SFP_INFO_BDX_LEN 24
	1086	+#define HCLGE_SFP_INFO_MAX_LEN \
	1087	+ (HCLGE_SFP_INFO_BD0_LEN + \
	1088	+ (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
	1089	+
	1090	+struct hclge_sfp_info_bd0_cmd {
	1091	+ __le16 offset;
	1092	+ __le16 read_len;
	1093	+ u8 data[HCLGE_SFP_INFO_BD0_LEN];
	1094	+};
	1095	+
	1096	+#define HCLGE_QUERY_DEV_SPECS_BD_NUM 4
	1097	+
	1098	+struct hclge_dev_specs_0_cmd {
	1099	+ __le32 rsv0;
	1100	+ __le32 mac_entry_num;
	1101	+ __le32 mng_entry_num;
	1102	+ __le16 rss_ind_tbl_size;
	1103	+ __le16 rss_key_size;
	1104	+ __le16 int_ql_max;
	1105	+ u8 max_non_tso_bd_num;
	1106	+ u8 rsv1;
	1107	+ __le32 max_tm_rate;
819	1108	};
820	1109
821	1110	int hclge_cmd_init(struct hclge_dev *hdev);
..	..	@@ -845,14 +1134,11 @@
845	1134	enum hclge_opcode_type opcode, bool is_read);
846	1135	void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
847	1136
848		-int hclge_cmd_set_promisc_mode(struct hclge_dev *hdev,
849		- struct hclge_promisc_param *param);
850		-
851	1137	enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
852	1138	struct hclge_desc *desc);
853	1139	enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
854	1140	struct hclge_desc *desc);
855	1141
856		-void hclge_destroy_cmd_queue(struct hclge_hw *hw);
	1142	+void hclge_cmd_uninit(struct hclge_dev *hdev);
857	1143	int hclge_cmd_queue_init(struct hclge_dev *hdev);
858	1144	#endif