add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/drivers/crypto/rockchip/rk_crypto_v2_ahash.c
..
..
@@ -51,13 +51,17 @@
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 	CRYPTO_WRITE(rk_dev, CRYPTO_RST_CTL, tmp | tmp_mask);
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 	/* This is usually done in 20 clock cycles */
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-	ret = readl_poll_timeout_atomic(rk_dev->reg + CRYPTO_RST_CTL,
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-					tmp, !tmp, 0, pool_timeout_us);
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+	ret = read_poll_timeout_atomic(CRYPTO_READ, tmp, !tmp, 0, pool_timeout_us,
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+				       false, rk_dev, CRYPTO_RST_CTL);
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 	if (ret)
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 		dev_err(rk_dev->dev, "cipher reset pool timeout %ums.",
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 			pool_timeout_us);
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 	CRYPTO_WRITE(rk_dev, CRYPTO_HASH_CTL, 0xffff0000);
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+
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+	/* clear dma int status */
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+	tmp = CRYPTO_READ(rk_dev, CRYPTO_DMA_INT_ST);
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+	CRYPTO_WRITE(rk_dev, CRYPTO_DMA_INT_ST, tmp);
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 }
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 static int rk_crypto_irq_handle(int irq, void *dev_id)
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@@ -285,11 +289,11 @@
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 	int ret = 0;
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 	u32 reg_ctrl = 0;
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-	ret = readl_poll_timeout_atomic(rk_dev->reg + CRYPTO_HASH_VALID,
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-					reg_ctrl,
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-					reg_ctrl & CRYPTO_HASH_IS_VALID,
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-					RK_POLL_PERIOD_US,
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-					RK_POLL_TIMEOUT_US);
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+	ret = read_poll_timeout_atomic(CRYPTO_READ, reg_ctrl,
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+				       reg_ctrl & CRYPTO_HASH_IS_VALID,
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+				       RK_POLL_PERIOD_US,
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+				       RK_POLL_TIMEOUT_US, false,
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+				       rk_dev, CRYPTO_HASH_VALID);
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 	if (ret)
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 		goto exit;
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