forked from ~ljy/RK356X_SDK_RELEASE

hc
2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2
kernel/drivers/crypto/caam/intern.h
....@@ -4,11 +4,14 @@
44 * Private/internal definitions between modules
55 *
66 * Copyright 2008-2011 Freescale Semiconductor, Inc.
7
- *
7
+ * Copyright 2019 NXP
88 */
99
1010 #ifndef INTERN_H
1111 #define INTERN_H
12
+
13
+#include "ctrl.h"
14
+#include <crypto/engine.h>
1215
1316 /* Currently comes from Kconfig param as a ^2 (driver-required) */
1417 #define JOBR_DEPTH (1 << CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE)
....@@ -44,37 +47,36 @@
4447 struct caam_job_ring __iomem *rregs; /* JobR's register space */
4548 struct tasklet_struct irqtask;
4649 int irq; /* One per queue */
50
+ bool hwrng;
4751
4852 /* Number of scatterlist crypt transforms active on the JobR */
4953 atomic_t tfm_count ____cacheline_aligned;
5054
5155 /* Job ring info */
52
- int ringsize; /* Size of rings (assume input = output) */
5356 struct caam_jrentry_info *entinfo; /* Alloc'ed 1 per ring entry */
5457 spinlock_t inplock ____cacheline_aligned; /* Input ring index lock */
55
- int inp_ring_write_index; /* Input index "tail" */
58
+ u32 inpring_avail; /* Number of free entries in input ring */
5659 int head; /* entinfo (s/w ring) head index */
57
- dma_addr_t *inpring; /* Base of input ring, alloc DMA-safe */
58
- spinlock_t outlock ____cacheline_aligned; /* Output ring index lock */
60
+ void *inpring; /* Base of input ring, alloc
61
+ * DMA-safe */
5962 int out_ring_read_index; /* Output index "tail" */
6063 int tail; /* entinfo (s/w ring) tail index */
61
- struct jr_outentry *outring; /* Base of output ring, DMA-safe */
64
+ void *outring; /* Base of output ring, DMA-safe */
65
+ struct crypto_engine *engine;
6266 };
6367
6468 /*
6569 * Driver-private storage for a single CAAM block instance
6670 */
6771 struct caam_drv_private {
68
-#ifdef CONFIG_CAAM_QI
69
- struct device *qidev;
70
-#endif
71
-
7272 /* Physical-presence section */
7373 struct caam_ctrl __iomem *ctrl; /* controller region */
7474 struct caam_deco __iomem *deco; /* DECO/CCB views */
7575 struct caam_assurance __iomem *assure;
7676 struct caam_queue_if __iomem *qi; /* QI control region */
7777 struct caam_job_ring __iomem *jr[4]; /* JobR's register space */
78
+
79
+ struct iommu_domain *domain;
7880
7981 /*
8082 * Detected geometry block. Filled in from device tree if powerpc,
....@@ -93,41 +95,122 @@
9395 Handles of the RNG4 block are initialized
9496 by this driver */
9597
96
- struct clk *caam_ipg;
97
- struct clk *caam_mem;
98
- struct clk *caam_aclk;
99
- struct clk *caam_emi_slow;
100
-
98
+ struct clk_bulk_data *clks;
99
+ int num_clks;
101100 /*
102101 * debugfs entries for developer view into driver/device
103102 * variables at runtime.
104103 */
105104 #ifdef CONFIG_DEBUG_FS
106
- struct dentry *dfs_root;
107105 struct dentry *ctl; /* controller dir */
108106 struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap;
109
- struct dentry *ctl_kek, *ctl_tkek, *ctl_tdsk;
110107 #endif
111108 };
112109
113
-void caam_jr_algapi_init(struct device *dev);
114
-void caam_jr_algapi_remove(struct device *dev);
110
+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API
115111
116
-#ifdef CONFIG_DEBUG_FS
117
-static int caam_debugfs_u64_get(void *data, u64 *val)
112
+int caam_algapi_init(struct device *dev);
113
+void caam_algapi_exit(void);
114
+
115
+#else
116
+
117
+static inline int caam_algapi_init(struct device *dev)
118118 {
119
- *val = caam64_to_cpu(*(u64 *)data);
120119 return 0;
121120 }
122121
123
-static int caam_debugfs_u32_get(void *data, u64 *val)
122
+static inline void caam_algapi_exit(void)
124123 {
125
- *val = caam32_to_cpu(*(u32 *)data);
124
+}
125
+
126
+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API */
127
+
128
+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API
129
+
130
+int caam_algapi_hash_init(struct device *dev);
131
+void caam_algapi_hash_exit(void);
132
+
133
+#else
134
+
135
+static inline int caam_algapi_hash_init(struct device *dev)
136
+{
126137 return 0;
127138 }
128139
129
-DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n");
130
-DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n");
131
-#endif
140
+static inline void caam_algapi_hash_exit(void)
141
+{
142
+}
143
+
144
+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API */
145
+
146
+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API
147
+
148
+int caam_pkc_init(struct device *dev);
149
+void caam_pkc_exit(void);
150
+
151
+#else
152
+
153
+static inline int caam_pkc_init(struct device *dev)
154
+{
155
+ return 0;
156
+}
157
+
158
+static inline void caam_pkc_exit(void)
159
+{
160
+}
161
+
162
+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API */
163
+
164
+#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API
165
+
166
+int caam_rng_init(struct device *dev);
167
+void caam_rng_exit(struct device *dev);
168
+
169
+#else
170
+
171
+static inline int caam_rng_init(struct device *dev)
172
+{
173
+ return 0;
174
+}
175
+
176
+static inline void caam_rng_exit(struct device *dev) {}
177
+
178
+#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API */
179
+
180
+#ifdef CONFIG_CAAM_QI
181
+
182
+int caam_qi_algapi_init(struct device *dev);
183
+void caam_qi_algapi_exit(void);
184
+
185
+#else
186
+
187
+static inline int caam_qi_algapi_init(struct device *dev)
188
+{
189
+ return 0;
190
+}
191
+
192
+static inline void caam_qi_algapi_exit(void)
193
+{
194
+}
195
+
196
+#endif /* CONFIG_CAAM_QI */
197
+
198
+static inline u64 caam_get_dma_mask(struct device *dev)
199
+{
200
+ struct device_node *nprop = dev->of_node;
201
+
202
+ if (caam_ptr_sz != sizeof(u64))
203
+ return DMA_BIT_MASK(32);
204
+
205
+ if (caam_dpaa2)
206
+ return DMA_BIT_MASK(49);
207
+
208
+ if (of_device_is_compatible(nprop, "fsl,sec-v5.0-job-ring") ||
209
+ of_device_is_compatible(nprop, "fsl,sec-v5.0"))
210
+ return DMA_BIT_MASK(40);
211
+
212
+ return DMA_BIT_MASK(36);
213
+}
214
+
132215
133216 #endif /* INTERN_H */