add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/x86/kernel/ldt.c
..
..
@@ -8,7 +8,7 @@
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  *
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  * Lock order:
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  *	contex.ldt_usr_sem
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- *	  mmap_sem
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+ *	  mmap_lock
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  *	    context.lock
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  */
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14
 
..
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@@ -27,7 +27,91 @@
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 #include <asm/tlb.h>
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 #include <asm/desc.h>
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 #include <asm/mmu_context.h>
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-#include <asm/syscalls.h>
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+#include <asm/pgtable_areas.h>
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+
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+#include <xen/xen.h>
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+
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+/* This is a multiple of PAGE_SIZE. */
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+#define LDT_SLOT_STRIDE (LDT_ENTRIES * LDT_ENTRY_SIZE)
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+
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+static inline void *ldt_slot_va(int slot)
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+{
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+	return (void *)(LDT_BASE_ADDR + LDT_SLOT_STRIDE * slot);
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+}
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+
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+void load_mm_ldt(struct mm_struct *mm)
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+{
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+	struct ldt_struct *ldt;
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+
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+	/* READ_ONCE synchronizes with smp_store_release */
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+	ldt = READ_ONCE(mm->context.ldt);
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+
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+	/*
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+	 * Any change to mm->context.ldt is followed by an IPI to all
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+	 * CPUs with the mm active.  The LDT will not be freed until
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+	 * after the IPI is handled by all such CPUs.  This means that,
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+	 * if the ldt_struct changes before we return, the values we see
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+	 * will be safe, and the new values will be loaded before we run
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+	 * any user code.
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+	 *
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+	 * NB: don't try to convert this to use RCU without extreme care.
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+	 * We would still need IRQs off, because we don't want to change
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+	 * the local LDT after an IPI loaded a newer value than the one
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+	 * that we can see.
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+	 */
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+
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+	if (unlikely(ldt)) {
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+		if (static_cpu_has(X86_FEATURE_PTI)) {
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+			if (WARN_ON_ONCE((unsigned long)ldt->slot > 1)) {
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+				/*
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+				 * Whoops -- either the new LDT isn't mapped
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+				 * (if slot == -1) or is mapped into a bogus
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+				 * slot (if slot > 1).
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+				 */
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+				clear_LDT();
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+				return;
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+			}
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+
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+			/*
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+			 * If page table isolation is enabled, ldt->entries
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+			 * will not be mapped in the userspace pagetables.
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+			 * Tell the CPU to access the LDT through the alias
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+			 * at ldt_slot_va(ldt->slot).
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+			 */
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+			set_ldt(ldt_slot_va(ldt->slot), ldt->nr_entries);
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+		} else {
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+			set_ldt(ldt->entries, ldt->nr_entries);
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+		}
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+	} else {
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+		clear_LDT();
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+	}
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+}
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+
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+void switch_ldt(struct mm_struct *prev, struct mm_struct *next)
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+{
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+	/*
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+	 * Load the LDT if either the old or new mm had an LDT.
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+	 *
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+	 * An mm will never go from having an LDT to not having an LDT.  Two
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+	 * mms never share an LDT, so we don't gain anything by checking to
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+	 * see whether the LDT changed.  There's also no guarantee that
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+	 * prev->context.ldt actually matches LDTR, but, if LDTR is non-NULL,
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+	 * then prev->context.ldt will also be non-NULL.
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+	 *
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+	 * If we really cared, we could optimize the case where prev == next
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+	 * and we're exiting lazy mode.  Most of the time, if this happens,
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+	 * we don't actually need to reload LDTR, but modify_ldt() is mostly
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+	 * used by legacy code and emulators where we don't need this level of
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+	 * performance.
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+	 *
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+	 * This uses | instead of || because it generates better code.
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+	 */
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+	if (unlikely((unsigned long)prev->context.ldt |
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+		     (unsigned long)next->context.ldt))
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+		load_mm_ldt(next);
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+
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+	DEBUG_LOCKS_WARN_ON(preemptible());
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+}
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115
 
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 static void refresh_ldt_segments(void)
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 {
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@@ -113,7 +197,7 @@
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 		 * tables.
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 		 */
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 		WARN_ON(!had_kernel_mapping);
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-		if (static_cpu_has(X86_FEATURE_PTI))
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+		if (boot_cpu_has(X86_FEATURE_PTI))
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 			WARN_ON(!had_user_mapping);
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 	} else {
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 		/*
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@@ -121,7 +205,7 @@
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 		 * Sync the pgd to the usermode tables.
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 		 */
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 		WARN_ON(had_kernel_mapping);
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-		if (static_cpu_has(X86_FEATURE_PTI))
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+		if (boot_cpu_has(X86_FEATURE_PTI))
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 			WARN_ON(had_user_mapping);
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 	}
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 }
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@@ -156,7 +240,7 @@
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 	k_pmd = pgd_to_pmd_walk(k_pgd, LDT_BASE_ADDR);
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 	u_pmd = pgd_to_pmd_walk(u_pgd, LDT_BASE_ADDR);
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242
 
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-	if (static_cpu_has(X86_FEATURE_PTI) && !mm->context.ldt)
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+	if (boot_cpu_has(X86_FEATURE_PTI) && !mm->context.ldt)
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 		set_pmd(u_pmd, *k_pmd);
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 }
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@@ -181,7 +265,7 @@
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 {
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 	pgd_t *pgd = pgd_offset(mm, LDT_BASE_ADDR);
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267
 
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-	if (static_cpu_has(X86_FEATURE_PTI) && !mm->context.ldt)
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+	if (boot_cpu_has(X86_FEATURE_PTI) && !mm->context.ldt)
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 		set_pgd(kernel_to_user_pgdp(pgd), *pgd);
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 }
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271
 
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@@ -208,7 +292,7 @@
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 	spinlock_t *ptl;
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 	int i, nr_pages;
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294
 
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-	if (!static_cpu_has(X86_FEATURE_PTI))
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+	if (!boot_cpu_has(X86_FEATURE_PTI))
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 		return 0;
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 	/*
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@@ -271,7 +355,7 @@
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 		return;
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 	/* LDT map/unmap is only required for PTI */
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-	if (!static_cpu_has(X86_FEATURE_PTI))
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+	if (!boot_cpu_has(X86_FEATURE_PTI))
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 		return;
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 	nr_pages = DIV_ROUND_UP(ldt->nr_entries * LDT_ENTRY_SIZE, PAGE_SIZE);
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@@ -288,7 +372,7 @@
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 	}
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 	va = (unsigned long)ldt_slot_va(ldt->slot);
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-	flush_tlb_mm_range(mm, va, va + nr_pages * PAGE_SIZE, 0);
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+	flush_tlb_mm_range(mm, va, va + nr_pages * PAGE_SIZE, PAGE_SHIFT, false);
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 }
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 #else /* !CONFIG_PAGE_TABLE_ISOLATION */
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@@ -311,7 +395,7 @@
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 	unsigned long start = LDT_BASE_ADDR;
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 	unsigned long end = LDT_END_ADDR;
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-	if (!static_cpu_has(X86_FEATURE_PTI))
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+	if (!boot_cpu_has(X86_FEATURE_PTI))
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 		return;
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 	tlb_gather_mmu(&tlb, mm, start, end);
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@@ -461,6 +545,28 @@
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 	return bytecount;
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 }
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+static bool allow_16bit_segments(void)
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+{
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+	if (!IS_ENABLED(CONFIG_X86_16BIT))
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+		return false;
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+
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+#ifdef CONFIG_XEN_PV
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+	/*
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+	 * Xen PV does not implement ESPFIX64, which means that 16-bit
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+	 * segments will not work correctly.  Until either Xen PV implements
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+	 * ESPFIX64 and can signal this fact to the guest or unless someone
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+	 * provides compelling evidence that allowing broken 16-bit segments
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+	 * is worthwhile, disallow 16-bit segments under Xen PV.
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+	 */
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+	if (xen_pv_domain()) {
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+		pr_info_once("Warning: 16-bit segments do not work correctly in a Xen PV guest\n");
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+		return false;
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+	}
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+#endif
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+
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+	return true;
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+}
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+
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 static int write_ldt(void __user *ptr, unsigned long bytecount, int oldmode)
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 {
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 	struct mm_struct *mm = current->mm;
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@@ -492,7 +598,7 @@
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 		/* The user wants to clear the entry. */
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 		memset(&ldt, 0, sizeof(ldt));
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 	} else {
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-		if (!IS_ENABLED(CONFIG_X86_16BIT) && !ldt_info.seg_32bit) {
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+		if (!ldt_info.seg_32bit && !allow_16bit_segments()) {
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 			error = -EINVAL;
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 			goto out;
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 		}