add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/x86/kernel/cpu/cacheinfo.c
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@@ -17,6 +17,7 @@
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 #include <linux/pci.h>
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 #include <asm/cpufeature.h>
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+#include <asm/cacheinfo.h>
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 #include <asm/amd_nb.h>
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 #include <asm/smp.h>
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@@ -247,6 +248,7 @@
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 	switch (leaf) {
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 	case 1:
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 		l1 = &l1i;
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+		fallthrough;
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 	case 0:
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 		if (!l1->val)
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 			return;
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@@ -602,6 +604,10 @@
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 		else
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 			amd_cpuid4(index, &eax, &ebx, &ecx);
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 		amd_init_l3_cache(this_leaf, index);
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+	} else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
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+		cpuid_count(0x8000001d, index, &eax.full,
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+			    &ebx.full, &ecx.full, &edx);
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+		amd_init_l3_cache(this_leaf, index);
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 	} else {
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 		cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
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 	}
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@@ -625,7 +631,8 @@
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 	union _cpuid4_leaf_eax	cache_eax;
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 	int 			i = -1;
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-	if (c->x86_vendor == X86_VENDOR_AMD)
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+	if (c->x86_vendor == X86_VENDOR_AMD ||
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+	    c->x86_vendor == X86_VENDOR_HYGON)
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 		op = 0x8000001d;
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 	else
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 		op = 4;
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@@ -639,7 +646,7 @@
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 	return i;
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 }
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-void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu, u8 node_id)
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+void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, int cpu)
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 {
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 	/*
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 	 * We may have multiple LLCs if L3 caches exist, so check if we
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@@ -650,7 +657,7 @@
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 	if (c->x86 < 0x17) {
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 		/* LLC is at the node level. */
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-		per_cpu(cpu_llc_id, cpu) = node_id;
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+		per_cpu(cpu_llc_id, cpu) = c->cpu_die_id;
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 	} else if (c->x86 == 0x17 && c->x86_model <= 0x1F) {
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 		/*
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 		 * LLC is at the core complex level.
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@@ -677,6 +684,22 @@
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 	}
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 }
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+void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c, int cpu)
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+{
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+	/*
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+	 * We may have multiple LLCs if L3 caches exist, so check if we
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+	 * have an L3 cache by looking at the L3 cache CPUID leaf.
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+	 */
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+	if (!cpuid_edx(0x80000006))
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+		return;
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+
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+	/*
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+	 * LLC is at the core complex level.
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+	 * Core complex ID is ApicId[3] for these processors.
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+	 */
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+	per_cpu(cpu_llc_id, cpu) = c->apicid >> 3;
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+}
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+
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 void init_amd_cacheinfo(struct cpuinfo_x86 *c)
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 {
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@@ -688,6 +711,11 @@
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 		else
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 			num_cache_leaves = 3;
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 	}
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+}
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+
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+void init_hygon_cacheinfo(struct cpuinfo_x86 *c)
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+{
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+	num_cache_leaves = find_num_cache_leaves(c);
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 }
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 void init_intel_cacheinfo(struct cpuinfo_x86 *c)
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@@ -912,7 +940,8 @@
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 	int index_msb, i;
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 	struct cpuinfo_x86 *c = &cpu_data(cpu);
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-	if (c->x86_vendor == X86_VENDOR_AMD) {
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+	if (c->x86_vendor == X86_VENDOR_AMD ||
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+	    c->x86_vendor == X86_VENDOR_HYGON) {
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 		if (__cache_amd_cpumap_setup(cpu, index, base))
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 			return;
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 	}