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2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 
 kernel/arch/arm64/include/asm/kvm_arm.h
....@@ -1,18 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2012,2013 - ARM Ltd
34  * Author: Marc Zyngier <marc.zyngier@arm.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
13
- *
14
- * You should have received a copy of the GNU General Public License
15
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
165  */
176 
187 #ifndef __ARM64_KVM_ARM_H__
....@@ -23,6 +12,7 @@
2312 #include <asm/types.h>
2413 
2514 /* Hyp Configuration Register (HCR) bits */
15
+#define HCR_ATA		(UL(1) << 56)
2616 #define HCR_FWB		(UL(1) << 46)
2717 #define HCR_API		(UL(1) << 41)
2818 #define HCR_APK		(UL(1) << 40)
....@@ -72,13 +62,12 @@
7262  * RW:		64bit by default, can be overridden for 32bit VMs
7363  * TAC:		Trap ACTLR
7464  * TSC:		Trap SMC
75
- * TVM:		Trap VM ops (until M+C set in SCTLR_EL1)
7665  * TSW:		Trap cache operations by set/way
7766  * TWE:		Trap WFE
7867  * TWI:		Trap WFI
7968  * TIDCP:	Trap L2CTLR/L2ECTLR
8069  * BSU_IS:	Upgrade barriers to the inner shareable domain
81
- * FB:		Force broadcast of all maintainance operations
70
+ * FB:		Force broadcast of all maintenance operations
8271  * AMO:		Override CPSR.A and enable signaling with VA
8372  * IMO:		Override CPSR.I and enable signaling with VI
8473  * FMO:		Override CPSR.F and enable signaling with VF
....@@ -86,15 +75,16 @@
8675  * PTW:		Take a stage2 fault if a stage1 walk steps in device memory
8776  */
8877 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \
89
-			 HCR_TVM | HCR_BSU_IS | HCR_FB | HCR_TAC | \
78
+			 HCR_BSU_IS | HCR_FB | HCR_TAC | \
9079 			 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \
9180 			 HCR_FMO | HCR_IMO | HCR_PTW )
9281 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF)
93
-#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK)
82
+#define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA)
83
+#define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
9484 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
9585 
9686 /* TCR_EL2 Registers bits */
97
-#define TCR_EL2_RES1		((1 << 31) | (1 << 23))
87
+#define TCR_EL2_RES1		((1U << 31) | (1 << 23))
9888 #define TCR_EL2_TBI		(1 << 20)
9989 #define TCR_EL2_PS_SHIFT	16
10090 #define TCR_EL2_PS_MASK		(7 << TCR_EL2_PS_SHIFT)
....@@ -111,6 +101,7 @@
111101 #define VTCR_EL2_RES1		(1U << 31)
112102 #define VTCR_EL2_HD		(1 << 22)
113103 #define VTCR_EL2_HA		(1 << 21)
104
+#define VTCR_EL2_PS_SHIFT	TCR_EL2_PS_SHIFT
114105 #define VTCR_EL2_PS_MASK	TCR_EL2_PS_MASK
115106 #define VTCR_EL2_TG0_MASK	TCR_TG0_MASK
116107 #define VTCR_EL2_TG0_4K		TCR_TG0_4K
....@@ -124,62 +115,150 @@
124115 #define VTCR_EL2_IRGN0_WBWA	TCR_IRGN0_WBWA
125116 #define VTCR_EL2_SL0_SHIFT	6
126117 #define VTCR_EL2_SL0_MASK	(3 << VTCR_EL2_SL0_SHIFT)
127
-#define VTCR_EL2_SL0_LVL1	(1 << VTCR_EL2_SL0_SHIFT)
128118 #define VTCR_EL2_T0SZ_MASK	0x3f
129
-#define VTCR_EL2_T0SZ_40B	24
130119 #define VTCR_EL2_VS_SHIFT	19
131120 #define VTCR_EL2_VS_8BIT	(0 << VTCR_EL2_VS_SHIFT)
132121 #define VTCR_EL2_VS_16BIT	(1 << VTCR_EL2_VS_SHIFT)
122
+
123
+#define VTCR_EL2_T0SZ(x)	TCR_T0SZ(x)
133124 
134125 /*
135126  * We configure the Stage-2 page tables to always restrict the IPA space to be
136127  * 40 bits wide (T0SZ = 24).  Systems with a PARange smaller than 40 bits are
137128  * not known to exist and will break with this configuration.
138129  *
139
- * VTCR_EL2.PS is extracted from ID_AA64MMFR0_EL1.PARange at boot time
140
- * (see hyp-init.S).
130
+ * The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2().
141131  *
142132  * Note that when using 4K pages, we concatenate two first level page tables
143133  * together. With 16K pages, we concatenate 16 first level page tables.
144134  *
145
- * The magic numbers used for VTTBR_X in this patch can be found in Tables
146
- * D4-23 and D4-25 in ARM DDI 0487A.b.
147135  */
148136 
149
-#define VTCR_EL2_T0SZ_IPA	VTCR_EL2_T0SZ_40B
150137 #define VTCR_EL2_COMMON_BITS	(VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \
151138 				 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1)
152139 
140
+/*
141
+ * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
142
+ * Interestingly, it depends on the page size.
143
+ * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a
144
+ *
145
+ *	-----------------------------------------
146
+ *	| Entry level		|  4K  | 16K/64K |
147
+ *	------------------------------------------
148
+ *	| Level: 0		|  2   |   -     |
149
+ *	------------------------------------------
150
+ *	| Level: 1		|  1   |   2     |
151
+ *	------------------------------------------
152
+ *	| Level: 2		|  0   |   1     |
153
+ *	------------------------------------------
154
+ *	| Level: 3		|  -   |   0     |
155
+ *	------------------------------------------
156
+ *
157
+ * The table roughly translates to :
158
+ *
159
+ *	SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
160
+ *
161
+ * Where TGRAN_SL0_BASE is a magic number depending on the page size:
162
+ * 	TGRAN_SL0_BASE(4K) = 2
163
+ *	TGRAN_SL0_BASE(16K) = 3
164
+ *	TGRAN_SL0_BASE(64K) = 3
165
+ * provided we take care of ruling out the unsupported cases and
166
+ * Entry_Level = 4 - Number_of_levels.
167
+ *
168
+ */
153169 #ifdef CONFIG_ARM64_64K_PAGES
154
-/*
155
- * Stage2 translation configuration:
156
- * 64kB pages (TG0 = 1)
157
- * 2 level page tables (SL = 1)
158
- */
159
-#define VTCR_EL2_TGRAN_FLAGS		(VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1)
160
-#define VTTBR_X_TGRAN_MAGIC		38
170
+
171
+#define VTCR_EL2_TGRAN			VTCR_EL2_TG0_64K
172
+#define VTCR_EL2_TGRAN_SL0_BASE		3UL
173
+
161174 #elif defined(CONFIG_ARM64_16K_PAGES)
162
-/*
163
- * Stage2 translation configuration:
164
- * 16kB pages (TG0 = 2)
165
- * 2 level page tables (SL = 1)
166
- */
167
-#define VTCR_EL2_TGRAN_FLAGS		(VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1)
168
-#define VTTBR_X_TGRAN_MAGIC		42
175
+
176
+#define VTCR_EL2_TGRAN			VTCR_EL2_TG0_16K
177
+#define VTCR_EL2_TGRAN_SL0_BASE		3UL
178
+
169179 #else	/* 4K */
170
-/*
171
- * Stage2 translation configuration:
172
- * 4kB pages (TG0 = 0)
173
- * 3 level page tables (SL = 1)
174
- */
175
-#define VTCR_EL2_TGRAN_FLAGS		(VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1)
176
-#define VTTBR_X_TGRAN_MAGIC		37
180
+
181
+#define VTCR_EL2_TGRAN			VTCR_EL2_TG0_4K
182
+#define VTCR_EL2_TGRAN_SL0_BASE		2UL
183
+
177184 #endif
178185 
179
-#define VTCR_EL2_FLAGS			(VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS)
180
-#define VTTBR_X				(VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA)
186
+#define VTCR_EL2_LVLS_TO_SL0(levels)	\
187
+	((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
188
+#define VTCR_EL2_SL0_TO_LVLS(sl0)	\
189
+	((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
190
+#define VTCR_EL2_LVLS(vtcr)		\
191
+	VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT)
181192 
182
-#define VTTBR_BADDR_MASK  (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X)
193
+#define VTCR_EL2_FLAGS			(VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN)
194
+#define VTCR_EL2_IPA(vtcr)		(64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
195
+
196
+/*
197
+ * ARM VMSAv8-64 defines an algorithm for finding the translation table
198
+ * descriptors in section D4.2.8 in ARM DDI 0487C.a.
199
+ *
200
+ * The algorithm defines the expectations on the translation table
201
+ * addresses for each level, based on PAGE_SIZE, entry level
202
+ * and the translation table size (T0SZ). The variable "x" in the
203
+ * algorithm determines the alignment of a table base address at a given
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+ * level and thus determines the alignment of VTTBR:BADDR for stage2
205
+ * page table entry level.
206
+ * Since the number of bits resolved at the entry level could vary
207
+ * depending on the T0SZ, the value of "x" is defined based on a
208
+ * Magic constant for a given PAGE_SIZE and Entry Level. The
209
+ * intermediate levels must be always aligned to the PAGE_SIZE (i.e,
210
+ * x = PAGE_SHIFT).
211
+ *
212
+ * The value of "x" for entry level is calculated as :
213
+ *    x = Magic_N - T0SZ
214
+ *
215
+ * where Magic_N is an integer depending on the page size and the entry
216
+ * level of the page table as below:
217
+ *
218
+ *	--------------------------------------------
219
+ *	| Entry level		|  4K    16K   64K |
220
+ *	--------------------------------------------
221
+ *	| Level: 0 (4 levels)	| 28   |  -  |  -  |
222
+ *	--------------------------------------------
223
+ *	| Level: 1 (3 levels)	| 37   | 31  | 25  |
224
+ *	--------------------------------------------
225
+ *	| Level: 2 (2 levels)	| 46   | 42  | 38  |
226
+ *	--------------------------------------------
227
+ *	| Level: 3 (1 level)	| -    | 53  | 51  |
228
+ *	--------------------------------------------
229
+ *
230
+ * We have a magic formula for the Magic_N below:
231
+ *
232
+ *  Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
233
+ *
234
+ * where Number_of_levels = (4 - Level). We are only interested in the
235
+ * value for Entry_Level for the stage2 page table.
236
+ *
237
+ * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
238
+ *
239
+ *	x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
240
+ *	  = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
241
+ *
242
+ * Here is one way to explain the Magic Formula:
243
+ *
244
+ *  x = log2(Size_of_Entry_Level_Table)
245
+ *
246
+ * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
247
+ * PAGE_SHIFT bits in the PTE, we have :
248
+ *
249
+ *  Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
250
+ *		     = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
251
+ *  where n = number of levels, and since each pointer is 8bytes, we have:
252
+ *
253
+ *  x = Bits_Entry_Level + 3
254
+ *    = IPA_SHIFT - (PAGE_SHIFT - 3) * n
255
+ *
256
+ * The only constraint here is that, we have to find the number of page table
257
+ * levels for a given IPA size (which we do, see stage2_pt_levels())
258
+ */
259
+#define ARM64_VTTBR_X(ipa, levels)	((ipa) - ((levels) * (PAGE_SHIFT - 3)))
260
+
261
+#define VTTBR_CNP_BIT     (UL(1))
183262 #define VTTBR_VMID_SHIFT  (UL(48))
184263 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
185264 
....@@ -190,7 +269,8 @@
190269 #define CPTR_EL2_TFP_SHIFT 10
191270 
192271 /* Hyp Coprocessor Trap Register */
193
-#define CPTR_EL2_TCPAC	(1 << 31)
272
+#define CPTR_EL2_TCPAC	(1U << 31)
273
+#define CPTR_EL2_TAM	(1 << 30)
194274 #define CPTR_EL2_TTA	(1 << 20)
195275 #define CPTR_EL2_TFP	(1 << CPTR_EL2_TFP_SHIFT)
196276 #define CPTR_EL2_TZ	(1 << 8)
....@@ -198,6 +278,8 @@
198278 #define CPTR_EL2_DEFAULT	CPTR_EL2_RES1
199279 
200280 /* Hyp Debug Configuration Register bits */
281
+#define MDCR_EL2_E2TB_MASK	(UL(0x3))
282
+#define MDCR_EL2_E2TB_SHIFT	(UL(24))
201283 #define MDCR_EL2_TTRF		(1 << 19)
202284 #define MDCR_EL2_TPMS		(1 << 14)
203285 #define MDCR_EL2_E2PB_MASK	(UL(0x3))
....@@ -228,18 +310,22 @@
228310 
229311 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
230312 #define HPFAR_MASK	(~UL(0xf))
231
-
232
-#define kvm_arm_exception_type	\
233
-	{0, "IRQ" }, 		\
234
-	{1, "TRAP" }
313
+/*
314
+ * We have
315
+ *	PAR	[PA_Shift - 1	: 12] = PA	[PA_Shift - 1 : 12]
316
+ *	HPFAR	[PA_Shift - 9	: 4]  = FIPA	[PA_Shift - 1 : 12]
317
+ */
318
+#define PAR_TO_HPFAR(par)		\
319
+	(((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8)
235320 
236321 #define ECN(x) { ESR_ELx_EC_##x, #x }
237322 
238323 #define kvm_arm_exception_class \
239324 	ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \
240
-	ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(CP14_64), ECN(SVC64), \
241
-	ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(IMP_DEF), ECN(IABT_LOW), \
242
-	ECN(IABT_CUR), ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
325
+	ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \
326
+	ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \
327
+	ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \
328
+	ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \
243329 	ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \
244330 	ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \
245331 	ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \