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2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 
 kernel/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * Hardware modules present on the OMAP44xx chips
34  *
....@@ -14,18 +15,9 @@
1415  * up-to-date with the file contents.
1516  * Note that this file is currently not in sync with autogeneration scripts.
1617  * The above note to be removed, once it is synced up.
17
- *
18
- * This program is free software; you can redistribute it and/or modify
19
- * it under the terms of the GNU General Public License version 2 as
20
- * published by the Free Software Foundation.
2118  */
2219 
2320 #include <linux/io.h>
24
-#include <linux/platform_data/hsmmc-omap.h>
25
-#include <linux/power/smartreflex.h>
26
-#include <linux/platform_data/i2c-omap.h>
27
-
28
-#include <linux/omap-dma.h>
2921 
3022 #include "omap_hwmod.h"
3123 #include "omap_hwmod_common_data.h"
....@@ -33,14 +25,9 @@
3325 #include "cm2_44xx.h"
3426 #include "prm44xx.h"
3527 #include "prm-regbits-44xx.h"
36
-#include "i2c.h"
37
-#include "wd_timer.h"
3828 
3929 /* Base offset for all OMAP4 interrupts external to MPUSS */
4030 #define OMAP44XX_IRQ_GIC_START	32
41
-
42
-/* Base offset for all OMAP4 dma requests */
43
-#define OMAP44XX_DMA_REQ_START	1
4431 
4532 /*
4633  * IP blocks
....@@ -137,21 +124,6 @@
137124 	.name	= "l4",
138125 };
139126 
140
-/* l4_abe */
141
-static struct omap_hwmod omap44xx_l4_abe_hwmod = {
142
-	.name		= "l4_abe",
143
-	.class		= &omap44xx_l4_hwmod_class,
144
-	.clkdm_name	= "abe_clkdm",
145
-	.prcm = {
146
-		.omap4 = {
147
-			.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
148
-			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
149
-			.lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
150
-			.flags	      = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151
-		},
152
-	},
153
-};
154
-
155127 /* l4_cfg */
156128 static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
157129 	.name		= "l4_cfg",
....@@ -245,99 +217,6 @@
245217  */
246218 
247219 /*
248
- * 'aess' class
249
- * audio engine sub system
250
- */
251
-
252
-static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
253
-	.rev_offs	= 0x0000,
254
-	.sysc_offs	= 0x0010,
255
-	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
256
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
257
-			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
258
-			   MSTANDBY_SMART_WKUP),
259
-	.sysc_fields	= &omap_hwmod_sysc_type2,
260
-};
261
-
262
-static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
263
-	.name	= "aess",
264
-	.sysc	= &omap44xx_aess_sysc,
265
-	.enable_preprogram = omap_hwmod_aess_preprogram,
266
-};
267
-
268
-/* aess */
269
-static struct omap_hwmod omap44xx_aess_hwmod = {
270
-	.name		= "aess",
271
-	.class		= &omap44xx_aess_hwmod_class,
272
-	.clkdm_name	= "abe_clkdm",
273
-	.main_clk	= "aess_fclk",
274
-	.prcm = {
275
-		.omap4 = {
276
-			.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
277
-			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
278
-			.lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
279
-			.modulemode   = MODULEMODE_SWCTRL,
280
-		},
281
-	},
282
-};
283
-
284
-/*
285
- * 'c2c' class
286
- * chip 2 chip interface used to plug the ape soc (omap) with an external modem
287
- * soc
288
- */
289
-
290
-static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
291
-	.name	= "c2c",
292
-};
293
-
294
-/* c2c */
295
-static struct omap_hwmod omap44xx_c2c_hwmod = {
296
-	.name		= "c2c",
297
-	.class		= &omap44xx_c2c_hwmod_class,
298
-	.clkdm_name	= "d2d_clkdm",
299
-	.prcm = {
300
-		.omap4 = {
301
-			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
302
-			.context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
303
-		},
304
-	},
305
-};
306
-
307
-/*
308
- * 'counter' class
309
- * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
310
- */
311
-
312
-static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
313
-	.rev_offs	= 0x0000,
314
-	.sysc_offs	= 0x0004,
315
-	.sysc_flags	= SYSC_HAS_SIDLEMODE,
316
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
317
-	.sysc_fields	= &omap_hwmod_sysc_type1,
318
-};
319
-
320
-static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
321
-	.name	= "counter",
322
-	.sysc	= &omap44xx_counter_sysc,
323
-};
324
-
325
-/* counter_32k */
326
-static struct omap_hwmod omap44xx_counter_32k_hwmod = {
327
-	.name		= "counter_32k",
328
-	.class		= &omap44xx_counter_hwmod_class,
329
-	.clkdm_name	= "l4_wkup_clkdm",
330
-	.flags		= HWMOD_SWSUP_SIDLE,
331
-	.main_clk	= "sys_32k_ck",
332
-	.prcm = {
333
-		.omap4 = {
334
-			.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
335
-			.context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
336
-		},
337
-	},
338
-};
339
-
340
-/*
341220  * 'ctrl_module' class
342221  * attila core control module + core pad control module + wkup pad control
343222  * module + attila wkup control module
....@@ -429,446 +308,6 @@
429308 };
430309 
431310 /*
432
- * 'dma' class
433
- * dma controller for data exchange between memory to memory (i.e. internal or
434
- * external memory) and gp peripherals to memory or memory to gp peripherals
435
- */
436
-
437
-static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
438
-	.rev_offs	= 0x0000,
439
-	.sysc_offs	= 0x002c,
440
-	.syss_offs	= 0x0028,
441
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
442
-			   SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
443
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
444
-			   SYSS_HAS_RESET_STATUS),
445
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
446
-			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
447
-	.sysc_fields	= &omap_hwmod_sysc_type1,
448
-};
449
-
450
-static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
451
-	.name	= "dma",
452
-	.sysc	= &omap44xx_dma_sysc,
453
-};
454
-
455
-/* dma dev_attr */
456
-static struct omap_dma_dev_attr dma_dev_attr = {
457
-	.dev_caps	= RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
458
-			  IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
459
-	.lch_count	= 32,
460
-};
461
-
462
-/* dma_system */
463
-static struct omap_hwmod omap44xx_dma_system_hwmod = {
464
-	.name		= "dma_system",
465
-	.class		= &omap44xx_dma_hwmod_class,
466
-	.clkdm_name	= "l3_dma_clkdm",
467
-	.main_clk	= "l3_div_ck",
468
-	.prcm = {
469
-		.omap4 = {
470
-			.clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
471
-			.context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
472
-		},
473
-	},
474
-	.dev_attr	= &dma_dev_attr,
475
-};
476
-
477
-/*
478
- * 'dmic' class
479
- * digital microphone controller
480
- */
481
-
482
-static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
483
-	.rev_offs	= 0x0000,
484
-	.sysc_offs	= 0x0010,
485
-	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
486
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
487
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
488
-			   SIDLE_SMART_WKUP),
489
-	.sysc_fields	= &omap_hwmod_sysc_type2,
490
-};
491
-
492
-static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
493
-	.name	= "dmic",
494
-	.sysc	= &omap44xx_dmic_sysc,
495
-};
496
-
497
-/* dmic */
498
-static struct omap_hwmod omap44xx_dmic_hwmod = {
499
-	.name		= "dmic",
500
-	.class		= &omap44xx_dmic_hwmod_class,
501
-	.clkdm_name	= "abe_clkdm",
502
-	.main_clk	= "func_dmic_abe_gfclk",
503
-	.prcm = {
504
-		.omap4 = {
505
-			.clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
506
-			.context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
507
-			.modulemode   = MODULEMODE_SWCTRL,
508
-		},
509
-	},
510
-};
511
-
512
-/*
513
- * 'dsp' class
514
- * dsp sub-system
515
- */
516
-
517
-static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
518
-	.name	= "dsp",
519
-};
520
-
521
-/* dsp */
522
-static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
523
-	{ .name = "dsp", .rst_shift = 0 },
524
-};
525
-
526
-static struct omap_hwmod omap44xx_dsp_hwmod = {
527
-	.name		= "dsp",
528
-	.class		= &omap44xx_dsp_hwmod_class,
529
-	.clkdm_name	= "tesla_clkdm",
530
-	.rst_lines	= omap44xx_dsp_resets,
531
-	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_resets),
532
-	.main_clk	= "dpll_iva_m4x2_ck",
533
-	.prcm = {
534
-		.omap4 = {
535
-			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
536
-			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
537
-			.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
538
-			.modulemode   = MODULEMODE_HWCTRL,
539
-		},
540
-	},
541
-};
542
-
543
-/*
544
- * 'dss' class
545
- * display sub-system
546
- */
547
-
548
-static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
549
-	.rev_offs	= 0x0000,
550
-	.syss_offs	= 0x0014,
551
-	.sysc_flags	= SYSS_HAS_RESET_STATUS,
552
-};
553
-
554
-static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
555
-	.name	= "dss",
556
-	.sysc	= &omap44xx_dss_sysc,
557
-	.reset	= omap_dss_reset,
558
-};
559
-
560
-/* dss */
561
-static struct omap_hwmod_opt_clk dss_opt_clks[] = {
562
-	{ .role = "sys_clk", .clk = "dss_sys_clk" },
563
-	{ .role = "tv_clk", .clk = "dss_tv_clk" },
564
-	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
565
-};
566
-
567
-static struct omap_hwmod omap44xx_dss_hwmod = {
568
-	.name		= "dss_core",
569
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
570
-	.class		= &omap44xx_dss_hwmod_class,
571
-	.clkdm_name	= "l3_dss_clkdm",
572
-	.main_clk	= "dss_dss_clk",
573
-	.prcm = {
574
-		.omap4 = {
575
-			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
576
-			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
577
-			.modulemode   = MODULEMODE_SWCTRL,
578
-		},
579
-	},
580
-	.opt_clks	= dss_opt_clks,
581
-	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
582
-};
583
-
584
-/*
585
- * 'dispc' class
586
- * display controller
587
- */
588
-
589
-static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
590
-	.rev_offs	= 0x0000,
591
-	.sysc_offs	= 0x0010,
592
-	.syss_offs	= 0x0014,
593
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
594
-			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
595
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
596
-			   SYSS_HAS_RESET_STATUS),
597
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
598
-			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
599
-	.sysc_fields	= &omap_hwmod_sysc_type1,
600
-};
601
-
602
-static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
603
-	.name	= "dispc",
604
-	.sysc	= &omap44xx_dispc_sysc,
605
-};
606
-
607
-/* dss_dispc */
608
-static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
609
-	.manager_count		= 3,
610
-	.has_framedonetv_irq	= 1
611
-};
612
-
613
-static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
614
-	.name		= "dss_dispc",
615
-	.class		= &omap44xx_dispc_hwmod_class,
616
-	.clkdm_name	= "l3_dss_clkdm",
617
-	.main_clk	= "dss_dss_clk",
618
-	.prcm = {
619
-		.omap4 = {
620
-			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
621
-			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
622
-		},
623
-	},
624
-	.dev_attr	= &omap44xx_dss_dispc_dev_attr,
625
-	.parent_hwmod	= &omap44xx_dss_hwmod,
626
-};
627
-
628
-/*
629
- * 'dsi' class
630
- * display serial interface controller
631
- */
632
-
633
-static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
634
-	.rev_offs	= 0x0000,
635
-	.sysc_offs	= 0x0010,
636
-	.syss_offs	= 0x0014,
637
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
638
-			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
639
-			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
640
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
641
-	.sysc_fields	= &omap_hwmod_sysc_type1,
642
-};
643
-
644
-static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
645
-	.name	= "dsi",
646
-	.sysc	= &omap44xx_dsi_sysc,
647
-};
648
-
649
-/* dss_dsi1 */
650
-static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
651
-	{ .role = "sys_clk", .clk = "dss_sys_clk" },
652
-};
653
-
654
-static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
655
-	.name		= "dss_dsi1",
656
-	.class		= &omap44xx_dsi_hwmod_class,
657
-	.clkdm_name	= "l3_dss_clkdm",
658
-	.main_clk	= "dss_dss_clk",
659
-	.prcm = {
660
-		.omap4 = {
661
-			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
662
-			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
663
-		},
664
-	},
665
-	.opt_clks	= dss_dsi1_opt_clks,
666
-	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
667
-	.parent_hwmod	= &omap44xx_dss_hwmod,
668
-};
669
-
670
-/* dss_dsi2 */
671
-static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
672
-	{ .role = "sys_clk", .clk = "dss_sys_clk" },
673
-};
674
-
675
-static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
676
-	.name		= "dss_dsi2",
677
-	.class		= &omap44xx_dsi_hwmod_class,
678
-	.clkdm_name	= "l3_dss_clkdm",
679
-	.main_clk	= "dss_dss_clk",
680
-	.prcm = {
681
-		.omap4 = {
682
-			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
683
-			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
684
-		},
685
-	},
686
-	.opt_clks	= dss_dsi2_opt_clks,
687
-	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi2_opt_clks),
688
-	.parent_hwmod	= &omap44xx_dss_hwmod,
689
-};
690
-
691
-/*
692
- * 'hdmi' class
693
- * hdmi controller
694
- */
695
-
696
-static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
697
-	.rev_offs	= 0x0000,
698
-	.sysc_offs	= 0x0010,
699
-	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
700
-			   SYSC_HAS_SOFTRESET),
701
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
702
-			   SIDLE_SMART_WKUP),
703
-	.sysc_fields	= &omap_hwmod_sysc_type2,
704
-};
705
-
706
-static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
707
-	.name	= "hdmi",
708
-	.sysc	= &omap44xx_hdmi_sysc,
709
-};
710
-
711
-/* dss_hdmi */
712
-static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
713
-	{ .role = "sys_clk", .clk = "dss_sys_clk" },
714
-	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
715
-};
716
-
717
-static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
718
-	.name		= "dss_hdmi",
719
-	.class		= &omap44xx_hdmi_hwmod_class,
720
-	.clkdm_name	= "l3_dss_clkdm",
721
-	/*
722
-	 * HDMI audio requires to use no-idle mode. Hence,
723
-	 * set idle mode by software.
724
-	 */
725
-	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
726
-	.main_clk	= "dss_48mhz_clk",
727
-	.prcm = {
728
-		.omap4 = {
729
-			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
730
-			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
731
-		},
732
-	},
733
-	.opt_clks	= dss_hdmi_opt_clks,
734
-	.opt_clks_cnt	= ARRAY_SIZE(dss_hdmi_opt_clks),
735
-	.parent_hwmod	= &omap44xx_dss_hwmod,
736
-};
737
-
738
-/*
739
- * 'rfbi' class
740
- * remote frame buffer interface
741
- */
742
-
743
-static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
744
-	.rev_offs	= 0x0000,
745
-	.sysc_offs	= 0x0010,
746
-	.syss_offs	= 0x0014,
747
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
748
-			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
749
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
750
-	.sysc_fields	= &omap_hwmod_sysc_type1,
751
-};
752
-
753
-static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
754
-	.name	= "rfbi",
755
-	.sysc	= &omap44xx_rfbi_sysc,
756
-};
757
-
758
-/* dss_rfbi */
759
-static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
760
-	{ .role = "ick", .clk = "l3_div_ck" },
761
-};
762
-
763
-static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
764
-	.name		= "dss_rfbi",
765
-	.class		= &omap44xx_rfbi_hwmod_class,
766
-	.clkdm_name	= "l3_dss_clkdm",
767
-	.main_clk	= "dss_dss_clk",
768
-	.prcm = {
769
-		.omap4 = {
770
-			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
771
-			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
772
-		},
773
-	},
774
-	.opt_clks	= dss_rfbi_opt_clks,
775
-	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
776
-	.parent_hwmod	= &omap44xx_dss_hwmod,
777
-};
778
-
779
-/*
780
- * 'venc' class
781
- * video encoder
782
- */
783
-
784
-static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
785
-	.name	= "venc",
786
-};
787
-
788
-/* dss_venc */
789
-static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
790
-	{ .role = "tv_clk", .clk = "dss_tv_clk" },
791
-};
792
-
793
-static struct omap_hwmod omap44xx_dss_venc_hwmod = {
794
-	.name		= "dss_venc",
795
-	.class		= &omap44xx_venc_hwmod_class,
796
-	.clkdm_name	= "l3_dss_clkdm",
797
-	.main_clk	= "dss_tv_clk",
798
-	.flags		= HWMOD_OPT_CLKS_NEEDED,
799
-	.prcm = {
800
-		.omap4 = {
801
-			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
802
-			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
803
-		},
804
-	},
805
-	.parent_hwmod	= &omap44xx_dss_hwmod,
806
-	.opt_clks	= dss_venc_opt_clks,
807
-	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
808
-};
809
-
810
-/* sha0 HIB2 (the 'P' (public) device) */
811
-static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
812
-	.rev_offs	= 0x100,
813
-	.sysc_offs	= 0x110,
814
-	.syss_offs	= 0x114,
815
-	.sysc_flags	= SYSS_HAS_RESET_STATUS,
816
-};
817
-
818
-static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
819
-	.name		= "sham",
820
-	.sysc		= &omap44xx_sha0_sysc,
821
-};
822
-
823
-struct omap_hwmod omap44xx_sha0_hwmod = {
824
-	.name		= "sham",
825
-	.class		= &omap44xx_sha0_hwmod_class,
826
-	.clkdm_name	= "l4_secure_clkdm",
827
-	.main_clk	= "l3_div_ck",
828
-	.prcm		= {
829
-		.omap4 = {
830
-			.clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
831
-			.context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
832
-			.modulemode   = MODULEMODE_SWCTRL,
833
-		},
834
-	},
835
-};
836
-
837
-/*
838
- * 'elm' class
839
- * bch error location module
840
- */
841
-
842
-static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
843
-	.rev_offs	= 0x0000,
844
-	.sysc_offs	= 0x0010,
845
-	.syss_offs	= 0x0014,
846
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
847
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
848
-			   SYSS_HAS_RESET_STATUS),
849
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
850
-	.sysc_fields	= &omap_hwmod_sysc_type1,
851
-};
852
-
853
-static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
854
-	.name	= "elm",
855
-	.sysc	= &omap44xx_elm_sysc,
856
-};
857
-
858
-/* elm */
859
-static struct omap_hwmod omap44xx_elm_hwmod = {
860
-	.name		= "elm",
861
-	.class		= &omap44xx_elm_hwmod_class,
862
-	.clkdm_name	= "l4_per_clkdm",
863
-	.prcm = {
864
-		.omap4 = {
865
-			.clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
866
-			.context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
867
-		},
868
-	},
869
-};
870
-
871
-/*
872311  * 'emif' class
873312  * external memory interface no1
874313  */
....@@ -915,301 +354,6 @@
915354 };
916355 
917356 /*
918
-    Crypto modules AES0/1 belong to:
919
-	PD_L4_PER power domain
920
-	CD_L4_SEC clock domain
921
-	On the L3, the AES modules are mapped to
922
-	L3_CLK2: Peripherals and multimedia sub clock domain
923
-*/
924
-static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
925
-	.rev_offs	= 0x80,
926
-	.sysc_offs	= 0x84,
927
-	.syss_offs	= 0x88,
928
-	.sysc_flags	= SYSS_HAS_RESET_STATUS,
929
-};
930
-
931
-static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
932
-	.name		= "aes",
933
-	.sysc		= &omap44xx_aes_sysc,
934
-};
935
-
936
-static struct omap_hwmod omap44xx_aes1_hwmod = {
937
-	.name		= "aes1",
938
-	.class		= &omap44xx_aes_hwmod_class,
939
-	.clkdm_name	= "l4_secure_clkdm",
940
-	.main_clk	= "l3_div_ck",
941
-	.prcm		= {
942
-		.omap4	= {
943
-			.context_offs	= OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
944
-			.clkctrl_offs	= OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
945
-			.modulemode	= MODULEMODE_SWCTRL,
946
-		},
947
-	},
948
-};
949
-
950
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
951
-	.master		= &omap44xx_l4_per_hwmod,
952
-	.slave		= &omap44xx_aes1_hwmod,
953
-	.clk		= "l3_div_ck",
954
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
955
-};
956
-
957
-static struct omap_hwmod omap44xx_aes2_hwmod = {
958
-	.name		= "aes2",
959
-	.class		= &omap44xx_aes_hwmod_class,
960
-	.clkdm_name	= "l4_secure_clkdm",
961
-	.main_clk	= "l3_div_ck",
962
-	.prcm		= {
963
-		.omap4	= {
964
-			.context_offs	= OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
965
-			.clkctrl_offs	= OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
966
-			.modulemode	= MODULEMODE_SWCTRL,
967
-		},
968
-	},
969
-};
970
-
971
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
972
-	.master		= &omap44xx_l4_per_hwmod,
973
-	.slave		= &omap44xx_aes2_hwmod,
974
-	.clk		= "l3_div_ck",
975
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
976
-};
977
-
978
-/*
979
- * 'des' class for DES3DES module
980
- */
981
-static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
982
-	.rev_offs	= 0x30,
983
-	.sysc_offs	= 0x34,
984
-	.syss_offs	= 0x38,
985
-	.sysc_flags	= SYSS_HAS_RESET_STATUS,
986
-};
987
-
988
-static struct omap_hwmod_class omap44xx_des_hwmod_class = {
989
-	.name		= "des",
990
-	.sysc		= &omap44xx_des_sysc,
991
-};
992
-
993
-static struct omap_hwmod omap44xx_des_hwmod = {
994
-	.name		= "des",
995
-	.class		= &omap44xx_des_hwmod_class,
996
-	.clkdm_name	= "l4_secure_clkdm",
997
-	.main_clk	= "l3_div_ck",
998
-	.prcm		= {
999
-		.omap4	= {
1000
-			.context_offs	= OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1001
-			.clkctrl_offs	= OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
1002
-			.modulemode	= MODULEMODE_SWCTRL,
1003
-		},
1004
-	},
1005
-};
1006
-
1007
-struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
1008
-	.master		= &omap44xx_l3_main_2_hwmod,
1009
-	.slave		= &omap44xx_des_hwmod,
1010
-	.clk		= "l3_div_ck",
1011
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1012
-};
1013
-
1014
-/*
1015
- * 'fdif' class
1016
- * face detection hw accelerator module
1017
- */
1018
-
1019
-static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1020
-	.rev_offs	= 0x0000,
1021
-	.sysc_offs	= 0x0010,
1022
-	/*
1023
-	 * FDIF needs 100 OCP clk cycles delay after a softreset before
1024
-	 * accessing sysconfig again.
1025
-	 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1026
-	 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1027
-	 *
1028
-	 * TODO: Indicate errata when available.
1029
-	 */
1030
-	.srst_udelay	= 2,
1031
-	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1032
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1033
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1034
-			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1035
-	.sysc_fields	= &omap_hwmod_sysc_type2,
1036
-};
1037
-
1038
-static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1039
-	.name	= "fdif",
1040
-	.sysc	= &omap44xx_fdif_sysc,
1041
-};
1042
-
1043
-/* fdif */
1044
-static struct omap_hwmod omap44xx_fdif_hwmod = {
1045
-	.name		= "fdif",
1046
-	.class		= &omap44xx_fdif_hwmod_class,
1047
-	.clkdm_name	= "iss_clkdm",
1048
-	.main_clk	= "fdif_fck",
1049
-	.prcm = {
1050
-		.omap4 = {
1051
-			.clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1052
-			.context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1053
-			.modulemode   = MODULEMODE_SWCTRL,
1054
-		},
1055
-	},
1056
-};
1057
-
1058
-/*
1059
- * 'gpio' class
1060
- * general purpose io module
1061
- */
1062
-
1063
-static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1064
-	.rev_offs	= 0x0000,
1065
-	.sysc_offs	= 0x0010,
1066
-	.syss_offs	= 0x0114,
1067
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1068
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1069
-			   SYSS_HAS_RESET_STATUS),
1070
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1071
-			   SIDLE_SMART_WKUP),
1072
-	.sysc_fields	= &omap_hwmod_sysc_type1,
1073
-};
1074
-
1075
-static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1076
-	.name	= "gpio",
1077
-	.sysc	= &omap44xx_gpio_sysc,
1078
-	.rev	= 2,
1079
-};
1080
-
1081
-/* gpio1 */
1082
-static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1083
-	{ .role = "dbclk", .clk = "gpio1_dbclk" },
1084
-};
1085
-
1086
-static struct omap_hwmod omap44xx_gpio1_hwmod = {
1087
-	.name		= "gpio1",
1088
-	.class		= &omap44xx_gpio_hwmod_class,
1089
-	.clkdm_name	= "l4_wkup_clkdm",
1090
-	.main_clk	= "l4_wkup_clk_mux_ck",
1091
-	.prcm = {
1092
-		.omap4 = {
1093
-			.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1094
-			.context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1095
-			.modulemode   = MODULEMODE_HWCTRL,
1096
-		},
1097
-	},
1098
-	.opt_clks	= gpio1_opt_clks,
1099
-	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
1100
-};
1101
-
1102
-/* gpio2 */
1103
-static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1104
-	{ .role = "dbclk", .clk = "gpio2_dbclk" },
1105
-};
1106
-
1107
-static struct omap_hwmod omap44xx_gpio2_hwmod = {
1108
-	.name		= "gpio2",
1109
-	.class		= &omap44xx_gpio_hwmod_class,
1110
-	.clkdm_name	= "l4_per_clkdm",
1111
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1112
-	.main_clk	= "l4_div_ck",
1113
-	.prcm = {
1114
-		.omap4 = {
1115
-			.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1116
-			.context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1117
-			.modulemode   = MODULEMODE_HWCTRL,
1118
-		},
1119
-	},
1120
-	.opt_clks	= gpio2_opt_clks,
1121
-	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
1122
-};
1123
-
1124
-/* gpio3 */
1125
-static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1126
-	{ .role = "dbclk", .clk = "gpio3_dbclk" },
1127
-};
1128
-
1129
-static struct omap_hwmod omap44xx_gpio3_hwmod = {
1130
-	.name		= "gpio3",
1131
-	.class		= &omap44xx_gpio_hwmod_class,
1132
-	.clkdm_name	= "l4_per_clkdm",
1133
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1134
-	.main_clk	= "l4_div_ck",
1135
-	.prcm = {
1136
-		.omap4 = {
1137
-			.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1138
-			.context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1139
-			.modulemode   = MODULEMODE_HWCTRL,
1140
-		},
1141
-	},
1142
-	.opt_clks	= gpio3_opt_clks,
1143
-	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
1144
-};
1145
-
1146
-/* gpio4 */
1147
-static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1148
-	{ .role = "dbclk", .clk = "gpio4_dbclk" },
1149
-};
1150
-
1151
-static struct omap_hwmod omap44xx_gpio4_hwmod = {
1152
-	.name		= "gpio4",
1153
-	.class		= &omap44xx_gpio_hwmod_class,
1154
-	.clkdm_name	= "l4_per_clkdm",
1155
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1156
-	.main_clk	= "l4_div_ck",
1157
-	.prcm = {
1158
-		.omap4 = {
1159
-			.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1160
-			.context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1161
-			.modulemode   = MODULEMODE_HWCTRL,
1162
-		},
1163
-	},
1164
-	.opt_clks	= gpio4_opt_clks,
1165
-	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
1166
-};
1167
-
1168
-/* gpio5 */
1169
-static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1170
-	{ .role = "dbclk", .clk = "gpio5_dbclk" },
1171
-};
1172
-
1173
-static struct omap_hwmod omap44xx_gpio5_hwmod = {
1174
-	.name		= "gpio5",
1175
-	.class		= &omap44xx_gpio_hwmod_class,
1176
-	.clkdm_name	= "l4_per_clkdm",
1177
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1178
-	.main_clk	= "l4_div_ck",
1179
-	.prcm = {
1180
-		.omap4 = {
1181
-			.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1182
-			.context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1183
-			.modulemode   = MODULEMODE_HWCTRL,
1184
-		},
1185
-	},
1186
-	.opt_clks	= gpio5_opt_clks,
1187
-	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
1188
-};
1189
-
1190
-/* gpio6 */
1191
-static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1192
-	{ .role = "dbclk", .clk = "gpio6_dbclk" },
1193
-};
1194
-
1195
-static struct omap_hwmod omap44xx_gpio6_hwmod = {
1196
-	.name		= "gpio6",
1197
-	.class		= &omap44xx_gpio_hwmod_class,
1198
-	.clkdm_name	= "l4_per_clkdm",
1199
-	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1200
-	.main_clk	= "l4_div_ck",
1201
-	.prcm = {
1202
-		.omap4 = {
1203
-			.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1204
-			.context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1205
-			.modulemode   = MODULEMODE_HWCTRL,
1206
-		},
1207
-	},
1208
-	.opt_clks	= gpio6_opt_clks,
1209
-	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
1210
-};
1211
-
1212
-/*
1213357  * 'gpmc' class
1214358  * general purpose memory controller
1215359  */
....@@ -1240,235 +384,6 @@
1240384 		.omap4 = {
1241385 			.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1242386 			.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1243
-			.modulemode   = MODULEMODE_HWCTRL,
1244
-		},
1245
-	},
1246
-};
1247
-
1248
-/*
1249
- * 'gpu' class
1250
- * 2d/3d graphics accelerator
1251
- */
1252
-
1253
-static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1254
-	.rev_offs	= 0x1fc00,
1255
-	.sysc_offs	= 0x1fc10,
1256
-	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1257
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1258
-			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1259
-			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1260
-	.sysc_fields	= &omap_hwmod_sysc_type2,
1261
-};
1262
-
1263
-static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1264
-	.name	= "gpu",
1265
-	.sysc	= &omap44xx_gpu_sysc,
1266
-};
1267
-
1268
-/* gpu */
1269
-static struct omap_hwmod omap44xx_gpu_hwmod = {
1270
-	.name		= "gpu",
1271
-	.class		= &omap44xx_gpu_hwmod_class,
1272
-	.clkdm_name	= "l3_gfx_clkdm",
1273
-	.main_clk	= "sgx_clk_mux",
1274
-	.prcm = {
1275
-		.omap4 = {
1276
-			.clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1277
-			.context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1278
-			.modulemode   = MODULEMODE_SWCTRL,
1279
-		},
1280
-	},
1281
-};
1282
-
1283
-/*
1284
- * 'hdq1w' class
1285
- * hdq / 1-wire serial interface controller
1286
- */
1287
-
1288
-static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1289
-	.rev_offs	= 0x0000,
1290
-	.sysc_offs	= 0x0014,
1291
-	.syss_offs	= 0x0018,
1292
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1293
-			   SYSS_HAS_RESET_STATUS),
1294
-	.sysc_fields	= &omap_hwmod_sysc_type1,
1295
-};
1296
-
1297
-static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1298
-	.name	= "hdq1w",
1299
-	.sysc	= &omap44xx_hdq1w_sysc,
1300
-};
1301
-
1302
-/* hdq1w */
1303
-static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1304
-	.name		= "hdq1w",
1305
-	.class		= &omap44xx_hdq1w_hwmod_class,
1306
-	.clkdm_name	= "l4_per_clkdm",
1307
-	.flags		= HWMOD_INIT_NO_RESET, /* XXX temporary */
1308
-	.main_clk	= "func_12m_fclk",
1309
-	.prcm = {
1310
-		.omap4 = {
1311
-			.clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1312
-			.context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1313
-			.modulemode   = MODULEMODE_SWCTRL,
1314
-		},
1315
-	},
1316
-};
1317
-
1318
-/*
1319
- * 'hsi' class
1320
- * mipi high-speed synchronous serial interface (multichannel and full-duplex
1321
- * serial if)
1322
- */
1323
-
1324
-static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1325
-	.rev_offs	= 0x0000,
1326
-	.sysc_offs	= 0x0010,
1327
-	.syss_offs	= 0x0014,
1328
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1329
-			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1330
-			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1331
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1332
-			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1333
-			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1334
-	.sysc_fields	= &omap_hwmod_sysc_type1,
1335
-};
1336
-
1337
-static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1338
-	.name	= "hsi",
1339
-	.sysc	= &omap44xx_hsi_sysc,
1340
-};
1341
-
1342
-/* hsi */
1343
-static struct omap_hwmod omap44xx_hsi_hwmod = {
1344
-	.name		= "hsi",
1345
-	.class		= &omap44xx_hsi_hwmod_class,
1346
-	.clkdm_name	= "l3_init_clkdm",
1347
-	.main_clk	= "hsi_fck",
1348
-	.prcm = {
1349
-		.omap4 = {
1350
-			.clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1351
-			.context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1352
-			.modulemode   = MODULEMODE_HWCTRL,
1353
-		},
1354
-	},
1355
-};
1356
-
1357
-/*
1358
- * 'i2c' class
1359
- * multimaster high-speed i2c controller
1360
- */
1361
-
1362
-static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1363
-	.rev_offs	= 0,
1364
-	.sysc_offs	= 0x0010,
1365
-	.syss_offs	= 0x0090,
1366
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1367
-			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1368
-			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1369
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1370
-			   SIDLE_SMART_WKUP),
1371
-	.sysc_fields	= &omap_hwmod_sysc_type1,
1372
-};
1373
-
1374
-static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1375
-	.name	= "i2c",
1376
-	.sysc	= &omap44xx_i2c_sysc,
1377
-	.rev	= OMAP_I2C_IP_VERSION_2,
1378
-	.reset	= &omap_i2c_reset,
1379
-};
1380
-
1381
-/* i2c1 */
1382
-static struct omap_hwmod omap44xx_i2c1_hwmod = {
1383
-	.name		= "i2c1",
1384
-	.class		= &omap44xx_i2c_hwmod_class,
1385
-	.clkdm_name	= "l4_per_clkdm",
1386
-	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1387
-	.main_clk	= "func_96m_fclk",
1388
-	.prcm = {
1389
-		.omap4 = {
1390
-			.clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1391
-			.context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1392
-			.modulemode   = MODULEMODE_SWCTRL,
1393
-		},
1394
-	},
1395
-};
1396
-
1397
-/* i2c2 */
1398
-static struct omap_hwmod omap44xx_i2c2_hwmod = {
1399
-	.name		= "i2c2",
1400
-	.class		= &omap44xx_i2c_hwmod_class,
1401
-	.clkdm_name	= "l4_per_clkdm",
1402
-	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1403
-	.main_clk	= "func_96m_fclk",
1404
-	.prcm = {
1405
-		.omap4 = {
1406
-			.clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1407
-			.context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1408
-			.modulemode   = MODULEMODE_SWCTRL,
1409
-		},
1410
-	},
1411
-};
1412
-
1413
-/* i2c3 */
1414
-static struct omap_hwmod omap44xx_i2c3_hwmod = {
1415
-	.name		= "i2c3",
1416
-	.class		= &omap44xx_i2c_hwmod_class,
1417
-	.clkdm_name	= "l4_per_clkdm",
1418
-	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1419
-	.main_clk	= "func_96m_fclk",
1420
-	.prcm = {
1421
-		.omap4 = {
1422
-			.clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1423
-			.context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1424
-			.modulemode   = MODULEMODE_SWCTRL,
1425
-		},
1426
-	},
1427
-};
1428
-
1429
-/* i2c4 */
1430
-static struct omap_hwmod omap44xx_i2c4_hwmod = {
1431
-	.name		= "i2c4",
1432
-	.class		= &omap44xx_i2c_hwmod_class,
1433
-	.clkdm_name	= "l4_per_clkdm",
1434
-	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1435
-	.main_clk	= "func_96m_fclk",
1436
-	.prcm = {
1437
-		.omap4 = {
1438
-			.clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1439
-			.context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1440
-			.modulemode   = MODULEMODE_SWCTRL,
1441
-		},
1442
-	},
1443
-};
1444
-
1445
-/*
1446
- * 'ipu' class
1447
- * imaging processor unit
1448
- */
1449
-
1450
-static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1451
-	.name	= "ipu",
1452
-};
1453
-
1454
-/* ipu */
1455
-static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1456
-	{ .name = "cpu0", .rst_shift = 0 },
1457
-	{ .name = "cpu1", .rst_shift = 1 },
1458
-};
1459
-
1460
-static struct omap_hwmod omap44xx_ipu_hwmod = {
1461
-	.name		= "ipu",
1462
-	.class		= &omap44xx_ipu_hwmod_class,
1463
-	.clkdm_name	= "ducati_clkdm",
1464
-	.rst_lines	= omap44xx_ipu_resets,
1465
-	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_resets),
1466
-	.main_clk	= "ducati_clk_mux_ck",
1467
-	.prcm = {
1468
-		.omap4 = {
1469
-			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1470
-			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1471
-			.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1472387 			.modulemode   = MODULEMODE_HWCTRL,
1473388 		},
1474389 	},
....@@ -1559,534 +474,6 @@
1559474 };
1560475 
1561476 /*
1562
- * 'kbd' class
1563
- * keyboard controller
1564
- */
1565
-
1566
-static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1567
-	.rev_offs	= 0x0000,
1568
-	.sysc_offs	= 0x0010,
1569
-	.syss_offs	= 0x0014,
1570
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1571
-			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1572
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1573
-			   SYSS_HAS_RESET_STATUS),
1574
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1575
-	.sysc_fields	= &omap_hwmod_sysc_type1,
1576
-};
1577
-
1578
-static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1579
-	.name	= "kbd",
1580
-	.sysc	= &omap44xx_kbd_sysc,
1581
-};
1582
-
1583
-/* kbd */
1584
-static struct omap_hwmod omap44xx_kbd_hwmod = {
1585
-	.name		= "kbd",
1586
-	.class		= &omap44xx_kbd_hwmod_class,
1587
-	.clkdm_name	= "l4_wkup_clkdm",
1588
-	.main_clk	= "sys_32k_ck",
1589
-	.prcm = {
1590
-		.omap4 = {
1591
-			.clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1592
-			.context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1593
-			.modulemode   = MODULEMODE_SWCTRL,
1594
-		},
1595
-	},
1596
-};
1597
-
1598
-/*
1599
- * 'mailbox' class
1600
- * mailbox module allowing communication between the on-chip processors using a
1601
- * queued mailbox-interrupt mechanism.
1602
- */
1603
-
1604
-static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1605
-	.rev_offs	= 0x0000,
1606
-	.sysc_offs	= 0x0010,
1607
-	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1608
-			   SYSC_HAS_SOFTRESET),
1609
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1610
-	.sysc_fields	= &omap_hwmod_sysc_type2,
1611
-};
1612
-
1613
-static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1614
-	.name	= "mailbox",
1615
-	.sysc	= &omap44xx_mailbox_sysc,
1616
-};
1617
-
1618
-/* mailbox */
1619
-static struct omap_hwmod omap44xx_mailbox_hwmod = {
1620
-	.name		= "mailbox",
1621
-	.class		= &omap44xx_mailbox_hwmod_class,
1622
-	.clkdm_name	= "l4_cfg_clkdm",
1623
-	.prcm = {
1624
-		.omap4 = {
1625
-			.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1626
-			.context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1627
-		},
1628
-	},
1629
-};
1630
-
1631
-/*
1632
- * 'mcasp' class
1633
- * multi-channel audio serial port controller
1634
- */
1635
-
1636
-/* The IP is not compliant to type1 / type2 scheme */
1637
-static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1638
-	.rev_offs	= 0,
1639
-	.sysc_offs	= 0x0004,
1640
-	.sysc_flags	= SYSC_HAS_SIDLEMODE,
1641
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1642
-			   SIDLE_SMART_WKUP),
1643
-	.sysc_fields	= &omap_hwmod_sysc_type_mcasp,
1644
-};
1645
-
1646
-static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1647
-	.name	= "mcasp",
1648
-	.sysc	= &omap44xx_mcasp_sysc,
1649
-};
1650
-
1651
-/* mcasp */
1652
-static struct omap_hwmod omap44xx_mcasp_hwmod = {
1653
-	.name		= "mcasp",
1654
-	.class		= &omap44xx_mcasp_hwmod_class,
1655
-	.clkdm_name	= "abe_clkdm",
1656
-	.main_clk	= "func_mcasp_abe_gfclk",
1657
-	.prcm = {
1658
-		.omap4 = {
1659
-			.clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1660
-			.context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1661
-			.modulemode   = MODULEMODE_SWCTRL,
1662
-		},
1663
-	},
1664
-};
1665
-
1666
-/*
1667
- * 'mcbsp' class
1668
- * multi channel buffered serial port controller
1669
- */
1670
-
1671
-static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1672
-	.rev_offs	= -ENODEV,
1673
-	.sysc_offs	= 0x008c,
1674
-	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1675
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1676
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1677
-	.sysc_fields	= &omap_hwmod_sysc_type1,
1678
-};
1679
-
1680
-static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1681
-	.name	= "mcbsp",
1682
-	.sysc	= &omap44xx_mcbsp_sysc,
1683
-};
1684
-
1685
-/* mcbsp1 */
1686
-static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1687
-	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1688
-	{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1689
-};
1690
-
1691
-static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1692
-	.name		= "mcbsp1",
1693
-	.class		= &omap44xx_mcbsp_hwmod_class,
1694
-	.clkdm_name	= "abe_clkdm",
1695
-	.main_clk	= "func_mcbsp1_gfclk",
1696
-	.prcm = {
1697
-		.omap4 = {
1698
-			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1699
-			.context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1700
-			.modulemode   = MODULEMODE_SWCTRL,
1701
-		},
1702
-	},
1703
-	.opt_clks	= mcbsp1_opt_clks,
1704
-	.opt_clks_cnt	= ARRAY_SIZE(mcbsp1_opt_clks),
1705
-};
1706
-
1707
-/* mcbsp2 */
1708
-static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1709
-	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1710
-	{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1711
-};
1712
-
1713
-static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1714
-	.name		= "mcbsp2",
1715
-	.class		= &omap44xx_mcbsp_hwmod_class,
1716
-	.clkdm_name	= "abe_clkdm",
1717
-	.main_clk	= "func_mcbsp2_gfclk",
1718
-	.prcm = {
1719
-		.omap4 = {
1720
-			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1721
-			.context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1722
-			.modulemode   = MODULEMODE_SWCTRL,
1723
-		},
1724
-	},
1725
-	.opt_clks	= mcbsp2_opt_clks,
1726
-	.opt_clks_cnt	= ARRAY_SIZE(mcbsp2_opt_clks),
1727
-};
1728
-
1729
-/* mcbsp3 */
1730
-static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1731
-	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1732
-	{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1733
-};
1734
-
1735
-static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1736
-	.name		= "mcbsp3",
1737
-	.class		= &omap44xx_mcbsp_hwmod_class,
1738
-	.clkdm_name	= "abe_clkdm",
1739
-	.main_clk	= "func_mcbsp3_gfclk",
1740
-	.prcm = {
1741
-		.omap4 = {
1742
-			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1743
-			.context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1744
-			.modulemode   = MODULEMODE_SWCTRL,
1745
-		},
1746
-	},
1747
-	.opt_clks	= mcbsp3_opt_clks,
1748
-	.opt_clks_cnt	= ARRAY_SIZE(mcbsp3_opt_clks),
1749
-};
1750
-
1751
-/* mcbsp4 */
1752
-static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1753
-	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1754
-	{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1755
-};
1756
-
1757
-static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1758
-	.name		= "mcbsp4",
1759
-	.class		= &omap44xx_mcbsp_hwmod_class,
1760
-	.clkdm_name	= "l4_per_clkdm",
1761
-	.main_clk	= "per_mcbsp4_gfclk",
1762
-	.prcm = {
1763
-		.omap4 = {
1764
-			.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1765
-			.context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1766
-			.modulemode   = MODULEMODE_SWCTRL,
1767
-		},
1768
-	},
1769
-	.opt_clks	= mcbsp4_opt_clks,
1770
-	.opt_clks_cnt	= ARRAY_SIZE(mcbsp4_opt_clks),
1771
-};
1772
-
1773
-/*
1774
- * 'mcpdm' class
1775
- * multi channel pdm controller (proprietary interface with phoenix power
1776
- * ic)
1777
- */
1778
-
1779
-static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1780
-	.rev_offs	= 0x0000,
1781
-	.sysc_offs	= 0x0010,
1782
-	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1783
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1784
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1785
-			   SIDLE_SMART_WKUP),
1786
-	.sysc_fields	= &omap_hwmod_sysc_type2,
1787
-};
1788
-
1789
-static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1790
-	.name	= "mcpdm",
1791
-	.sysc	= &omap44xx_mcpdm_sysc,
1792
-};
1793
-
1794
-/* mcpdm */
1795
-static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1796
-	.name		= "mcpdm",
1797
-	.class		= &omap44xx_mcpdm_hwmod_class,
1798
-	.clkdm_name	= "abe_clkdm",
1799
-	/*
1800
-	 * It's suspected that the McPDM requires an off-chip main
1801
-	 * functional clock, controlled via I2C.  This IP block is
1802
-	 * currently reset very early during boot, before I2C is
1803
-	 * available, so it doesn't seem that we have any choice in
1804
-	 * the kernel other than to avoid resetting it.
1805
-	 *
1806
-	 * Also, McPDM needs to be configured to NO_IDLE mode when it
1807
-	 * is in used otherwise vital clocks will be gated which
1808
-	 * results 'slow motion' audio playback.
1809
-	 */
1810
-	.flags		= HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1811
-	.main_clk	= "pad_clks_ck",
1812
-	.prcm = {
1813
-		.omap4 = {
1814
-			.clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1815
-			.context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1816
-			.modulemode   = MODULEMODE_SWCTRL,
1817
-		},
1818
-	},
1819
-};
1820
-
1821
-/*
1822
- * 'mcspi' class
1823
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
1824
- * bus
1825
- */
1826
-
1827
-static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1828
-	.rev_offs	= 0x0000,
1829
-	.sysc_offs	= 0x0010,
1830
-	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1831
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1832
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1833
-			   SIDLE_SMART_WKUP),
1834
-	.sysc_fields	= &omap_hwmod_sysc_type2,
1835
-};
1836
-
1837
-static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1838
-	.name	= "mcspi",
1839
-	.sysc	= &omap44xx_mcspi_sysc,
1840
-};
1841
-
1842
-/* mcspi1 */
1843
-static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1844
-	.name		= "mcspi1",
1845
-	.class		= &omap44xx_mcspi_hwmod_class,
1846
-	.clkdm_name	= "l4_per_clkdm",
1847
-	.main_clk	= "func_48m_fclk",
1848
-	.prcm = {
1849
-		.omap4 = {
1850
-			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1851
-			.context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1852
-			.modulemode   = MODULEMODE_SWCTRL,
1853
-		},
1854
-	},
1855
-};
1856
-
1857
-/* mcspi2 */
1858
-static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1859
-	.name		= "mcspi2",
1860
-	.class		= &omap44xx_mcspi_hwmod_class,
1861
-	.clkdm_name	= "l4_per_clkdm",
1862
-	.main_clk	= "func_48m_fclk",
1863
-	.prcm = {
1864
-		.omap4 = {
1865
-			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1866
-			.context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1867
-			.modulemode   = MODULEMODE_SWCTRL,
1868
-		},
1869
-	},
1870
-};
1871
-
1872
-/* mcspi3 */
1873
-static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1874
-	.name		= "mcspi3",
1875
-	.class		= &omap44xx_mcspi_hwmod_class,
1876
-	.clkdm_name	= "l4_per_clkdm",
1877
-	.main_clk	= "func_48m_fclk",
1878
-	.prcm = {
1879
-		.omap4 = {
1880
-			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1881
-			.context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1882
-			.modulemode   = MODULEMODE_SWCTRL,
1883
-		},
1884
-	},
1885
-};
1886
-
1887
-/* mcspi4 */
1888
-static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1889
-	.name		= "mcspi4",
1890
-	.class		= &omap44xx_mcspi_hwmod_class,
1891
-	.clkdm_name	= "l4_per_clkdm",
1892
-	.main_clk	= "func_48m_fclk",
1893
-	.prcm = {
1894
-		.omap4 = {
1895
-			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1896
-			.context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1897
-			.modulemode   = MODULEMODE_SWCTRL,
1898
-		},
1899
-	},
1900
-};
1901
-
1902
-/*
1903
- * 'mmc' class
1904
- * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1905
- */
1906
-
1907
-static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1908
-	.rev_offs	= 0x0000,
1909
-	.sysc_offs	= 0x0010,
1910
-	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1911
-			   SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1912
-			   SYSC_HAS_SOFTRESET),
1913
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1914
-			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1915
-			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1916
-	.sysc_fields	= &omap_hwmod_sysc_type2,
1917
-};
1918
-
1919
-static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1920
-	.name	= "mmc",
1921
-	.sysc	= &omap44xx_mmc_sysc,
1922
-};
1923
-
1924
-/* mmc1 */
1925
-static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1926
-	.flags	= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1927
-};
1928
-
1929
-static struct omap_hwmod omap44xx_mmc1_hwmod = {
1930
-	.name		= "mmc1",
1931
-	.class		= &omap44xx_mmc_hwmod_class,
1932
-	.clkdm_name	= "l3_init_clkdm",
1933
-	.main_clk	= "hsmmc1_fclk",
1934
-	.prcm = {
1935
-		.omap4 = {
1936
-			.clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1937
-			.context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1938
-			.modulemode   = MODULEMODE_SWCTRL,
1939
-		},
1940
-	},
1941
-	.dev_attr	= &mmc1_dev_attr,
1942
-};
1943
-
1944
-/* mmc2 */
1945
-static struct omap_hwmod omap44xx_mmc2_hwmod = {
1946
-	.name		= "mmc2",
1947
-	.class		= &omap44xx_mmc_hwmod_class,
1948
-	.clkdm_name	= "l3_init_clkdm",
1949
-	.main_clk	= "hsmmc2_fclk",
1950
-	.prcm = {
1951
-		.omap4 = {
1952
-			.clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1953
-			.context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1954
-			.modulemode   = MODULEMODE_SWCTRL,
1955
-		},
1956
-	},
1957
-};
1958
-
1959
-/* mmc3 */
1960
-static struct omap_hwmod omap44xx_mmc3_hwmod = {
1961
-	.name		= "mmc3",
1962
-	.class		= &omap44xx_mmc_hwmod_class,
1963
-	.clkdm_name	= "l4_per_clkdm",
1964
-	.main_clk	= "func_48m_fclk",
1965
-	.prcm = {
1966
-		.omap4 = {
1967
-			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
1968
-			.context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
1969
-			.modulemode   = MODULEMODE_SWCTRL,
1970
-		},
1971
-	},
1972
-};
1973
-
1974
-/* mmc4 */
1975
-static struct omap_hwmod omap44xx_mmc4_hwmod = {
1976
-	.name		= "mmc4",
1977
-	.class		= &omap44xx_mmc_hwmod_class,
1978
-	.clkdm_name	= "l4_per_clkdm",
1979
-	.main_clk	= "func_48m_fclk",
1980
-	.prcm = {
1981
-		.omap4 = {
1982
-			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
1983
-			.context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
1984
-			.modulemode   = MODULEMODE_SWCTRL,
1985
-		},
1986
-	},
1987
-};
1988
-
1989
-/* mmc5 */
1990
-static struct omap_hwmod omap44xx_mmc5_hwmod = {
1991
-	.name		= "mmc5",
1992
-	.class		= &omap44xx_mmc_hwmod_class,
1993
-	.clkdm_name	= "l4_per_clkdm",
1994
-	.main_clk	= "func_48m_fclk",
1995
-	.prcm = {
1996
-		.omap4 = {
1997
-			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
1998
-			.context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
1999
-			.modulemode   = MODULEMODE_SWCTRL,
2000
-		},
2001
-	},
2002
-};
2003
-
2004
-/*
2005
- * 'mmu' class
2006
- * The memory management unit performs virtual to physical address translation
2007
- * for its requestors.
2008
- */
2009
-
2010
-static struct omap_hwmod_class_sysconfig mmu_sysc = {
2011
-	.rev_offs	= 0x000,
2012
-	.sysc_offs	= 0x010,
2013
-	.syss_offs	= 0x014,
2014
-	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2015
-			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2016
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2017
-	.sysc_fields	= &omap_hwmod_sysc_type1,
2018
-};
2019
-
2020
-static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2021
-	.name = "mmu",
2022
-	.sysc = &mmu_sysc,
2023
-};
2024
-
2025
-/* mmu ipu */
2026
-
2027
-static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2028
-static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2029
-	{ .name = "mmu_cache", .rst_shift = 2 },
2030
-};
2031
-
2032
-/* l3_main_2 -> mmu_ipu */
2033
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2034
-	.master		= &omap44xx_l3_main_2_hwmod,
2035
-	.slave		= &omap44xx_mmu_ipu_hwmod,
2036
-	.clk		= "l3_div_ck",
2037
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2038
-};
2039
-
2040
-static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2041
-	.name		= "mmu_ipu",
2042
-	.class		= &omap44xx_mmu_hwmod_class,
2043
-	.clkdm_name	= "ducati_clkdm",
2044
-	.rst_lines	= omap44xx_mmu_ipu_resets,
2045
-	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2046
-	.main_clk	= "ducati_clk_mux_ck",
2047
-	.prcm = {
2048
-		.omap4 = {
2049
-			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2050
-			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2051
-			.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2052
-			.modulemode   = MODULEMODE_HWCTRL,
2053
-		},
2054
-	},
2055
-};
2056
-
2057
-/* mmu dsp */
2058
-
2059
-static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2060
-static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2061
-	{ .name = "mmu_cache", .rst_shift = 1 },
2062
-};
2063
-
2064
-/* l4_cfg -> dsp */
2065
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2066
-	.master		= &omap44xx_l4_cfg_hwmod,
2067
-	.slave		= &omap44xx_mmu_dsp_hwmod,
2068
-	.clk		= "l4_div_ck",
2069
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2070
-};
2071
-
2072
-static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2073
-	.name		= "mmu_dsp",
2074
-	.class		= &omap44xx_mmu_hwmod_class,
2075
-	.clkdm_name	= "tesla_clkdm",
2076
-	.rst_lines	= omap44xx_mmu_dsp_resets,
2077
-	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2078
-	.main_clk	= "dpll_iva_m4x2_ck",
2079
-	.prcm = {
2080
-		.omap4 = {
2081
-			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2082
-			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2083
-			.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2084
-			.modulemode   = MODULEMODE_HWCTRL,
2085
-		},
2086
-	},
2087
-};
2088
-
2089
-/*
2090477  * 'mpu' class
2091478  * mpu sub-system
2092479  */
....@@ -2132,51 +519,6 @@
2132519 	},
2133520 };
2134521 
2135
-/*
2136
- * 'ocp2scp' class
2137
- * bridge to transform ocp interface protocol to scp (serial control port)
2138
- * protocol
2139
- */
2140
-
2141
-static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2142
-	.rev_offs	= 0x0000,
2143
-	.sysc_offs	= 0x0010,
2144
-	.syss_offs	= 0x0014,
2145
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2146
-			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2147
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2148
-	.sysc_fields	= &omap_hwmod_sysc_type1,
2149
-};
2150
-
2151
-static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2152
-	.name	= "ocp2scp",
2153
-	.sysc	= &omap44xx_ocp2scp_sysc,
2154
-};
2155
-
2156
-/* ocp2scp_usb_phy */
2157
-static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2158
-	.name		= "ocp2scp_usb_phy",
2159
-	.class		= &omap44xx_ocp2scp_hwmod_class,
2160
-	.clkdm_name	= "l3_init_clkdm",
2161
-	/*
2162
-	 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2163
-	 * block as an "optional clock," and normally should never be
2164
-	 * specified as the main_clk for an OMAP IP block.  However it
2165
-	 * turns out that this clock is actually the main clock for
2166
-	 * the ocp2scp_usb_phy IP block:
2167
-	 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2168
-	 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2169
-	 * to be the best workaround.
2170
-	 */
2171
-	.main_clk	= "ocp2scp_usb_phy_phy_48m",
2172
-	.prcm = {
2173
-		.omap4 = {
2174
-			.clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2175
-			.context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2176
-			.modulemode   = MODULEMODE_HWCTRL,
2177
-		},
2178
-	},
2179
-};
2180522 
2181523 /*
2182524  * 'prcm' class
....@@ -2283,730 +625,6 @@
2283625 };
2284626 
2285627 /*
2286
- * 'slimbus' class
2287
- * bidirectional, multi-drop, multi-channel two-line serial interface between
2288
- * the device and external components
2289
- */
2290
-
2291
-static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2292
-	.rev_offs	= 0x0000,
2293
-	.sysc_offs	= 0x0010,
2294
-	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2295
-			   SYSC_HAS_SOFTRESET),
2296
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2297
-			   SIDLE_SMART_WKUP),
2298
-	.sysc_fields	= &omap_hwmod_sysc_type2,
2299
-};
2300
-
2301
-static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2302
-	.name	= "slimbus",
2303
-	.sysc	= &omap44xx_slimbus_sysc,
2304
-};
2305
-
2306
-/* slimbus1 */
2307
-static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2308
-	{ .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2309
-	{ .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2310
-	{ .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2311
-	{ .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2312
-};
2313
-
2314
-static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2315
-	.name		= "slimbus1",
2316
-	.class		= &omap44xx_slimbus_hwmod_class,
2317
-	.clkdm_name	= "abe_clkdm",
2318
-	.prcm = {
2319
-		.omap4 = {
2320
-			.clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2321
-			.context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2322
-			.modulemode   = MODULEMODE_SWCTRL,
2323
-		},
2324
-	},
2325
-	.opt_clks	= slimbus1_opt_clks,
2326
-	.opt_clks_cnt	= ARRAY_SIZE(slimbus1_opt_clks),
2327
-};
2328
-
2329
-/* slimbus2 */
2330
-static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2331
-	{ .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2332
-	{ .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2333
-	{ .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2334
-};
2335
-
2336
-static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2337
-	.name		= "slimbus2",
2338
-	.class		= &omap44xx_slimbus_hwmod_class,
2339
-	.clkdm_name	= "l4_per_clkdm",
2340
-	.prcm = {
2341
-		.omap4 = {
2342
-			.clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2343
-			.context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2344
-			.modulemode   = MODULEMODE_SWCTRL,
2345
-		},
2346
-	},
2347
-	.opt_clks	= slimbus2_opt_clks,
2348
-	.opt_clks_cnt	= ARRAY_SIZE(slimbus2_opt_clks),
2349
-};
2350
-
2351
-/*
2352
- * 'smartreflex' class
2353
- * smartreflex module (monitor silicon performance and outputs a measure of
2354
- * performance error)
2355
- */
2356
-
2357
-/* The IP is not compliant to type1 / type2 scheme */
2358
-static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2359
-	.rev_offs	= -ENODEV,
2360
-	.sysc_offs	= 0x0038,
2361
-	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2362
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2363
-			   SIDLE_SMART_WKUP),
2364
-	.sysc_fields	= &omap36xx_sr_sysc_fields,
2365
-};
2366
-
2367
-static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2368
-	.name	= "smartreflex",
2369
-	.sysc	= &omap44xx_smartreflex_sysc,
2370
-	.rev	= 2,
2371
-};
2372
-
2373
-/* smartreflex_core */
2374
-static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2375
-	.sensor_voltdm_name   = "core",
2376
-};
2377
-
2378
-static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2379
-	.name		= "smartreflex_core",
2380
-	.class		= &omap44xx_smartreflex_hwmod_class,
2381
-	.clkdm_name	= "l4_ao_clkdm",
2382
-
2383
-	.main_clk	= "smartreflex_core_fck",
2384
-	.prcm = {
2385
-		.omap4 = {
2386
-			.clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2387
-			.context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2388
-			.modulemode   = MODULEMODE_SWCTRL,
2389
-		},
2390
-	},
2391
-	.dev_attr	= &smartreflex_core_dev_attr,
2392
-};
2393
-
2394
-/* smartreflex_iva */
2395
-static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2396
-	.sensor_voltdm_name	= "iva",
2397
-};
2398
-
2399
-static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2400
-	.name		= "smartreflex_iva",
2401
-	.class		= &omap44xx_smartreflex_hwmod_class,
2402
-	.clkdm_name	= "l4_ao_clkdm",
2403
-	.main_clk	= "smartreflex_iva_fck",
2404
-	.prcm = {
2405
-		.omap4 = {
2406
-			.clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2407
-			.context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2408
-			.modulemode   = MODULEMODE_SWCTRL,
2409
-		},
2410
-	},
2411
-	.dev_attr	= &smartreflex_iva_dev_attr,
2412
-};
2413
-
2414
-/* smartreflex_mpu */
2415
-static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2416
-	.sensor_voltdm_name	= "mpu",
2417
-};
2418
-
2419
-static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2420
-	.name		= "smartreflex_mpu",
2421
-	.class		= &omap44xx_smartreflex_hwmod_class,
2422
-	.clkdm_name	= "l4_ao_clkdm",
2423
-	.main_clk	= "smartreflex_mpu_fck",
2424
-	.prcm = {
2425
-		.omap4 = {
2426
-			.clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2427
-			.context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2428
-			.modulemode   = MODULEMODE_SWCTRL,
2429
-		},
2430
-	},
2431
-	.dev_attr	= &smartreflex_mpu_dev_attr,
2432
-};
2433
-
2434
-/*
2435
- * 'spinlock' class
2436
- * spinlock provides hardware assistance for synchronizing the processes
2437
- * running on multiple processors
2438
- */
2439
-
2440
-static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2441
-	.rev_offs	= 0x0000,
2442
-	.sysc_offs	= 0x0010,
2443
-	.syss_offs	= 0x0014,
2444
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2445
-			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2446
-			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2447
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2448
-	.sysc_fields	= &omap_hwmod_sysc_type1,
2449
-};
2450
-
2451
-static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2452
-	.name	= "spinlock",
2453
-	.sysc	= &omap44xx_spinlock_sysc,
2454
-};
2455
-
2456
-/* spinlock */
2457
-static struct omap_hwmod omap44xx_spinlock_hwmod = {
2458
-	.name		= "spinlock",
2459
-	.class		= &omap44xx_spinlock_hwmod_class,
2460
-	.clkdm_name	= "l4_cfg_clkdm",
2461
-	.prcm = {
2462
-		.omap4 = {
2463
-			.clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2464
-			.context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2465
-		},
2466
-	},
2467
-};
2468
-
2469
-/*
2470
- * 'timer' class
2471
- * general purpose timer module with accurate 1ms tick
2472
- * This class contains several variants: ['timer_1ms', 'timer']
2473
- */
2474
-
2475
-static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2476
-	.rev_offs	= 0x0000,
2477
-	.sysc_offs	= 0x0010,
2478
-	.syss_offs	= 0x0014,
2479
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2480
-			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2481
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2482
-			   SYSS_HAS_RESET_STATUS),
2483
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2484
-	.sysc_fields	= &omap_hwmod_sysc_type1,
2485
-};
2486
-
2487
-static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2488
-	.name	= "timer",
2489
-	.sysc	= &omap44xx_timer_1ms_sysc,
2490
-};
2491
-
2492
-static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2493
-	.rev_offs	= 0x0000,
2494
-	.sysc_offs	= 0x0010,
2495
-	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2496
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2497
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2498
-			   SIDLE_SMART_WKUP),
2499
-	.sysc_fields	= &omap_hwmod_sysc_type2,
2500
-};
2501
-
2502
-static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2503
-	.name	= "timer",
2504
-	.sysc	= &omap44xx_timer_sysc,
2505
-};
2506
-
2507
-/* timer1 */
2508
-static struct omap_hwmod omap44xx_timer1_hwmod = {
2509
-	.name		= "timer1",
2510
-	.class		= &omap44xx_timer_1ms_hwmod_class,
2511
-	.clkdm_name	= "l4_wkup_clkdm",
2512
-	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
2513
-	.main_clk	= "dmt1_clk_mux",
2514
-	.prcm = {
2515
-		.omap4 = {
2516
-			.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2517
-			.context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2518
-			.modulemode   = MODULEMODE_SWCTRL,
2519
-		},
2520
-	},
2521
-};
2522
-
2523
-/* timer2 */
2524
-static struct omap_hwmod omap44xx_timer2_hwmod = {
2525
-	.name		= "timer2",
2526
-	.class		= &omap44xx_timer_1ms_hwmod_class,
2527
-	.clkdm_name	= "l4_per_clkdm",
2528
-	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
2529
-	.main_clk	= "cm2_dm2_mux",
2530
-	.prcm = {
2531
-		.omap4 = {
2532
-			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2533
-			.context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2534
-			.modulemode   = MODULEMODE_SWCTRL,
2535
-		},
2536
-	},
2537
-};
2538
-
2539
-/* timer3 */
2540
-static struct omap_hwmod omap44xx_timer3_hwmod = {
2541
-	.name		= "timer3",
2542
-	.class		= &omap44xx_timer_hwmod_class,
2543
-	.clkdm_name	= "l4_per_clkdm",
2544
-	.main_clk	= "cm2_dm3_mux",
2545
-	.prcm = {
2546
-		.omap4 = {
2547
-			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2548
-			.context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2549
-			.modulemode   = MODULEMODE_SWCTRL,
2550
-		},
2551
-	},
2552
-};
2553
-
2554
-/* timer4 */
2555
-static struct omap_hwmod omap44xx_timer4_hwmod = {
2556
-	.name		= "timer4",
2557
-	.class		= &omap44xx_timer_hwmod_class,
2558
-	.clkdm_name	= "l4_per_clkdm",
2559
-	.main_clk	= "cm2_dm4_mux",
2560
-	.prcm = {
2561
-		.omap4 = {
2562
-			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2563
-			.context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2564
-			.modulemode   = MODULEMODE_SWCTRL,
2565
-		},
2566
-	},
2567
-};
2568
-
2569
-/* timer5 */
2570
-static struct omap_hwmod omap44xx_timer5_hwmod = {
2571
-	.name		= "timer5",
2572
-	.class		= &omap44xx_timer_hwmod_class,
2573
-	.clkdm_name	= "abe_clkdm",
2574
-	.main_clk	= "timer5_sync_mux",
2575
-	.prcm = {
2576
-		.omap4 = {
2577
-			.clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2578
-			.context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2579
-			.modulemode   = MODULEMODE_SWCTRL,
2580
-		},
2581
-	},
2582
-};
2583
-
2584
-/* timer6 */
2585
-static struct omap_hwmod omap44xx_timer6_hwmod = {
2586
-	.name		= "timer6",
2587
-	.class		= &omap44xx_timer_hwmod_class,
2588
-	.clkdm_name	= "abe_clkdm",
2589
-	.main_clk	= "timer6_sync_mux",
2590
-	.prcm = {
2591
-		.omap4 = {
2592
-			.clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2593
-			.context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2594
-			.modulemode   = MODULEMODE_SWCTRL,
2595
-		},
2596
-	},
2597
-};
2598
-
2599
-/* timer7 */
2600
-static struct omap_hwmod omap44xx_timer7_hwmod = {
2601
-	.name		= "timer7",
2602
-	.class		= &omap44xx_timer_hwmod_class,
2603
-	.clkdm_name	= "abe_clkdm",
2604
-	.main_clk	= "timer7_sync_mux",
2605
-	.prcm = {
2606
-		.omap4 = {
2607
-			.clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2608
-			.context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2609
-			.modulemode   = MODULEMODE_SWCTRL,
2610
-		},
2611
-	},
2612
-};
2613
-
2614
-/* timer8 */
2615
-static struct omap_hwmod omap44xx_timer8_hwmod = {
2616
-	.name		= "timer8",
2617
-	.class		= &omap44xx_timer_hwmod_class,
2618
-	.clkdm_name	= "abe_clkdm",
2619
-	.main_clk	= "timer8_sync_mux",
2620
-	.prcm = {
2621
-		.omap4 = {
2622
-			.clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2623
-			.context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2624
-			.modulemode   = MODULEMODE_SWCTRL,
2625
-		},
2626
-	},
2627
-};
2628
-
2629
-/* timer9 */
2630
-static struct omap_hwmod omap44xx_timer9_hwmod = {
2631
-	.name		= "timer9",
2632
-	.class		= &omap44xx_timer_hwmod_class,
2633
-	.clkdm_name	= "l4_per_clkdm",
2634
-	.main_clk	= "cm2_dm9_mux",
2635
-	.prcm = {
2636
-		.omap4 = {
2637
-			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2638
-			.context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2639
-			.modulemode   = MODULEMODE_SWCTRL,
2640
-		},
2641
-	},
2642
-};
2643
-
2644
-/* timer10 */
2645
-static struct omap_hwmod omap44xx_timer10_hwmod = {
2646
-	.name		= "timer10",
2647
-	.class		= &omap44xx_timer_1ms_hwmod_class,
2648
-	.clkdm_name	= "l4_per_clkdm",
2649
-	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
2650
-	.main_clk	= "cm2_dm10_mux",
2651
-	.prcm = {
2652
-		.omap4 = {
2653
-			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2654
-			.context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2655
-			.modulemode   = MODULEMODE_SWCTRL,
2656
-		},
2657
-	},
2658
-};
2659
-
2660
-/* timer11 */
2661
-static struct omap_hwmod omap44xx_timer11_hwmod = {
2662
-	.name		= "timer11",
2663
-	.class		= &omap44xx_timer_hwmod_class,
2664
-	.clkdm_name	= "l4_per_clkdm",
2665
-	.main_clk	= "cm2_dm11_mux",
2666
-	.prcm = {
2667
-		.omap4 = {
2668
-			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2669
-			.context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2670
-			.modulemode   = MODULEMODE_SWCTRL,
2671
-		},
2672
-	},
2673
-};
2674
-
2675
-/*
2676
- * 'uart' class
2677
- * universal asynchronous receiver/transmitter (uart)
2678
- */
2679
-
2680
-static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2681
-	.rev_offs	= 0x0050,
2682
-	.sysc_offs	= 0x0054,
2683
-	.syss_offs	= 0x0058,
2684
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2685
-			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2686
-			   SYSS_HAS_RESET_STATUS),
2687
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2688
-			   SIDLE_SMART_WKUP),
2689
-	.sysc_fields	= &omap_hwmod_sysc_type1,
2690
-};
2691
-
2692
-static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2693
-	.name	= "uart",
2694
-	.sysc	= &omap44xx_uart_sysc,
2695
-};
2696
-
2697
-/* uart1 */
2698
-static struct omap_hwmod omap44xx_uart1_hwmod = {
2699
-	.name		= "uart1",
2700
-	.class		= &omap44xx_uart_hwmod_class,
2701
-	.clkdm_name	= "l4_per_clkdm",
2702
-	.flags		= HWMOD_SWSUP_SIDLE_ACT,
2703
-	.main_clk	= "func_48m_fclk",
2704
-	.prcm = {
2705
-		.omap4 = {
2706
-			.clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2707
-			.context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2708
-			.modulemode   = MODULEMODE_SWCTRL,
2709
-		},
2710
-	},
2711
-};
2712
-
2713
-/* uart2 */
2714
-static struct omap_hwmod omap44xx_uart2_hwmod = {
2715
-	.name		= "uart2",
2716
-	.class		= &omap44xx_uart_hwmod_class,
2717
-	.clkdm_name	= "l4_per_clkdm",
2718
-	.flags		= HWMOD_SWSUP_SIDLE_ACT,
2719
-	.main_clk	= "func_48m_fclk",
2720
-	.prcm = {
2721
-		.omap4 = {
2722
-			.clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2723
-			.context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2724
-			.modulemode   = MODULEMODE_SWCTRL,
2725
-		},
2726
-	},
2727
-};
2728
-
2729
-/* uart3 */
2730
-static struct omap_hwmod omap44xx_uart3_hwmod = {
2731
-	.name		= "uart3",
2732
-	.class		= &omap44xx_uart_hwmod_class,
2733
-	.clkdm_name	= "l4_per_clkdm",
2734
-	.flags		= DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2735
-	.main_clk	= "func_48m_fclk",
2736
-	.prcm = {
2737
-		.omap4 = {
2738
-			.clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2739
-			.context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2740
-			.modulemode   = MODULEMODE_SWCTRL,
2741
-		},
2742
-	},
2743
-};
2744
-
2745
-/* uart4 */
2746
-static struct omap_hwmod omap44xx_uart4_hwmod = {
2747
-	.name		= "uart4",
2748
-	.class		= &omap44xx_uart_hwmod_class,
2749
-	.clkdm_name	= "l4_per_clkdm",
2750
-	.flags		= DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2751
-	.main_clk	= "func_48m_fclk",
2752
-	.prcm = {
2753
-		.omap4 = {
2754
-			.clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2755
-			.context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2756
-			.modulemode   = MODULEMODE_SWCTRL,
2757
-		},
2758
-	},
2759
-};
2760
-
2761
-/*
2762
- * 'usb_host_fs' class
2763
- * full-speed usb host controller
2764
- */
2765
-
2766
-/* The IP is not compliant to type1 / type2 scheme */
2767
-static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2768
-	.rev_offs	= 0x0000,
2769
-	.sysc_offs	= 0x0210,
2770
-	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2771
-			   SYSC_HAS_SOFTRESET),
2772
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2773
-			   SIDLE_SMART_WKUP),
2774
-	.sysc_fields	= &omap_hwmod_sysc_type_usb_host_fs,
2775
-};
2776
-
2777
-static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2778
-	.name	= "usb_host_fs",
2779
-	.sysc	= &omap44xx_usb_host_fs_sysc,
2780
-};
2781
-
2782
-/* usb_host_fs */
2783
-static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2784
-	.name		= "usb_host_fs",
2785
-	.class		= &omap44xx_usb_host_fs_hwmod_class,
2786
-	.clkdm_name	= "l3_init_clkdm",
2787
-	.main_clk	= "usb_host_fs_fck",
2788
-	.prcm = {
2789
-		.omap4 = {
2790
-			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2791
-			.context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2792
-			.modulemode   = MODULEMODE_SWCTRL,
2793
-		},
2794
-	},
2795
-};
2796
-
2797
-/*
2798
- * 'usb_host_hs' class
2799
- * high-speed multi-port usb host controller
2800
- */
2801
-
2802
-static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2803
-	.rev_offs	= 0x0000,
2804
-	.sysc_offs	= 0x0010,
2805
-	.syss_offs	= 0x0014,
2806
-	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2807
-			   SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2808
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2809
-			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2810
-			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2811
-	.sysc_fields	= &omap_hwmod_sysc_type2,
2812
-};
2813
-
2814
-static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2815
-	.name	= "usb_host_hs",
2816
-	.sysc	= &omap44xx_usb_host_hs_sysc,
2817
-};
2818
-
2819
-/* usb_host_hs */
2820
-static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2821
-	.name		= "usb_host_hs",
2822
-	.class		= &omap44xx_usb_host_hs_hwmod_class,
2823
-	.clkdm_name	= "l3_init_clkdm",
2824
-	.main_clk	= "usb_host_hs_fck",
2825
-	.prcm = {
2826
-		.omap4 = {
2827
-			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2828
-			.context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2829
-			.modulemode   = MODULEMODE_SWCTRL,
2830
-		},
2831
-	},
2832
-
2833
-	/*
2834
-	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2835
-	 * id: i660
2836
-	 *
2837
-	 * Description:
2838
-	 * In the following configuration :
2839
-	 * - USBHOST module is set to smart-idle mode
2840
-	 * - PRCM asserts idle_req to the USBHOST module ( This typically
2841
-	 *   happens when the system is going to a low power mode : all ports
2842
-	 *   have been suspended, the master part of the USBHOST module has
2843
-	 *   entered the standby state, and SW has cut the functional clocks)
2844
-	 * - an USBHOST interrupt occurs before the module is able to answer
2845
-	 *   idle_ack, typically a remote wakeup IRQ.
2846
-	 * Then the USB HOST module will enter a deadlock situation where it
2847
-	 * is no more accessible nor functional.
2848
-	 *
2849
-	 * Workaround:
2850
-	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2851
-	 */
2852
-
2853
-	/*
2854
-	 * Errata: USB host EHCI may stall when entering smart-standby mode
2855
-	 * Id: i571
2856
-	 *
2857
-	 * Description:
2858
-	 * When the USBHOST module is set to smart-standby mode, and when it is
2859
-	 * ready to enter the standby state (i.e. all ports are suspended and
2860
-	 * all attached devices are in suspend mode), then it can wrongly assert
2861
-	 * the Mstandby signal too early while there are still some residual OCP
2862
-	 * transactions ongoing. If this condition occurs, the internal state
2863
-	 * machine may go to an undefined state and the USB link may be stuck
2864
-	 * upon the next resume.
2865
-	 *
2866
-	 * Workaround:
2867
-	 * Don't use smart standby; use only force standby,
2868
-	 * hence HWMOD_SWSUP_MSTANDBY
2869
-	 */
2870
-
2871
-	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2872
-};
2873
-
2874
-/*
2875
- * 'usb_otg_hs' class
2876
- * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2877
- */
2878
-
2879
-static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2880
-	.rev_offs	= 0x0400,
2881
-	.sysc_offs	= 0x0404,
2882
-	.syss_offs	= 0x0408,
2883
-	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2884
-			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2885
-			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2886
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2887
-			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2888
-			   MSTANDBY_SMART),
2889
-	.sysc_fields	= &omap_hwmod_sysc_type1,
2890
-};
2891
-
2892
-static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2893
-	.name	= "usb_otg_hs",
2894
-	.sysc	= &omap44xx_usb_otg_hs_sysc,
2895
-};
2896
-
2897
-/* usb_otg_hs */
2898
-static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
2899
-	{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
2900
-};
2901
-
2902
-static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
2903
-	.name		= "usb_otg_hs",
2904
-	.class		= &omap44xx_usb_otg_hs_hwmod_class,
2905
-	.clkdm_name	= "l3_init_clkdm",
2906
-	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2907
-	.main_clk	= "usb_otg_hs_ick",
2908
-	.prcm = {
2909
-		.omap4 = {
2910
-			.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
2911
-			.context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
2912
-			.modulemode   = MODULEMODE_HWCTRL,
2913
-		},
2914
-	},
2915
-	.opt_clks	= usb_otg_hs_opt_clks,
2916
-	.opt_clks_cnt	= ARRAY_SIZE(usb_otg_hs_opt_clks),
2917
-};
2918
-
2919
-/*
2920
- * 'usb_tll_hs' class
2921
- * usb_tll_hs module is the adapter on the usb_host_hs ports
2922
- */
2923
-
2924
-static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
2925
-	.rev_offs	= 0x0000,
2926
-	.sysc_offs	= 0x0010,
2927
-	.syss_offs	= 0x0014,
2928
-	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2929
-			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2930
-			   SYSC_HAS_AUTOIDLE),
2931
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2932
-	.sysc_fields	= &omap_hwmod_sysc_type1,
2933
-};
2934
-
2935
-static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
2936
-	.name	= "usb_tll_hs",
2937
-	.sysc	= &omap44xx_usb_tll_hs_sysc,
2938
-};
2939
-
2940
-static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
2941
-	.name		= "usb_tll_hs",
2942
-	.class		= &omap44xx_usb_tll_hs_hwmod_class,
2943
-	.clkdm_name	= "l3_init_clkdm",
2944
-	.main_clk	= "usb_tll_hs_ick",
2945
-	.prcm = {
2946
-		.omap4 = {
2947
-			.clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
2948
-			.context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
2949
-			.modulemode   = MODULEMODE_HWCTRL,
2950
-		},
2951
-	},
2952
-};
2953
-
2954
-/*
2955
- * 'wd_timer' class
2956
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
2957
- * overflow condition
2958
- */
2959
-
2960
-static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
2961
-	.rev_offs	= 0x0000,
2962
-	.sysc_offs	= 0x0010,
2963
-	.syss_offs	= 0x0014,
2964
-	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2965
-			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2966
-	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2967
-			   SIDLE_SMART_WKUP),
2968
-	.sysc_fields	= &omap_hwmod_sysc_type1,
2969
-};
2970
-
2971
-static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
2972
-	.name		= "wd_timer",
2973
-	.sysc		= &omap44xx_wd_timer_sysc,
2974
-	.pre_shutdown	= &omap2_wd_timer_disable,
2975
-	.reset		= &omap2_wd_timer_reset,
2976
-};
2977
-
2978
-/* wd_timer2 */
2979
-static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
2980
-	.name		= "wd_timer2",
2981
-	.class		= &omap44xx_wd_timer_hwmod_class,
2982
-	.clkdm_name	= "l4_wkup_clkdm",
2983
-	.main_clk	= "sys_32k_ck",
2984
-	.prcm = {
2985
-		.omap4 = {
2986
-			.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
2987
-			.context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
2988
-			.modulemode   = MODULEMODE_SWCTRL,
2989
-		},
2990
-	},
2991
-};
2992
-
2993
-/* wd_timer3 */
2994
-static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
2995
-	.name		= "wd_timer3",
2996
-	.class		= &omap44xx_wd_timer_hwmod_class,
2997
-	.clkdm_name	= "abe_clkdm",
2998
-	.main_clk	= "sys_32k_ck",
2999
-	.prcm = {
3000
-		.omap4 = {
3001
-			.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
3002
-			.context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
3003
-			.modulemode   = MODULEMODE_SWCTRL,
3004
-		},
3005
-	},
3006
-};
3007
-
3008
-
3009
-/*
3010628  * interfaces
3011629  */
3012630 
....@@ -3050,22 +668,6 @@
3050668 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3051669 };
3052670 
3053
-/* dsp -> l3_main_1 */
3054
-static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3055
-	.master		= &omap44xx_dsp_hwmod,
3056
-	.slave		= &omap44xx_l3_main_1_hwmod,
3057
-	.clk		= "l3_div_ck",
3058
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3059
-};
3060
-
3061
-/* dss -> l3_main_1 */
3062
-static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3063
-	.master		= &omap44xx_dss_hwmod,
3064
-	.slave		= &omap44xx_l3_main_1_hwmod,
3065
-	.clk		= "l3_div_ck",
3066
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3067
-};
3068
-
3069671 /* l3_main_2 -> l3_main_1 */
3070672 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3071673 	.master		= &omap44xx_l3_main_2_hwmod,
....@@ -3082,22 +684,6 @@
3082684 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3083685 };
3084686 
3085
-/* mmc1 -> l3_main_1 */
3086
-static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3087
-	.master		= &omap44xx_mmc1_hwmod,
3088
-	.slave		= &omap44xx_l3_main_1_hwmod,
3089
-	.clk		= "l3_div_ck",
3090
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3091
-};
3092
-
3093
-/* mmc2 -> l3_main_1 */
3094
-static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3095
-	.master		= &omap44xx_mmc2_hwmod,
3096
-	.slave		= &omap44xx_l3_main_1_hwmod,
3097
-	.clk		= "l3_div_ck",
3098
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3099
-};
3100
-
3101687 /* mpu -> l3_main_1 */
3102688 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3103689 	.master		= &omap44xx_mpu_hwmod,
....@@ -3111,46 +697,6 @@
3111697 	.master		= &omap44xx_debugss_hwmod,
3112698 	.slave		= &omap44xx_l3_main_2_hwmod,
3113699 	.clk		= "dbgclk_mux_ck",
3114
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3115
-};
3116
-
3117
-/* dma_system -> l3_main_2 */
3118
-static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3119
-	.master		= &omap44xx_dma_system_hwmod,
3120
-	.slave		= &omap44xx_l3_main_2_hwmod,
3121
-	.clk		= "l3_div_ck",
3122
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3123
-};
3124
-
3125
-/* fdif -> l3_main_2 */
3126
-static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3127
-	.master		= &omap44xx_fdif_hwmod,
3128
-	.slave		= &omap44xx_l3_main_2_hwmod,
3129
-	.clk		= "l3_div_ck",
3130
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3131
-};
3132
-
3133
-/* gpu -> l3_main_2 */
3134
-static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3135
-	.master		= &omap44xx_gpu_hwmod,
3136
-	.slave		= &omap44xx_l3_main_2_hwmod,
3137
-	.clk		= "l3_div_ck",
3138
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3139
-};
3140
-
3141
-/* hsi -> l3_main_2 */
3142
-static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3143
-	.master		= &omap44xx_hsi_hwmod,
3144
-	.slave		= &omap44xx_l3_main_2_hwmod,
3145
-	.clk		= "l3_div_ck",
3146
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3147
-};
3148
-
3149
-/* ipu -> l3_main_2 */
3150
-static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3151
-	.master		= &omap44xx_ipu_hwmod,
3152
-	.slave		= &omap44xx_l3_main_2_hwmod,
3153
-	.clk		= "l3_div_ck",
3154700 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3155701 };
3156702 
....@@ -3186,30 +732,6 @@
3186732 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3187733 };
3188734 
3189
-/* usb_host_fs -> l3_main_2 */
3190
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3191
-	.master		= &omap44xx_usb_host_fs_hwmod,
3192
-	.slave		= &omap44xx_l3_main_2_hwmod,
3193
-	.clk		= "l3_div_ck",
3194
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3195
-};
3196
-
3197
-/* usb_host_hs -> l3_main_2 */
3198
-static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3199
-	.master		= &omap44xx_usb_host_hs_hwmod,
3200
-	.slave		= &omap44xx_l3_main_2_hwmod,
3201
-	.clk		= "l3_div_ck",
3202
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3203
-};
3204
-
3205
-/* usb_otg_hs -> l3_main_2 */
3206
-static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3207
-	.master		= &omap44xx_usb_otg_hs_hwmod,
3208
-	.slave		= &omap44xx_l3_main_2_hwmod,
3209
-	.clk		= "l3_div_ck",
3210
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3211
-};
3212
-
3213735 /* l3_main_1 -> l3_main_3 */
3214736 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3215737 	.master		= &omap44xx_l3_main_1_hwmod,
....@@ -3231,38 +753,6 @@
3231753 	.master		= &omap44xx_l4_cfg_hwmod,
3232754 	.slave		= &omap44xx_l3_main_3_hwmod,
3233755 	.clk		= "l4_div_ck",
3234
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3235
-};
3236
-
3237
-/* aess -> l4_abe */
3238
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3239
-	.master		= &omap44xx_aess_hwmod,
3240
-	.slave		= &omap44xx_l4_abe_hwmod,
3241
-	.clk		= "ocp_abe_iclk",
3242
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3243
-};
3244
-
3245
-/* dsp -> l4_abe */
3246
-static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3247
-	.master		= &omap44xx_dsp_hwmod,
3248
-	.slave		= &omap44xx_l4_abe_hwmod,
3249
-	.clk		= "ocp_abe_iclk",
3250
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3251
-};
3252
-
3253
-/* l3_main_1 -> l4_abe */
3254
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3255
-	.master		= &omap44xx_l3_main_1_hwmod,
3256
-	.slave		= &omap44xx_l4_abe_hwmod,
3257
-	.clk		= "l3_div_ck",
3258
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3259
-};
3260
-
3261
-/* mpu -> l4_abe */
3262
-static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3263
-	.master		= &omap44xx_mpu_hwmod,
3264
-	.slave		= &omap44xx_l4_abe_hwmod,
3265
-	.clk		= "ocp_abe_iclk",
3266756 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3267757 };
3268758 
....@@ -3306,38 +796,6 @@
3306796 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3307797 };
3308798 
3309
-/* l4_abe -> aess */
3310
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3311
-	.master		= &omap44xx_l4_abe_hwmod,
3312
-	.slave		= &omap44xx_aess_hwmod,
3313
-	.clk		= "ocp_abe_iclk",
3314
-	.user		= OCP_USER_MPU,
3315
-};
3316
-
3317
-/* l4_abe -> aess (dma) */
3318
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3319
-	.master		= &omap44xx_l4_abe_hwmod,
3320
-	.slave		= &omap44xx_aess_hwmod,
3321
-	.clk		= "ocp_abe_iclk",
3322
-	.user		= OCP_USER_SDMA,
3323
-};
3324
-
3325
-/* l3_main_2 -> c2c */
3326
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3327
-	.master		= &omap44xx_l3_main_2_hwmod,
3328
-	.slave		= &omap44xx_c2c_hwmod,
3329
-	.clk		= "l3_div_ck",
3330
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3331
-};
3332
-
3333
-/* l4_wkup -> counter_32k */
3334
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3335
-	.master		= &omap44xx_l4_wkup_hwmod,
3336
-	.slave		= &omap44xx_counter_32k_hwmod,
3337
-	.clk		= "l4_wkup_clk_mux_ck",
3338
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3339
-};
3340
-
3341799 /* l4_cfg -> ctrl_module_core */
3342800 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3343801 	.master		= &omap44xx_l4_cfg_hwmod,
....@@ -3378,298 +836,10 @@
3378836 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3379837 };
3380838 
3381
-/* l4_cfg -> dma_system */
3382
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3383
-	.master		= &omap44xx_l4_cfg_hwmod,
3384
-	.slave		= &omap44xx_dma_system_hwmod,
3385
-	.clk		= "l4_div_ck",
3386
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3387
-};
3388
-
3389
-/* l4_abe -> dmic */
3390
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3391
-	.master		= &omap44xx_l4_abe_hwmod,
3392
-	.slave		= &omap44xx_dmic_hwmod,
3393
-	.clk		= "ocp_abe_iclk",
3394
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3395
-};
3396
-
3397
-/* dsp -> iva */
3398
-static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3399
-	.master		= &omap44xx_dsp_hwmod,
3400
-	.slave		= &omap44xx_iva_hwmod,
3401
-	.clk		= "dpll_iva_m5x2_ck",
3402
-	.user		= OCP_USER_DSP,
3403
-};
3404
-
3405
-/* dsp -> sl2if */
3406
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3407
-	.master		= &omap44xx_dsp_hwmod,
3408
-	.slave		= &omap44xx_sl2if_hwmod,
3409
-	.clk		= "dpll_iva_m5x2_ck",
3410
-	.user		= OCP_USER_DSP,
3411
-};
3412
-
3413
-/* l4_cfg -> dsp */
3414
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3415
-	.master		= &omap44xx_l4_cfg_hwmod,
3416
-	.slave		= &omap44xx_dsp_hwmod,
3417
-	.clk		= "l4_div_ck",
3418
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3419
-};
3420
-
3421
-/* l3_main_2 -> dss */
3422
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3423
-	.master		= &omap44xx_l3_main_2_hwmod,
3424
-	.slave		= &omap44xx_dss_hwmod,
3425
-	.clk		= "l3_div_ck",
3426
-	.user		= OCP_USER_SDMA,
3427
-};
3428
-
3429
-/* l4_per -> dss */
3430
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3431
-	.master		= &omap44xx_l4_per_hwmod,
3432
-	.slave		= &omap44xx_dss_hwmod,
3433
-	.clk		= "l4_div_ck",
3434
-	.user		= OCP_USER_MPU,
3435
-};
3436
-
3437
-/* l3_main_2 -> dss_dispc */
3438
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3439
-	.master		= &omap44xx_l3_main_2_hwmod,
3440
-	.slave		= &omap44xx_dss_dispc_hwmod,
3441
-	.clk		= "l3_div_ck",
3442
-	.user		= OCP_USER_SDMA,
3443
-};
3444
-
3445
-/* l4_per -> dss_dispc */
3446
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3447
-	.master		= &omap44xx_l4_per_hwmod,
3448
-	.slave		= &omap44xx_dss_dispc_hwmod,
3449
-	.clk		= "l4_div_ck",
3450
-	.user		= OCP_USER_MPU,
3451
-};
3452
-
3453
-/* l3_main_2 -> dss_dsi1 */
3454
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3455
-	.master		= &omap44xx_l3_main_2_hwmod,
3456
-	.slave		= &omap44xx_dss_dsi1_hwmod,
3457
-	.clk		= "l3_div_ck",
3458
-	.user		= OCP_USER_SDMA,
3459
-};
3460
-
3461
-/* l4_per -> dss_dsi1 */
3462
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3463
-	.master		= &omap44xx_l4_per_hwmod,
3464
-	.slave		= &omap44xx_dss_dsi1_hwmod,
3465
-	.clk		= "l4_div_ck",
3466
-	.user		= OCP_USER_MPU,
3467
-};
3468
-
3469
-/* l3_main_2 -> dss_dsi2 */
3470
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3471
-	.master		= &omap44xx_l3_main_2_hwmod,
3472
-	.slave		= &omap44xx_dss_dsi2_hwmod,
3473
-	.clk		= "l3_div_ck",
3474
-	.user		= OCP_USER_SDMA,
3475
-};
3476
-
3477
-/* l4_per -> dss_dsi2 */
3478
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3479
-	.master		= &omap44xx_l4_per_hwmod,
3480
-	.slave		= &omap44xx_dss_dsi2_hwmod,
3481
-	.clk		= "l4_div_ck",
3482
-	.user		= OCP_USER_MPU,
3483
-};
3484
-
3485
-/* l3_main_2 -> dss_hdmi */
3486
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3487
-	.master		= &omap44xx_l3_main_2_hwmod,
3488
-	.slave		= &omap44xx_dss_hdmi_hwmod,
3489
-	.clk		= "l3_div_ck",
3490
-	.user		= OCP_USER_SDMA,
3491
-};
3492
-
3493
-/* l4_per -> dss_hdmi */
3494
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3495
-	.master		= &omap44xx_l4_per_hwmod,
3496
-	.slave		= &omap44xx_dss_hdmi_hwmod,
3497
-	.clk		= "l4_div_ck",
3498
-	.user		= OCP_USER_MPU,
3499
-};
3500
-
3501
-/* l3_main_2 -> dss_rfbi */
3502
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3503
-	.master		= &omap44xx_l3_main_2_hwmod,
3504
-	.slave		= &omap44xx_dss_rfbi_hwmod,
3505
-	.clk		= "l3_div_ck",
3506
-	.user		= OCP_USER_SDMA,
3507
-};
3508
-
3509
-/* l4_per -> dss_rfbi */
3510
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3511
-	.master		= &omap44xx_l4_per_hwmod,
3512
-	.slave		= &omap44xx_dss_rfbi_hwmod,
3513
-	.clk		= "l4_div_ck",
3514
-	.user		= OCP_USER_MPU,
3515
-};
3516
-
3517
-/* l3_main_2 -> dss_venc */
3518
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3519
-	.master		= &omap44xx_l3_main_2_hwmod,
3520
-	.slave		= &omap44xx_dss_venc_hwmod,
3521
-	.clk		= "l3_div_ck",
3522
-	.user		= OCP_USER_SDMA,
3523
-};
3524
-
3525
-/* l4_per -> dss_venc */
3526
-static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3527
-	.master		= &omap44xx_l4_per_hwmod,
3528
-	.slave		= &omap44xx_dss_venc_hwmod,
3529
-	.clk		= "l4_div_ck",
3530
-	.user		= OCP_USER_MPU,
3531
-};
3532
-
3533
-/* l3_main_2 -> sham */
3534
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
3535
-	.master		= &omap44xx_l3_main_2_hwmod,
3536
-	.slave		= &omap44xx_sha0_hwmod,
3537
-	.clk		= "l3_div_ck",
3538
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3539
-};
3540
-
3541
-/* l4_per -> elm */
3542
-static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3543
-	.master		= &omap44xx_l4_per_hwmod,
3544
-	.slave		= &omap44xx_elm_hwmod,
3545
-	.clk		= "l4_div_ck",
3546
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3547
-};
3548
-
3549
-/* l4_cfg -> fdif */
3550
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3551
-	.master		= &omap44xx_l4_cfg_hwmod,
3552
-	.slave		= &omap44xx_fdif_hwmod,
3553
-	.clk		= "l4_div_ck",
3554
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3555
-};
3556
-
3557
-/* l4_wkup -> gpio1 */
3558
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3559
-	.master		= &omap44xx_l4_wkup_hwmod,
3560
-	.slave		= &omap44xx_gpio1_hwmod,
3561
-	.clk		= "l4_wkup_clk_mux_ck",
3562
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3563
-};
3564
-
3565
-/* l4_per -> gpio2 */
3566
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3567
-	.master		= &omap44xx_l4_per_hwmod,
3568
-	.slave		= &omap44xx_gpio2_hwmod,
3569
-	.clk		= "l4_div_ck",
3570
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3571
-};
3572
-
3573
-/* l4_per -> gpio3 */
3574
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3575
-	.master		= &omap44xx_l4_per_hwmod,
3576
-	.slave		= &omap44xx_gpio3_hwmod,
3577
-	.clk		= "l4_div_ck",
3578
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3579
-};
3580
-
3581
-/* l4_per -> gpio4 */
3582
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3583
-	.master		= &omap44xx_l4_per_hwmod,
3584
-	.slave		= &omap44xx_gpio4_hwmod,
3585
-	.clk		= "l4_div_ck",
3586
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3587
-};
3588
-
3589
-/* l4_per -> gpio5 */
3590
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3591
-	.master		= &omap44xx_l4_per_hwmod,
3592
-	.slave		= &omap44xx_gpio5_hwmod,
3593
-	.clk		= "l4_div_ck",
3594
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3595
-};
3596
-
3597
-/* l4_per -> gpio6 */
3598
-static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3599
-	.master		= &omap44xx_l4_per_hwmod,
3600
-	.slave		= &omap44xx_gpio6_hwmod,
3601
-	.clk		= "l4_div_ck",
3602
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3603
-};
3604
-
3605839 /* l3_main_2 -> gpmc */
3606840 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
3607841 	.master		= &omap44xx_l3_main_2_hwmod,
3608842 	.slave		= &omap44xx_gpmc_hwmod,
3609
-	.clk		= "l3_div_ck",
3610
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3611
-};
3612
-
3613
-/* l3_main_2 -> gpu */
3614
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
3615
-	.master		= &omap44xx_l3_main_2_hwmod,
3616
-	.slave		= &omap44xx_gpu_hwmod,
3617
-	.clk		= "l3_div_ck",
3618
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3619
-};
3620
-
3621
-/* l4_per -> hdq1w */
3622
-static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
3623
-	.master		= &omap44xx_l4_per_hwmod,
3624
-	.slave		= &omap44xx_hdq1w_hwmod,
3625
-	.clk		= "l4_div_ck",
3626
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3627
-};
3628
-
3629
-/* l4_cfg -> hsi */
3630
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
3631
-	.master		= &omap44xx_l4_cfg_hwmod,
3632
-	.slave		= &omap44xx_hsi_hwmod,
3633
-	.clk		= "l4_div_ck",
3634
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3635
-};
3636
-
3637
-/* l4_per -> i2c1 */
3638
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
3639
-	.master		= &omap44xx_l4_per_hwmod,
3640
-	.slave		= &omap44xx_i2c1_hwmod,
3641
-	.clk		= "l4_div_ck",
3642
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3643
-};
3644
-
3645
-/* l4_per -> i2c2 */
3646
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
3647
-	.master		= &omap44xx_l4_per_hwmod,
3648
-	.slave		= &omap44xx_i2c2_hwmod,
3649
-	.clk		= "l4_div_ck",
3650
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3651
-};
3652
-
3653
-/* l4_per -> i2c3 */
3654
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
3655
-	.master		= &omap44xx_l4_per_hwmod,
3656
-	.slave		= &omap44xx_i2c3_hwmod,
3657
-	.clk		= "l4_div_ck",
3658
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3659
-};
3660
-
3661
-/* l4_per -> i2c4 */
3662
-static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
3663
-	.master		= &omap44xx_l4_per_hwmod,
3664
-	.slave		= &omap44xx_i2c4_hwmod,
3665
-	.clk		= "l4_div_ck",
3666
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3667
-};
3668
-
3669
-/* l3_main_2 -> ipu */
3670
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
3671
-	.master		= &omap44xx_l3_main_2_hwmod,
3672
-	.slave		= &omap44xx_ipu_hwmod,
3673843 	.clk		= "l3_div_ck",
3674844 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3675845 };
....@@ -3698,163 +868,11 @@
3698868 	.user		= OCP_USER_MPU,
3699869 };
3700870 
3701
-/* l4_wkup -> kbd */
3702
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
3703
-	.master		= &omap44xx_l4_wkup_hwmod,
3704
-	.slave		= &omap44xx_kbd_hwmod,
3705
-	.clk		= "l4_wkup_clk_mux_ck",
3706
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3707
-};
3708
-
3709
-/* l4_cfg -> mailbox */
3710
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
3711
-	.master		= &omap44xx_l4_cfg_hwmod,
3712
-	.slave		= &omap44xx_mailbox_hwmod,
3713
-	.clk		= "l4_div_ck",
3714
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3715
-};
3716
-
3717
-/* l4_abe -> mcasp */
3718
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
3719
-	.master		= &omap44xx_l4_abe_hwmod,
3720
-	.slave		= &omap44xx_mcasp_hwmod,
3721
-	.clk		= "ocp_abe_iclk",
3722
-	.user		= OCP_USER_MPU,
3723
-};
3724
-
3725
-/* l4_abe -> mcasp (dma) */
3726
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
3727
-	.master		= &omap44xx_l4_abe_hwmod,
3728
-	.slave		= &omap44xx_mcasp_hwmod,
3729
-	.clk		= "ocp_abe_iclk",
3730
-	.user		= OCP_USER_SDMA,
3731
-};
3732
-
3733
-/* l4_abe -> mcbsp1 */
3734
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
3735
-	.master		= &omap44xx_l4_abe_hwmod,
3736
-	.slave		= &omap44xx_mcbsp1_hwmod,
3737
-	.clk		= "ocp_abe_iclk",
3738
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3739
-};
3740
-
3741
-/* l4_abe -> mcbsp2 */
3742
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3743
-	.master		= &omap44xx_l4_abe_hwmod,
3744
-	.slave		= &omap44xx_mcbsp2_hwmod,
3745
-	.clk		= "ocp_abe_iclk",
3746
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3747
-};
3748
-
3749
-/* l4_abe -> mcbsp3 */
3750
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3751
-	.master		= &omap44xx_l4_abe_hwmod,
3752
-	.slave		= &omap44xx_mcbsp3_hwmod,
3753
-	.clk		= "ocp_abe_iclk",
3754
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3755
-};
3756
-
3757
-/* l4_per -> mcbsp4 */
3758
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3759
-	.master		= &omap44xx_l4_per_hwmod,
3760
-	.slave		= &omap44xx_mcbsp4_hwmod,
3761
-	.clk		= "l4_div_ck",
3762
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3763
-};
3764
-
3765
-/* l4_abe -> mcpdm */
3766
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3767
-	.master		= &omap44xx_l4_abe_hwmod,
3768
-	.slave		= &omap44xx_mcpdm_hwmod,
3769
-	.clk		= "ocp_abe_iclk",
3770
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3771
-};
3772
-
3773
-/* l4_per -> mcspi1 */
3774
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3775
-	.master		= &omap44xx_l4_per_hwmod,
3776
-	.slave		= &omap44xx_mcspi1_hwmod,
3777
-	.clk		= "l4_div_ck",
3778
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3779
-};
3780
-
3781
-/* l4_per -> mcspi2 */
3782
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3783
-	.master		= &omap44xx_l4_per_hwmod,
3784
-	.slave		= &omap44xx_mcspi2_hwmod,
3785
-	.clk		= "l4_div_ck",
3786
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3787
-};
3788
-
3789
-/* l4_per -> mcspi3 */
3790
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3791
-	.master		= &omap44xx_l4_per_hwmod,
3792
-	.slave		= &omap44xx_mcspi3_hwmod,
3793
-	.clk		= "l4_div_ck",
3794
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3795
-};
3796
-
3797
-/* l4_per -> mcspi4 */
3798
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3799
-	.master		= &omap44xx_l4_per_hwmod,
3800
-	.slave		= &omap44xx_mcspi4_hwmod,
3801
-	.clk		= "l4_div_ck",
3802
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3803
-};
3804
-
3805
-/* l4_per -> mmc1 */
3806
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3807
-	.master		= &omap44xx_l4_per_hwmod,
3808
-	.slave		= &omap44xx_mmc1_hwmod,
3809
-	.clk		= "l4_div_ck",
3810
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3811
-};
3812
-
3813
-/* l4_per -> mmc2 */
3814
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3815
-	.master		= &omap44xx_l4_per_hwmod,
3816
-	.slave		= &omap44xx_mmc2_hwmod,
3817
-	.clk		= "l4_div_ck",
3818
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3819
-};
3820
-
3821
-/* l4_per -> mmc3 */
3822
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3823
-	.master		= &omap44xx_l4_per_hwmod,
3824
-	.slave		= &omap44xx_mmc3_hwmod,
3825
-	.clk		= "l4_div_ck",
3826
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3827
-};
3828
-
3829
-/* l4_per -> mmc4 */
3830
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3831
-	.master		= &omap44xx_l4_per_hwmod,
3832
-	.slave		= &omap44xx_mmc4_hwmod,
3833
-	.clk		= "l4_div_ck",
3834
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3835
-};
3836
-
3837
-/* l4_per -> mmc5 */
3838
-static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3839
-	.master		= &omap44xx_l4_per_hwmod,
3840
-	.slave		= &omap44xx_mmc5_hwmod,
3841
-	.clk		= "l4_div_ck",
3842
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3843
-};
3844
-
3845871 /* l3_main_2 -> ocmc_ram */
3846872 static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
3847873 	.master		= &omap44xx_l3_main_2_hwmod,
3848874 	.slave		= &omap44xx_ocmc_ram_hwmod,
3849875 	.clk		= "l3_div_ck",
3850
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3851
-};
3852
-
3853
-/* l4_cfg -> ocp2scp_usb_phy */
3854
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
3855
-	.master		= &omap44xx_l4_cfg_hwmod,
3856
-	.slave		= &omap44xx_ocp2scp_usb_phy_hwmod,
3857
-	.clk		= "l4_div_ck",
3858876 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3859877 };
3860878 
....@@ -3906,238 +924,6 @@
3906924 	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3907925 };
3908926 
3909
-/* l4_abe -> slimbus1 */
3910
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
3911
-	.master		= &omap44xx_l4_abe_hwmod,
3912
-	.slave		= &omap44xx_slimbus1_hwmod,
3913
-	.clk		= "ocp_abe_iclk",
3914
-	.user		= OCP_USER_MPU,
3915
-};
3916
-
3917
-/* l4_abe -> slimbus1 (dma) */
3918
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
3919
-	.master		= &omap44xx_l4_abe_hwmod,
3920
-	.slave		= &omap44xx_slimbus1_hwmod,
3921
-	.clk		= "ocp_abe_iclk",
3922
-	.user		= OCP_USER_SDMA,
3923
-};
3924
-
3925
-/* l4_per -> slimbus2 */
3926
-static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
3927
-	.master		= &omap44xx_l4_per_hwmod,
3928
-	.slave		= &omap44xx_slimbus2_hwmod,
3929
-	.clk		= "l4_div_ck",
3930
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3931
-};
3932
-
3933
-/* l4_cfg -> smartreflex_core */
3934
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3935
-	.master		= &omap44xx_l4_cfg_hwmod,
3936
-	.slave		= &omap44xx_smartreflex_core_hwmod,
3937
-	.clk		= "l4_div_ck",
3938
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3939
-};
3940
-
3941
-/* l4_cfg -> smartreflex_iva */
3942
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3943
-	.master		= &omap44xx_l4_cfg_hwmod,
3944
-	.slave		= &omap44xx_smartreflex_iva_hwmod,
3945
-	.clk		= "l4_div_ck",
3946
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3947
-};
3948
-
3949
-/* l4_cfg -> smartreflex_mpu */
3950
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3951
-	.master		= &omap44xx_l4_cfg_hwmod,
3952
-	.slave		= &omap44xx_smartreflex_mpu_hwmod,
3953
-	.clk		= "l4_div_ck",
3954
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3955
-};
3956
-
3957
-/* l4_cfg -> spinlock */
3958
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3959
-	.master		= &omap44xx_l4_cfg_hwmod,
3960
-	.slave		= &omap44xx_spinlock_hwmod,
3961
-	.clk		= "l4_div_ck",
3962
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3963
-};
3964
-
3965
-/* l4_wkup -> timer1 */
3966
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3967
-	.master		= &omap44xx_l4_wkup_hwmod,
3968
-	.slave		= &omap44xx_timer1_hwmod,
3969
-	.clk		= "l4_wkup_clk_mux_ck",
3970
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3971
-};
3972
-
3973
-/* l4_per -> timer2 */
3974
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
3975
-	.master		= &omap44xx_l4_per_hwmod,
3976
-	.slave		= &omap44xx_timer2_hwmod,
3977
-	.clk		= "l4_div_ck",
3978
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3979
-};
3980
-
3981
-/* l4_per -> timer3 */
3982
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
3983
-	.master		= &omap44xx_l4_per_hwmod,
3984
-	.slave		= &omap44xx_timer3_hwmod,
3985
-	.clk		= "l4_div_ck",
3986
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3987
-};
3988
-
3989
-/* l4_per -> timer4 */
3990
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
3991
-	.master		= &omap44xx_l4_per_hwmod,
3992
-	.slave		= &omap44xx_timer4_hwmod,
3993
-	.clk		= "l4_div_ck",
3994
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3995
-};
3996
-
3997
-/* l4_abe -> timer5 */
3998
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
3999
-	.master		= &omap44xx_l4_abe_hwmod,
4000
-	.slave		= &omap44xx_timer5_hwmod,
4001
-	.clk		= "ocp_abe_iclk",
4002
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4003
-};
4004
-
4005
-/* l4_abe -> timer6 */
4006
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4007
-	.master		= &omap44xx_l4_abe_hwmod,
4008
-	.slave		= &omap44xx_timer6_hwmod,
4009
-	.clk		= "ocp_abe_iclk",
4010
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4011
-};
4012
-
4013
-/* l4_abe -> timer7 */
4014
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4015
-	.master		= &omap44xx_l4_abe_hwmod,
4016
-	.slave		= &omap44xx_timer7_hwmod,
4017
-	.clk		= "ocp_abe_iclk",
4018
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4019
-};
4020
-
4021
-/* l4_abe -> timer8 */
4022
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4023
-	.master		= &omap44xx_l4_abe_hwmod,
4024
-	.slave		= &omap44xx_timer8_hwmod,
4025
-	.clk		= "ocp_abe_iclk",
4026
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4027
-};
4028
-
4029
-/* l4_per -> timer9 */
4030
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4031
-	.master		= &omap44xx_l4_per_hwmod,
4032
-	.slave		= &omap44xx_timer9_hwmod,
4033
-	.clk		= "l4_div_ck",
4034
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4035
-};
4036
-
4037
-/* l4_per -> timer10 */
4038
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4039
-	.master		= &omap44xx_l4_per_hwmod,
4040
-	.slave		= &omap44xx_timer10_hwmod,
4041
-	.clk		= "l4_div_ck",
4042
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4043
-};
4044
-
4045
-/* l4_per -> timer11 */
4046
-static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4047
-	.master		= &omap44xx_l4_per_hwmod,
4048
-	.slave		= &omap44xx_timer11_hwmod,
4049
-	.clk		= "l4_div_ck",
4050
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4051
-};
4052
-
4053
-/* l4_per -> uart1 */
4054
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4055
-	.master		= &omap44xx_l4_per_hwmod,
4056
-	.slave		= &omap44xx_uart1_hwmod,
4057
-	.clk		= "l4_div_ck",
4058
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4059
-};
4060
-
4061
-/* l4_per -> uart2 */
4062
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4063
-	.master		= &omap44xx_l4_per_hwmod,
4064
-	.slave		= &omap44xx_uart2_hwmod,
4065
-	.clk		= "l4_div_ck",
4066
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4067
-};
4068
-
4069
-/* l4_per -> uart3 */
4070
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4071
-	.master		= &omap44xx_l4_per_hwmod,
4072
-	.slave		= &omap44xx_uart3_hwmod,
4073
-	.clk		= "l4_div_ck",
4074
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4075
-};
4076
-
4077
-/* l4_per -> uart4 */
4078
-static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4079
-	.master		= &omap44xx_l4_per_hwmod,
4080
-	.slave		= &omap44xx_uart4_hwmod,
4081
-	.clk		= "l4_div_ck",
4082
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4083
-};
4084
-
4085
-/* l4_cfg -> usb_host_fs */
4086
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4087
-	.master		= &omap44xx_l4_cfg_hwmod,
4088
-	.slave		= &omap44xx_usb_host_fs_hwmod,
4089
-	.clk		= "l4_div_ck",
4090
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4091
-};
4092
-
4093
-/* l4_cfg -> usb_host_hs */
4094
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4095
-	.master		= &omap44xx_l4_cfg_hwmod,
4096
-	.slave		= &omap44xx_usb_host_hs_hwmod,
4097
-	.clk		= "l4_div_ck",
4098
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4099
-};
4100
-
4101
-/* l4_cfg -> usb_otg_hs */
4102
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4103
-	.master		= &omap44xx_l4_cfg_hwmod,
4104
-	.slave		= &omap44xx_usb_otg_hs_hwmod,
4105
-	.clk		= "l4_div_ck",
4106
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4107
-};
4108
-
4109
-/* l4_cfg -> usb_tll_hs */
4110
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4111
-	.master		= &omap44xx_l4_cfg_hwmod,
4112
-	.slave		= &omap44xx_usb_tll_hs_hwmod,
4113
-	.clk		= "l4_div_ck",
4114
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4115
-};
4116
-
4117
-/* l4_wkup -> wd_timer2 */
4118
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4119
-	.master		= &omap44xx_l4_wkup_hwmod,
4120
-	.slave		= &omap44xx_wd_timer2_hwmod,
4121
-	.clk		= "l4_wkup_clk_mux_ck",
4122
-	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4123
-};
4124
-
4125
-/* l4_abe -> wd_timer3 */
4126
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4127
-	.master		= &omap44xx_l4_abe_hwmod,
4128
-	.slave		= &omap44xx_wd_timer3_hwmod,
4129
-	.clk		= "ocp_abe_iclk",
4130
-	.user		= OCP_USER_MPU,
4131
-};
4132
-
4133
-/* l4_abe -> wd_timer3 (dma) */
4134
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4135
-	.master		= &omap44xx_l4_abe_hwmod,
4136
-	.slave		= &omap44xx_wd_timer3_hwmod,
4137
-	.clk		= "ocp_abe_iclk",
4138
-	.user		= OCP_USER_SDMA,
4139
-};
4140
-
4141927 /* mpu -> emif1 */
4142928 static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4143929 	.master		= &omap44xx_mpu_hwmod,
....@@ -4160,149 +946,40 @@
4160946 	&omap44xx_iva__l3_instr,
4161947 	&omap44xx_l3_main_3__l3_instr,
4162948 	&omap44xx_ocp_wp_noc__l3_instr,
4163
-	&omap44xx_dsp__l3_main_1,
4164
-	&omap44xx_dss__l3_main_1,
4165949 	&omap44xx_l3_main_2__l3_main_1,
4166950 	&omap44xx_l4_cfg__l3_main_1,
4167
-	&omap44xx_mmc1__l3_main_1,
4168
-	&omap44xx_mmc2__l3_main_1,
4169951 	&omap44xx_mpu__l3_main_1,
4170952 	&omap44xx_debugss__l3_main_2,
4171
-	&omap44xx_dma_system__l3_main_2,
4172
-	&omap44xx_fdif__l3_main_2,
4173
-	&omap44xx_gpu__l3_main_2,
4174
-	&omap44xx_hsi__l3_main_2,
4175
-	&omap44xx_ipu__l3_main_2,
4176953 	&omap44xx_iss__l3_main_2,
4177954 	&omap44xx_iva__l3_main_2,
4178955 	&omap44xx_l3_main_1__l3_main_2,
4179956 	&omap44xx_l4_cfg__l3_main_2,
4180
-	/* &omap44xx_usb_host_fs__l3_main_2, */
4181
-	&omap44xx_usb_host_hs__l3_main_2,
4182
-	&omap44xx_usb_otg_hs__l3_main_2,
4183957 	&omap44xx_l3_main_1__l3_main_3,
4184958 	&omap44xx_l3_main_2__l3_main_3,
4185959 	&omap44xx_l4_cfg__l3_main_3,
4186
-	&omap44xx_aess__l4_abe,
4187
-	&omap44xx_dsp__l4_abe,
4188
-	&omap44xx_l3_main_1__l4_abe,
4189
-	&omap44xx_mpu__l4_abe,
4190960 	&omap44xx_l3_main_1__l4_cfg,
4191961 	&omap44xx_l3_main_2__l4_per,
4192962 	&omap44xx_l4_cfg__l4_wkup,
4193963 	&omap44xx_mpu__mpu_private,
4194964 	&omap44xx_l4_cfg__ocp_wp_noc,
4195
-	&omap44xx_l4_abe__aess,
4196
-	&omap44xx_l4_abe__aess_dma,
4197
-	&omap44xx_l3_main_2__c2c,
4198
-	&omap44xx_l4_wkup__counter_32k,
4199965 	&omap44xx_l4_cfg__ctrl_module_core,
4200966 	&omap44xx_l4_cfg__ctrl_module_pad_core,
4201967 	&omap44xx_l4_wkup__ctrl_module_wkup,
4202968 	&omap44xx_l4_wkup__ctrl_module_pad_wkup,
4203969 	&omap44xx_l3_instr__debugss,
4204
-	&omap44xx_l4_cfg__dma_system,
4205
-	&omap44xx_l4_abe__dmic,
4206
-	&omap44xx_dsp__iva,
4207
-	/* &omap44xx_dsp__sl2if, */
4208
-	&omap44xx_l4_cfg__dsp,
4209
-	&omap44xx_l3_main_2__dss,
4210
-	&omap44xx_l4_per__dss,
4211
-	&omap44xx_l3_main_2__dss_dispc,
4212
-	&omap44xx_l4_per__dss_dispc,
4213
-	&omap44xx_l3_main_2__dss_dsi1,
4214
-	&omap44xx_l4_per__dss_dsi1,
4215
-	&omap44xx_l3_main_2__dss_dsi2,
4216
-	&omap44xx_l4_per__dss_dsi2,
4217
-	&omap44xx_l3_main_2__dss_hdmi,
4218
-	&omap44xx_l4_per__dss_hdmi,
4219
-	&omap44xx_l3_main_2__dss_rfbi,
4220
-	&omap44xx_l4_per__dss_rfbi,
4221
-	&omap44xx_l3_main_2__dss_venc,
4222
-	&omap44xx_l4_per__dss_venc,
4223
-	&omap44xx_l4_per__elm,
4224
-	&omap44xx_l4_cfg__fdif,
4225
-	&omap44xx_l4_wkup__gpio1,
4226
-	&omap44xx_l4_per__gpio2,
4227
-	&omap44xx_l4_per__gpio3,
4228
-	&omap44xx_l4_per__gpio4,
4229
-	&omap44xx_l4_per__gpio5,
4230
-	&omap44xx_l4_per__gpio6,
4231970 	&omap44xx_l3_main_2__gpmc,
4232
-	&omap44xx_l3_main_2__gpu,
4233
-	&omap44xx_l4_per__hdq1w,
4234
-	&omap44xx_l4_cfg__hsi,
4235
-	&omap44xx_l4_per__i2c1,
4236
-	&omap44xx_l4_per__i2c2,
4237
-	&omap44xx_l4_per__i2c3,
4238
-	&omap44xx_l4_per__i2c4,
4239
-	&omap44xx_l3_main_2__ipu,
4240971 	&omap44xx_l3_main_2__iss,
4241972 	/* &omap44xx_iva__sl2if, */
4242973 	&omap44xx_l3_main_2__iva,
4243
-	&omap44xx_l4_wkup__kbd,
4244
-	&omap44xx_l4_cfg__mailbox,
4245
-	&omap44xx_l4_abe__mcasp,
4246
-	&omap44xx_l4_abe__mcasp_dma,
4247
-	&omap44xx_l4_abe__mcbsp1,
4248
-	&omap44xx_l4_abe__mcbsp2,
4249
-	&omap44xx_l4_abe__mcbsp3,
4250
-	&omap44xx_l4_per__mcbsp4,
4251
-	&omap44xx_l4_abe__mcpdm,
4252
-	&omap44xx_l4_per__mcspi1,
4253
-	&omap44xx_l4_per__mcspi2,
4254
-	&omap44xx_l4_per__mcspi3,
4255
-	&omap44xx_l4_per__mcspi4,
4256
-	&omap44xx_l4_per__mmc1,
4257
-	&omap44xx_l4_per__mmc2,
4258
-	&omap44xx_l4_per__mmc3,
4259
-	&omap44xx_l4_per__mmc4,
4260
-	&omap44xx_l4_per__mmc5,
4261
-	&omap44xx_l3_main_2__mmu_ipu,
4262
-	&omap44xx_l4_cfg__mmu_dsp,
4263974 	&omap44xx_l3_main_2__ocmc_ram,
4264
-	&omap44xx_l4_cfg__ocp2scp_usb_phy,
4265975 	&omap44xx_mpu_private__prcm_mpu,
4266976 	&omap44xx_l4_wkup__cm_core_aon,
4267977 	&omap44xx_l4_cfg__cm_core,
4268978 	&omap44xx_l4_wkup__prm,
4269979 	&omap44xx_l4_wkup__scrm,
4270980 	/* &omap44xx_l3_main_2__sl2if, */
4271
-	&omap44xx_l4_abe__slimbus1,
4272
-	&omap44xx_l4_abe__slimbus1_dma,
4273
-	&omap44xx_l4_per__slimbus2,
4274
-	&omap44xx_l4_cfg__smartreflex_core,
4275
-	&omap44xx_l4_cfg__smartreflex_iva,
4276
-	&omap44xx_l4_cfg__smartreflex_mpu,
4277
-	&omap44xx_l4_cfg__spinlock,
4278
-	&omap44xx_l4_wkup__timer1,
4279
-	&omap44xx_l4_per__timer2,
4280
-	&omap44xx_l4_per__timer3,
4281
-	&omap44xx_l4_per__timer4,
4282
-	&omap44xx_l4_abe__timer5,
4283
-	&omap44xx_l4_abe__timer6,
4284
-	&omap44xx_l4_abe__timer7,
4285
-	&omap44xx_l4_abe__timer8,
4286
-	&omap44xx_l4_per__timer9,
4287
-	&omap44xx_l4_per__timer10,
4288
-	&omap44xx_l4_per__timer11,
4289
-	&omap44xx_l4_per__uart1,
4290
-	&omap44xx_l4_per__uart2,
4291
-	&omap44xx_l4_per__uart3,
4292
-	&omap44xx_l4_per__uart4,
4293
-	/* &omap44xx_l4_cfg__usb_host_fs, */
4294
-	&omap44xx_l4_cfg__usb_host_hs,
4295
-	&omap44xx_l4_cfg__usb_otg_hs,
4296
-	&omap44xx_l4_cfg__usb_tll_hs,
4297
-	&omap44xx_l4_wkup__wd_timer2,
4298
-	&omap44xx_l4_abe__wd_timer3,
4299
-	&omap44xx_l4_abe__wd_timer3_dma,
4300981 	&omap44xx_mpu__emif1,
4301982 	&omap44xx_mpu__emif2,
4302
-	&omap44xx_l3_main_2__aes1,
4303
-	&omap44xx_l3_main_2__aes2,
4304
-	&omap44xx_l3_main_2__des,
4305
-	&omap44xx_l3_main_2__sha0,
4306983 	NULL,
4307984 };
4308985