add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/mach-omap2/omap-smp.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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 /*
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  * OMAP4 SMP source file. It contains platform specific functions
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  * needed for the linux smp kernel.
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@@ -10,10 +11,6 @@
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  * Platform file needed for the OMAP4 SMP. This file is based on arm
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  * realview smp platform.
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  * * Copyright (c) 2002 ARM Limited.
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- *
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- * This program is free software; you can redistribute it and/or modify
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- * it under the terms of the GNU General Public License version 2 as
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- * published by the Free Software Foundation.
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  */
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 #include <linux/init.h>
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 #include <linux/device.h>
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@@ -69,15 +66,13 @@
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 	.startup_addr = omap5_secondary_startup,
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 };
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-static DEFINE_SPINLOCK(boot_lock);
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-
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 void __iomem *omap4_get_scu_base(void)
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 {
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 	return cfg.scu_base;
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 }
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 #ifdef CONFIG_OMAP5_ERRATA_801819
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-void omap5_erratum_workaround_801819(void)
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+static void omap5_erratum_workaround_801819(void)
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 {
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 	u32 acr, revidr;
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 	u32 acr_mask;
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@@ -173,12 +168,6 @@
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 		/* Enable ACR to allow for ICUALLU workaround */
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 		omap5_secondary_harden_predictor();
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 	}
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-
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-	/*
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-	 * Synchronise with the boot thread.
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-	 */
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-	spin_lock(&boot_lock);
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-	spin_unlock(&boot_lock);
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 }
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 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
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@@ -186,12 +175,6 @@
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 	static struct clockdomain *cpu1_clkdm;
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 	static bool booted;
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 	static struct powerdomain *cpu1_pwrdm;
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-
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-	/*
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-	 * Set synchronisation state between this boot processor
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-	 * and the secondary one
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-	 */
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-	spin_lock(&boot_lock);
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 	/*
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 	 * Update the AuxCoreBoot0 with boot state for secondary core.
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@@ -265,12 +248,6 @@
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 	}
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 	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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-
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-	/*
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-	 * Now the secondary core is starting up let it run its
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-	 * calibrations, then wait for it to finish
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-	 */
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-	spin_unlock(&boot_lock);
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 	return 0;
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 }