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2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2 
 kernel/arch/arm/mach-omap2/dma.c
....@@ -1,3 +1,4 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
12 /*
23  * OMAP2+ DMA driver
34  *
....@@ -12,13 +13,9 @@
1213  * Copyright (C) 2009 Texas Instruments
1314  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
1415  *
15
- * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
16
+ * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
1617  * Converted DMA library into platform driver
1718  *	- G, Manjunath Kondaiah <manjugk@ti.com>
18
- *
19
- * This program is free software; you can redistribute it and/or modify
20
- * it under the terms of the GNU General Public License version 2 as
21
- * published by the Free Software Foundation.
2219  */
2320 
2421 #include <linux/err.h>
....@@ -33,10 +30,6 @@
3330 #include <linux/omap-dma.h>
3431 
3532 #include "soc.h"
36
-#include "omap_hwmod.h"
37
-#include "omap_device.h"
38
-
39
-static enum omap_reg_offsets dma_common_ch_end;
4033 
4134 static const struct omap_dma_reg reg_map[] = {
4235 	[REVISION]	= { 0x0000, 0x00, OMAP_DMA_REG_32BIT },
....@@ -83,42 +76,6 @@
8376 	[CNDP]		= { 0x00d4, 0x60, OMAP_DMA_REG_32BIT },
8477 	[CCDN]		= { 0x00d8, 0x60, OMAP_DMA_REG_32BIT },
8578 };
86
-
87
-static void __iomem *dma_base;
88
-static inline void dma_write(u32 val, int reg, int lch)
89
-{
90
-	void __iomem *addr = dma_base;
91
-
92
-	addr += reg_map[reg].offset;
93
-	addr += reg_map[reg].stride * lch;
94
-
95
-	writel_relaxed(val, addr);
96
-}
97
-
98
-static inline u32 dma_read(int reg, int lch)
99
-{
100
-	void __iomem *addr = dma_base;
101
-
102
-	addr += reg_map[reg].offset;
103
-	addr += reg_map[reg].stride * lch;
104
-
105
-	return readl_relaxed(addr);
106
-}
107
-
108
-static void omap2_clear_dma(int lch)
109
-{
110
-	int i;
111
-
112
-	for (i = CSDP; i <= dma_common_ch_end; i += 1)
113
-		dma_write(0, i, lch);
114
-}
115
-
116
-static void omap2_show_dma_caps(void)
117
-{
118
-	u8 revision = dma_read(REVISION, 0) & 0xff;
119
-	printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
120
-				revision >> 4, revision & 0xf);
121
-}
12279 
12380 static unsigned configure_dma_errata(void)
12481 {
....@@ -214,82 +171,35 @@
214171 	{ "musb-hdrc.1.auto", "dmareq5", SDMA_FILTER_PARAM(64) }, /* OMAP2420 only */
215172 };
216173 
217
-static struct omap_system_dma_plat_info dma_plat_info __initdata = {
218
-	.reg_map	= reg_map,
219
-	.channel_stride	= 0x60,
220
-	.show_dma_caps	= omap2_show_dma_caps,
221
-	.clear_dma	= omap2_clear_dma,
222
-	.dma_write	= dma_write,
223
-	.dma_read	= dma_read,
174
+static struct omap_dma_dev_attr dma_attr = {
175
+	.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
176
+		    IS_CSSA_32 | IS_CDSA_32,
177
+	.lch_count = 32,
224178 };
225179 
226
-static struct platform_device_info omap_dma_dev_info __initdata = {
227
-	.name = "omap-dma-engine",
228
-	.id = -1,
229
-	.dma_mask = DMA_BIT_MASK(32),
180
+struct omap_system_dma_plat_info dma_plat_info = {
181
+	.reg_map	= reg_map,
182
+	.channel_stride	= 0x60,
183
+	.dma_attr	= &dma_attr,
230184 };
231185 
232186 /* One time initializations */
233
-static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
187
+static int __init omap2_system_dma_init(void)
234188 {
235
-	struct platform_device			*pdev;
236
-	struct omap_system_dma_plat_info	p;
237
-	struct omap_dma_dev_attr		*d;
238
-	struct resource				*mem;
239
-	char					*name = "omap_dma_system";
240
-
241
-	p = dma_plat_info;
242
-	p.dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
243
-	p.errata = configure_dma_errata();
189
+	dma_plat_info.errata = configure_dma_errata();
244190 
245191 	if (soc_is_omap24xx()) {
246192 		/* DMA slave map for drivers not yet converted to DT */
247
-		p.slave_map = omap24xx_sdma_dt_map;
248
-		p.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
193
+		dma_plat_info.slave_map = omap24xx_sdma_dt_map;
194
+		dma_plat_info.slavecnt = ARRAY_SIZE(omap24xx_sdma_dt_map);
249195 	}
250196 
251
-	pdev = omap_device_build(name, 0, oh, &p, sizeof(p));
252
-	if (IS_ERR(pdev)) {
253
-		pr_err("%s: Can't build omap_device for %s:%s.\n",
254
-			__func__, name, oh->name);
255
-		return PTR_ERR(pdev);
256
-	}
197
+	if (!soc_is_omap242x())
198
+		dma_attr.dev_caps |= IS_RW_PRIORITY;
257199 
258
-	omap_dma_dev_info.res = pdev->resource;
259
-	omap_dma_dev_info.num_res = pdev->num_resources;
260
-
261
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
262
-	if (!mem) {
263
-		dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
264
-		return -EINVAL;
265
-	}
266
-
267
-	dma_base = ioremap(mem->start, resource_size(mem));
268
-	if (!dma_base) {
269
-		dev_err(&pdev->dev, "%s: ioremap fail\n", __func__);
270
-		return -ENOMEM;
271
-	}
272
-
273
-	d = oh->dev_attr;
274
-
275
-	if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
276
-		d->dev_caps |= HS_CHANNELS_RESERVED;
277
-
278
-	if (platform_get_irq_byname(pdev, "0") < 0)
279
-		d->dev_caps |= DMA_ENGINE_HANDLE_IRQ;
280
-
281
-	/* Check the capabilities register for descriptor loading feature */
282
-	if (dma_read(CAPS_0, 0) & DMA_HAS_DESCRIPTOR_CAPS)
283
-		dma_common_ch_end = CCDN;
284
-	else
285
-		dma_common_ch_end = CCFN;
200
+	if (soc_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
201
+		dma_attr.dev_caps |= HS_CHANNELS_RESERVED;
286202 
287203 	return 0;
288
-}
289
-
290
-static int __init omap2_system_dma_init(void)
291
-{
292
-	return omap_hwmod_for_each_by_class("dma",
293
-			omap2_system_dma_init_dev, NULL);
294204 }
295205 omap_arch_initcall(omap2_system_dma_init);