add driver 5G

hc

2024-01-31 f9004dbfff8a3fbbd7e2a88c8a4327c7f2f8e5b2

 kernel/arch/arm/mach-omap2/Kconfig
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@@ -1,3 +1,4 @@
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+# SPDX-License-Identifier: GPL-2.0-only
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 menu "TI OMAP/AM/DM/DRA Family"
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 	depends on ARCH_MULTI_V6 || ARCH_MULTI_V7
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@@ -65,7 +66,6 @@
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 	select ARCH_OMAP2PLUS
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 	select ARM_GIC
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 	select MACH_OMAP_GENERIC
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-	select MIGHT_HAVE_CACHE_L2X0
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 	select HAVE_ARM_SCU
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 	select GENERIC_CLOCKEVENTS_BROADCAST
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 	select HAVE_ARM_TWD
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@@ -93,7 +93,7 @@
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 config ARCH_OMAP2PLUS
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 	bool
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 	select ARCH_HAS_BANDGAP
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-	select ARCH_HAS_HOLES_MEMORYMODEL
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+	select ARCH_HAS_RESET_CONTROLLER
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 	select ARCH_OMAP
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 	select CLKSRC_MMIO
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 	select GENERIC_IRQ_CHIP
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@@ -104,6 +104,9 @@
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 	select OMAP_DM_TIMER
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 	select OMAP_GPMC
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 	select PINCTRL
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+	select PM_GENERIC_DOMAINS if PM
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+	select PM_GENERIC_DOMAINS_OF if PM
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+	select RESET_CONTROLLER
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 	select SOC_BUS
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 	select TI_SYSC
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 	select OMAP_IRQCHIP
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@@ -223,7 +226,6 @@
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 config OMAP3_SDRC_AC_TIMING
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 	bool "Enable SDRC AC timing register changes"
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 	depends on ARCH_OMAP3
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-	default n
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 	help
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 	  If you know that none of your system initiators will attempt to
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 	  access SDRAM during CORE DVFS, select Y here.  This should boost